/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Machine Code Emitter                                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
    SmallVectorImpl<MCFixup> &Fixups,
    const MCSubtargetInfo &STI) const {
  static const uint64_t InstBits[] = {
    UINT64_C(1522540544),	// ABSWr
    UINT64_C(3670024192),	// ABSXr
    UINT64_C(68591616),	// ABS_ZPmZ_B
    UINT64_C(81174528),	// ABS_ZPmZ_D
    UINT64_C(72785920),	// ABS_ZPmZ_H
    UINT64_C(76980224),	// ABS_ZPmZ_S
    UINT64_C(67543040),	// ABS_ZPzZ_B
    UINT64_C(80125952),	// ABS_ZPzZ_D
    UINT64_C(71737344),	// ABS_ZPzZ_H
    UINT64_C(75931648),	// ABS_ZPzZ_S
    UINT64_C(1310767104),	// ABSv16i8
    UINT64_C(1591785472),	// ABSv1i64
    UINT64_C(245413888),	// ABSv2i32
    UINT64_C(1323350016),	// ABSv2i64
    UINT64_C(241219584),	// ABSv4i16
    UINT64_C(1319155712),	// ABSv4i32
    UINT64_C(1314961408),	// ABSv8i16
    UINT64_C(237025280),	// ABSv8i8
    UINT64_C(1161875456),	// ADCLB_ZZZ_D
    UINT64_C(1157681152),	// ADCLB_ZZZ_S
    UINT64_C(1161876480),	// ADCLT_ZZZ_D
    UINT64_C(1157682176),	// ADCLT_ZZZ_S
    UINT64_C(973078528),	// ADCSWr
    UINT64_C(3120562176),	// ADCSXr
    UINT64_C(436207616),	// ADCWr
    UINT64_C(2583691264),	// ADCXr
    UINT64_C(2441084928),	// ADDG
    UINT64_C(3234856960),	// ADDHA_MPPZ_D
    UINT64_C(3230662656),	// ADDHA_MPPZ_S
    UINT64_C(1163943936),	// ADDHNB_ZZZ_B
    UINT64_C(1168138240),	// ADDHNB_ZZZ_H
    UINT64_C(1172332544),	// ADDHNB_ZZZ_S
    UINT64_C(1163944960),	// ADDHNT_ZZZ_B
    UINT64_C(1168139264),	// ADDHNT_ZZZ_H
    UINT64_C(1172333568),	// ADDHNT_ZZZ_S
    UINT64_C(245383168),	// ADDHNv2i64_v2i32
    UINT64_C(1319124992),	// ADDHNv2i64_v4i32
    UINT64_C(241188864),	// ADDHNv4i32_v4i16
    UINT64_C(1314930688),	// ADDHNv4i32_v8i16
    UINT64_C(1310736384),	// ADDHNv8i16_v16i8
    UINT64_C(236994560),	// ADDHNv8i16_v8i8
    UINT64_C(73420800),	// ADDPL_XXI
    UINT64_C(2583699456),	// ADDPT_shift
    UINT64_C(1142005760),	// ADDP_ZPmZ_B
    UINT64_C(1154588672),	// ADDP_ZPmZ_D
    UINT64_C(1146200064),	// ADDP_ZPmZ_H
    UINT64_C(1150394368),	// ADDP_ZPmZ_S
    UINT64_C(1310768128),	// ADDPv16i8
    UINT64_C(245414912),	// ADDPv2i32
    UINT64_C(1323351040),	// ADDPv2i64
    UINT64_C(1592899584),	// ADDPv2i64p
    UINT64_C(241220608),	// ADDPv4i16
    UINT64_C(1319156736),	// ADDPv4i32
    UINT64_C(1314962432),	// ADDPv8i16
    UINT64_C(237026304),	// ADDPv8i8
    UINT64_C(69236736),	// ADDQP_ZZZ_B
    UINT64_C(81819648),	// ADDQP_ZZZ_D
    UINT64_C(73431040),	// ADDQP_ZZZ_H
    UINT64_C(77625344),	// ADDQP_ZZZ_S
    UINT64_C(67444736),	// ADDQV_VPZ_B
    UINT64_C(80027648),	// ADDQV_VPZ_D
    UINT64_C(71639040),	// ADDQV_VPZ_H
    UINT64_C(75833344),	// ADDQV_VPZ_S
    UINT64_C(73422848),	// ADDSPL_XXI
    UINT64_C(69237760),	// ADDSUBP_ZZZ_B
    UINT64_C(81820672),	// ADDSUBP_ZZZ_D
    UINT64_C(73432064),	// ADDSUBP_ZZZ_H
    UINT64_C(77626368),	// ADDSUBP_ZZZ_S
    UINT64_C(69228544),	// ADDSVL_XXI
    UINT64_C(822083584),	// ADDSWri
    UINT64_C(721420288),	// ADDSWrs
    UINT64_C(723517440),	// ADDSWrx
    UINT64_C(2969567232),	// ADDSXri
    UINT64_C(2868903936),	// ADDSXrs
    UINT64_C(2871001088),	// ADDSXrx
    UINT64_C(2871025664),	// ADDSXrx64
    UINT64_C(3234922496),	// ADDVA_MPPZ_D
    UINT64_C(3230728192),	// ADDVA_MPPZ_S
    UINT64_C(69226496),	// ADDVL_XXI
    UINT64_C(1311881216),	// ADDVv16i8v
    UINT64_C(242333696),	// ADDVv4i16v
    UINT64_C(1320269824),	// ADDVv4i32v
    UINT64_C(1316075520),	// ADDVv8i16v
    UINT64_C(238139392),	// ADDVv8i8v
    UINT64_C(285212672),	// ADDWri
    UINT64_C(184549376),	// ADDWrs
    UINT64_C(186646528),	// ADDWrx
    UINT64_C(2432696320),	// ADDXri
    UINT64_C(2332033024),	// ADDXrs
    UINT64_C(2334130176),	// ADDXrx
    UINT64_C(2334154752),	// ADDXrx64
    UINT64_C(3240141568),	// ADD_VG2_2ZZ_B
    UINT64_C(3252724480),	// ADD_VG2_2ZZ_D
    UINT64_C(3244335872),	// ADD_VG2_2ZZ_H
    UINT64_C(3248530176),	// ADD_VG2_2ZZ_S
    UINT64_C(3252688912),	// ADD_VG2_M2Z2Z_D
    UINT64_C(3248494608),	// ADD_VG2_M2Z2Z_S
    UINT64_C(3244300304),	// ADD_VG2_M2ZZ_D
    UINT64_C(3240106000),	// ADD_VG2_M2ZZ_S
    UINT64_C(3252689936),	// ADD_VG2_M2Z_D
    UINT64_C(3248495632),	// ADD_VG2_M2Z_S
    UINT64_C(3240143616),	// ADD_VG4_4ZZ_B
    UINT64_C(3252726528),	// ADD_VG4_4ZZ_D
    UINT64_C(3244337920),	// ADD_VG4_4ZZ_H
    UINT64_C(3248532224),	// ADD_VG4_4ZZ_S
    UINT64_C(3252754448),	// ADD_VG4_M4Z4Z_D
    UINT64_C(3248560144),	// ADD_VG4_M4Z4Z_S
    UINT64_C(3245348880),	// ADD_VG4_M4ZZ_D
    UINT64_C(3241154576),	// ADD_VG4_M4ZZ_S
    UINT64_C(3252755472),	// ADD_VG4_M4Z_D
    UINT64_C(3248561168),	// ADD_VG4_M4Z_S
    UINT64_C(622903296),	// ADD_ZI_B
    UINT64_C(635486208),	// ADD_ZI_D
    UINT64_C(627097600),	// ADD_ZI_H
    UINT64_C(631291904),	// ADD_ZI_S
    UINT64_C(67108864),	// ADD_ZPmZ_B
    UINT64_C(79953920),	// ADD_ZPmZ_CPA
    UINT64_C(79691776),	// ADD_ZPmZ_D
    UINT64_C(71303168),	// ADD_ZPmZ_H
    UINT64_C(75497472),	// ADD_ZPmZ_S
    UINT64_C(69206016),	// ADD_ZZZ_B
    UINT64_C(81790976),	// ADD_ZZZ_CPA
    UINT64_C(81788928),	// ADD_ZZZ_D
    UINT64_C(73400320),	// ADD_ZZZ_H
    UINT64_C(77594624),	// ADD_ZZZ_S
    UINT64_C(1310753792),	// ADDv16i8
    UINT64_C(1591772160),	// ADDv1i64
    UINT64_C(245400576),	// ADDv2i32
    UINT64_C(1323336704),	// ADDv2i64
    UINT64_C(241206272),	// ADDv4i16
    UINT64_C(1319142400),	// ADDv4i32
    UINT64_C(1314948096),	// ADDv8i16
    UINT64_C(237011968),	// ADDv8i8
    UINT64_C(268435456),	// ADR
    UINT64_C(2415919104),	// ADRP
    UINT64_C(81829888),	// ADR_LSL_ZZZ_D_0
    UINT64_C(81830912),	// ADR_LSL_ZZZ_D_1
    UINT64_C(81831936),	// ADR_LSL_ZZZ_D_2
    UINT64_C(81832960),	// ADR_LSL_ZZZ_D_3
    UINT64_C(77635584),	// ADR_LSL_ZZZ_S_0
    UINT64_C(77636608),	// ADR_LSL_ZZZ_S_1
    UINT64_C(77637632),	// ADR_LSL_ZZZ_S_2
    UINT64_C(77638656),	// ADR_LSL_ZZZ_S_3
    UINT64_C(69246976),	// ADR_SXTW_ZZZ_D_0
    UINT64_C(69248000),	// ADR_SXTW_ZZZ_D_1
    UINT64_C(69249024),	// ADR_SXTW_ZZZ_D_2
    UINT64_C(69250048),	// ADR_SXTW_ZZZ_D_3
    UINT64_C(73441280),	// ADR_UXTW_ZZZ_D_0
    UINT64_C(73442304),	// ADR_UXTW_ZZZ_D_1
    UINT64_C(73443328),	// ADR_UXTW_ZZZ_D_2
    UINT64_C(73444352),	// ADR_UXTW_ZZZ_D_3
    UINT64_C(1159982080),	// AESDIMC_2ZZI_B
    UINT64_C(1160244224),	// AESDIMC_4ZZI_B
    UINT64_C(1159916544),	// AESD_2ZZI_B
    UINT64_C(1160178688),	// AESD_4ZZI_B
    UINT64_C(1159914496),	// AESD_ZZZ_B
    UINT64_C(1311266816),	// AESDrr
    UINT64_C(1159981056),	// AESEMC_2ZZI_B
    UINT64_C(1160243200),	// AESEMC_4ZZI_B
    UINT64_C(1159915520),	// AESE_2ZZI_B
    UINT64_C(1160177664),	// AESE_4ZZI_B
    UINT64_C(1159913472),	// AESE_ZZZ_B
    UINT64_C(1311262720),	// AESErr
    UINT64_C(1159783424),	// AESIMC_ZZ_B
    UINT64_C(1311275008),	// AESIMCrr
    UINT64_C(1159782400),	// AESMC_ZZ_B
    UINT64_C(1311270912),	// AESMCrr
    UINT64_C(69083136),	// ANDQV_VPZ_B
    UINT64_C(81666048),	// ANDQV_VPZ_D
    UINT64_C(73277440),	// ANDQV_VPZ_H
    UINT64_C(77471744),	// ANDQV_VPZ_S
    UINT64_C(1912602624),	// ANDSWri
    UINT64_C(1778384896),	// ANDSWrs
    UINT64_C(4060086272),	// ANDSXri
    UINT64_C(3925868544),	// ANDSXrs
    UINT64_C(624967680),	// ANDS_PPzPP
    UINT64_C(68820992),	// ANDV_VPZ_B
    UINT64_C(81403904),	// ANDV_VPZ_D
    UINT64_C(73015296),	// ANDV_VPZ_H
    UINT64_C(77209600),	// ANDV_VPZ_S
    UINT64_C(301989888),	// ANDWri
    UINT64_C(167772160),	// ANDWrs
    UINT64_C(2449473536),	// ANDXri
    UINT64_C(2315255808),	// ANDXrs
    UINT64_C(620773376),	// AND_PPzPP
    UINT64_C(92274688),	// AND_ZI
    UINT64_C(68812800),	// AND_ZPmZ_B
    UINT64_C(81395712),	// AND_ZPmZ_D
    UINT64_C(73007104),	// AND_ZPmZ_H
    UINT64_C(77201408),	// AND_ZPmZ_S
    UINT64_C(69218304),	// AND_ZZZ
    UINT64_C(1310727168),	// ANDv16i8
    UINT64_C(236985344),	// ANDv8i8
    UINT64_C(3574493184),	// APAS
    UINT64_C(67404032),	// ASRD_ZPmI_B
    UINT64_C(75792384),	// ASRD_ZPmI_D
    UINT64_C(67404288),	// ASRD_ZPmI_H
    UINT64_C(71598080),	// ASRD_ZPmI_S
    UINT64_C(68452352),	// ASRR_ZPmZ_B
    UINT64_C(81035264),	// ASRR_ZPmZ_D
    UINT64_C(72646656),	// ASRR_ZPmZ_H
    UINT64_C(76840960),	// ASRR_ZPmZ_S
    UINT64_C(448800768),	// ASRVWr
    UINT64_C(2596284416),	// ASRVXr
    UINT64_C(68714496),	// ASR_WIDE_ZPmZ_B
    UINT64_C(72908800),	// ASR_WIDE_ZPmZ_H
    UINT64_C(77103104),	// ASR_WIDE_ZPmZ_S
    UINT64_C(69238784),	// ASR_WIDE_ZZZ_B
    UINT64_C(73433088),	// ASR_WIDE_ZZZ_H
    UINT64_C(77627392),	// ASR_WIDE_ZZZ_S
    UINT64_C(67141888),	// ASR_ZPmI_B
    UINT64_C(75530240),	// ASR_ZPmI_D
    UINT64_C(67142144),	// ASR_ZPmI_H
    UINT64_C(71335936),	// ASR_ZPmI_S
    UINT64_C(68190208),	// ASR_ZPmZ_B
    UINT64_C(80773120),	// ASR_ZPmZ_D
    UINT64_C(72384512),	// ASR_ZPmZ_H
    UINT64_C(76578816),	// ASR_ZPmZ_S
    UINT64_C(69767168),	// ASR_ZZI_B
    UINT64_C(77631488),	// ASR_ZZI_D
    UINT64_C(70291456),	// ASR_ZZI_H
    UINT64_C(73437184),	// ASR_ZZI_S
    UINT64_C(3670087680),	// AUTDA
    UINT64_C(3670088704),	// AUTDB
    UINT64_C(3670096864),	// AUTDZA
    UINT64_C(3670097888),	// AUTDZB
    UINT64_C(3670085632),	// AUTIA
    UINT64_C(3573752223),	// AUTIA1716
    UINT64_C(3670129662),	// AUTIA171615
    UINT64_C(3573752767),	// AUTIASP
    UINT64_C(4085252127),	// AUTIASPPCi
    UINT64_C(3670118430),	// AUTIASPPCr
    UINT64_C(3573752735),	// AUTIAZ
    UINT64_C(3670086656),	// AUTIB
    UINT64_C(3573752287),	// AUTIB1716
    UINT64_C(3670130686),	// AUTIB171615
    UINT64_C(3573752831),	// AUTIBSP
    UINT64_C(4087349279),	// AUTIBSPPCi
    UINT64_C(3670119454),	// AUTIBSPPCr
    UINT64_C(3573752799),	// AUTIBZ
    UINT64_C(3670094816),	// AUTIZA
    UINT64_C(3670095840),	// AUTIZB
    UINT64_C(3573563487),	// AXFLAG
    UINT64_C(335544320),	// B
    UINT64_C(3458203648),	// BCAX
    UINT64_C(73414656),	// BCAX_ZZZZ
    UINT64_C(1409286160),	// BCcc
    UINT64_C(1157673984),	// BDEP_ZZZ_B
    UINT64_C(1170256896),	// BDEP_ZZZ_D
    UINT64_C(1161868288),	// BDEP_ZZZ_H
    UINT64_C(1166062592),	// BDEP_ZZZ_S
    UINT64_C(1157672960),	// BEXT_ZZZ_B
    UINT64_C(1170255872),	// BEXT_ZZZ_D
    UINT64_C(1161867264),	// BEXT_ZZZ_H
    UINT64_C(1166061568),	// BEXT_ZZZ_S
    UINT64_C(255913984),	// BF16DOTlanev4bf16
    UINT64_C(1329655808),	// BF16DOTlanev8bf16
    UINT64_C(782333952),	// BF1CVTL
    UINT64_C(1856075776),	// BF1CVTL2
    UINT64_C(1695102976),	// BF1CVTLT_ZZ_BtoH
    UINT64_C(3244744705),	// BF1CVTL_2ZZ_BtoH
    UINT64_C(3244744704),	// BF1CVT_2ZZ_BtoH
    UINT64_C(1695037440),	// BF1CVT_ZZ_BtoH
    UINT64_C(786528256),	// BF2CVTL
    UINT64_C(1860270080),	// BF2CVTL2
    UINT64_C(1695104000),	// BF2CVTLT_ZZ_BtoH
    UINT64_C(3253133313),	// BF2CVTL_2ZZ_BtoH
    UINT64_C(3253133312),	// BF2CVT_2ZZ_BtoH
    UINT64_C(1695038464),	// BF2CVT_ZZ_BtoH
    UINT64_C(3252952064),	// BFADD_VG2_M2Z_H
    UINT64_C(3253017600),	// BFADD_VG4_M4Z_H
    UINT64_C(1694531584),	// BFADD_ZPmZZ
    UINT64_C(1694498816),	// BFADD_ZZZ
    UINT64_C(3240148992),	// BFCLAMP_VG2_2ZZZ_H
    UINT64_C(3240151040),	// BFCLAMP_VG4_4ZZZ_H
    UINT64_C(1679827968),	// BFCLAMP_ZZZ
    UINT64_C(509820928),	// BFCVT
    UINT64_C(245458944),	// BFCVTN
    UINT64_C(1319200768),	// BFCVTN2
    UINT64_C(1686806528),	// BFCVTNT_ZPmZ
    UINT64_C(1686282240),	// BFCVTNT_ZPzZ_StoH
    UINT64_C(1695168512),	// BFCVTN_Z2Z_HtoB
    UINT64_C(3244351520),	// BFCVTN_Z2Z_StoH
    UINT64_C(3244613632),	// BFCVT_Z2Z_HtoB
    UINT64_C(3244351488),	// BFCVT_Z2Z_StoH
    UINT64_C(1703583744),	// BFCVT_ZPmZ
    UINT64_C(1687863296),	// BFCVT_ZPzZ_StoH
    UINT64_C(3248492560),	// BFDOT_VG2_M2Z2Z_HtoS
    UINT64_C(3243249688),	// BFDOT_VG2_M2ZZI_HtoS
    UINT64_C(3240103952),	// BFDOT_VG2_M2ZZ_HtoS
    UINT64_C(3248558096),	// BFDOT_VG4_M4Z4Z_HtoS
    UINT64_C(3243282456),	// BFDOT_VG4_M4ZZI_HtoS
    UINT64_C(3241152528),	// BFDOT_VG4_M4ZZ_HtoS
    UINT64_C(1684029440),	// BFDOT_ZZI
    UINT64_C(1684045824),	// BFDOT_ZZZ
    UINT64_C(776010752),	// BFDOTv4bf16
    UINT64_C(1849752576),	// BFDOTv8bf16
    UINT64_C(3240145184),	// BFMAXNM_VG2_2Z2Z_H
    UINT64_C(3240141088),	// BFMAXNM_VG2_2ZZ_H
    UINT64_C(3240147232),	// BFMAXNM_VG4_4Z2Z_H
    UINT64_C(3240143136),	// BFMAXNM_VG4_4ZZ_H
    UINT64_C(1694793728),	// BFMAXNM_ZPmZZ
    UINT64_C(3240145152),	// BFMAX_VG2_2Z2Z_H
    UINT64_C(3240141056),	// BFMAX_VG2_2ZZ_H
    UINT64_C(3240147200),	// BFMAX_VG4_4Z2Z_H
    UINT64_C(3240143104),	// BFMAX_VG4_4ZZ_H
    UINT64_C(1694924800),	// BFMAX_ZPmZZ
    UINT64_C(3240145185),	// BFMINNM_VG2_2Z2Z_H
    UINT64_C(3240141089),	// BFMINNM_VG2_2ZZ_H
    UINT64_C(3240147233),	// BFMINNM_VG4_4Z2Z_H
    UINT64_C(3240143137),	// BFMINNM_VG4_4ZZ_H
    UINT64_C(1694859264),	// BFMINNM_ZPmZZ
    UINT64_C(3240145153),	// BFMIN_VG2_2Z2Z_H
    UINT64_C(3240141057),	// BFMIN_VG2_2ZZ_H
    UINT64_C(3240147201),	// BFMIN_VG4_4Z2Z_H
    UINT64_C(3240143105),	// BFMIN_VG4_4ZZ_H
    UINT64_C(1694990336),	// BFMIN_ZPmZZ
    UINT64_C(784399360),	// BFMLALB
    UINT64_C(264302592),	// BFMLALBIdx
    UINT64_C(1692434432),	// BFMLALB_ZZZ
    UINT64_C(1692418048),	// BFMLALB_ZZZI
    UINT64_C(1858141184),	// BFMLALT
    UINT64_C(1338044416),	// BFMLALTIdx
    UINT64_C(1692435456),	// BFMLALT_ZZZ
    UINT64_C(1692419072),	// BFMLALT_ZZZI
    UINT64_C(3246395408),	// BFMLAL_MZZI_HtoS
    UINT64_C(3240102928),	// BFMLAL_MZZ_HtoS
    UINT64_C(3248490512),	// BFMLAL_VG2_M2Z2Z_HtoS
    UINT64_C(3247443984),	// BFMLAL_VG2_M2ZZI_HtoS
    UINT64_C(3240101904),	// BFMLAL_VG2_M2ZZ_HtoS
    UINT64_C(3248556048),	// BFMLAL_VG4_M4Z4Z_HtoS
    UINT64_C(3247476752),	// BFMLAL_VG4_M4ZZI_HtoS
    UINT64_C(3241150480),	// BFMLAL_VG4_M4ZZ_HtoS
    UINT64_C(3252686856),	// BFMLA_VG2_M2Z2Z
    UINT64_C(3244301312),	// BFMLA_VG2_M2ZZ
    UINT64_C(3239055392),	// BFMLA_VG2_M2ZZI
    UINT64_C(3252752392),	// BFMLA_VG4_M4Z4Z
    UINT64_C(3245349888),	// BFMLA_VG4_M4ZZ
    UINT64_C(3239088160),	// BFMLA_VG4_M4ZZI
    UINT64_C(1696595968),	// BFMLA_ZPmZZ
    UINT64_C(1679820800),	// BFMLA_ZZZI
    UINT64_C(1692426240),	// BFMLSLB_ZZZI_S
    UINT64_C(1692442624),	// BFMLSLB_ZZZ_S
    UINT64_C(1692427264),	// BFMLSLT_ZZZI_S
    UINT64_C(1692443648),	// BFMLSLT_ZZZ_S
    UINT64_C(3246395416),	// BFMLSL_MZZI_HtoS
    UINT64_C(3240102936),	// BFMLSL_MZZ_HtoS
    UINT64_C(3248490520),	// BFMLSL_VG2_M2Z2Z_HtoS
    UINT64_C(3247443992),	// BFMLSL_VG2_M2ZZI_HtoS
    UINT64_C(3240101912),	// BFMLSL_VG2_M2ZZ_HtoS
    UINT64_C(3248556056),	// BFMLSL_VG4_M4Z4Z_HtoS
    UINT64_C(3247476760),	// BFMLSL_VG4_M4ZZI_HtoS
    UINT64_C(3241150488),	// BFMLSL_VG4_M4ZZ_HtoS
    UINT64_C(3252686872),	// BFMLS_VG2_M2Z2Z
    UINT64_C(3244301320),	// BFMLS_VG2_M2ZZ
    UINT64_C(3239055408),	// BFMLS_VG2_M2ZZI
    UINT64_C(3252752408),	// BFMLS_VG4_M4Z4Z
    UINT64_C(3245349896),	// BFMLS_VG4_M4ZZ
    UINT64_C(3239088176),	// BFMLS_VG4_M4ZZI
    UINT64_C(1696604160),	// BFMLS_ZPmZZ
    UINT64_C(1679821824),	// BFMLS_ZZZI
    UINT64_C(1849748480),	// BFMMLA
    UINT64_C(1692459008),	// BFMMLA_ZZZ_H
    UINT64_C(1684071424),	// BFMMLA_ZZZ_HtoS
    UINT64_C(2167407112),	// BFMOP4A_M2Z2Z_H
    UINT64_C(2165309952),	// BFMOP4A_M2Z2Z_S
    UINT64_C(2166358536),	// BFMOP4A_M2ZZ_H
    UINT64_C(2164261376),	// BFMOP4A_M2ZZ_S
    UINT64_C(2167406600),	// BFMOP4A_MZ2Z_H
    UINT64_C(2165309440),	// BFMOP4A_MZ2Z_S
    UINT64_C(2166358024),	// BFMOP4A_MZZ_H
    UINT64_C(2164260864),	// BFMOP4A_MZZ_S
    UINT64_C(2167407128),	// BFMOP4S_M2Z2Z_H
    UINT64_C(2165309968),	// BFMOP4S_M2Z2Z_S
    UINT64_C(2166358552),	// BFMOP4S_M2ZZ_H
    UINT64_C(2164261392),	// BFMOP4S_M2ZZ_S
    UINT64_C(2167406616),	// BFMOP4S_MZ2Z_H
    UINT64_C(2165309456),	// BFMOP4S_MZ2Z_S
    UINT64_C(2166358040),	// BFMOP4S_MZZ_H
    UINT64_C(2164260880),	// BFMOP4S_MZZ_S
    UINT64_C(2172649472),	// BFMOPA_MPPZZ
    UINT64_C(2174746632),	// BFMOPA_MPPZZ_H
    UINT64_C(2172649488),	// BFMOPS_MPPZZ
    UINT64_C(2174746648),	// BFMOPS_MPPZZ_H
    UINT64_C(3240158208),	// BFMUL_2Z2Z
    UINT64_C(3240159232),	// BFMUL_2ZZ
    UINT64_C(3240223744),	// BFMUL_4Z4Z
    UINT64_C(3240224768),	// BFMUL_4ZZ
    UINT64_C(1694662656),	// BFMUL_ZPmZZ
    UINT64_C(1694500864),	// BFMUL_ZZZ
    UINT64_C(1679828992),	// BFMUL_ZZZI
    UINT64_C(855638016),	// BFMWri
    UINT64_C(3007315968),	// BFMXri
    UINT64_C(3240145280),	// BFSCALE_2Z2Z
    UINT64_C(3240141184),	// BFSCALE_2ZZ
    UINT64_C(3240147328),	// BFSCALE_4Z4Z
    UINT64_C(3240143232),	// BFSCALE_4ZZ
    UINT64_C(1695121408),	// BFSCALE_ZPZZ_H
    UINT64_C(3252952072),	// BFSUB_VG2_M2Z_H
    UINT64_C(3253017608),	// BFSUB_VG4_M4Z_H
    UINT64_C(1694597120),	// BFSUB_ZPmZZ
    UINT64_C(1694499840),	// BFSUB_ZZZ
    UINT64_C(2170552328),	// BFTMOPA_M2ZZZI_HtoH
    UINT64_C(2168455168),	// BFTMOPA_M2ZZZI_HtoS
    UINT64_C(3243245592),	// BFVDOT_VG2_M2ZZI_HtoS
    UINT64_C(1157675008),	// BGRP_ZZZ_B
    UINT64_C(1170257920),	// BGRP_ZZZ_D
    UINT64_C(1161869312),	// BGRP_ZZZ_H
    UINT64_C(1166063616),	// BGRP_ZZZ_S
    UINT64_C(1780482048),	// BICSWrs
    UINT64_C(3927965696),	// BICSXrs
    UINT64_C(624967696),	// BICS_PPzPP
    UINT64_C(169869312),	// BICWrs
    UINT64_C(2317352960),	// BICXrs
    UINT64_C(620773392),	// BIC_PPzPP
    UINT64_C(68878336),	// BIC_ZPmZ_B
    UINT64_C(81461248),	// BIC_ZPmZ_D
    UINT64_C(73072640),	// BIC_ZPmZ_H
    UINT64_C(77266944),	// BIC_ZPmZ_S
    UINT64_C(81801216),	// BIC_ZZZ
    UINT64_C(1314921472),	// BICv16i8
    UINT64_C(788534272),	// BICv2i32
    UINT64_C(788567040),	// BICv4i16
    UINT64_C(1862276096),	// BICv4i32
    UINT64_C(1862308864),	// BICv8i16
    UINT64_C(241179648),	// BICv8i8
    UINT64_C(1860180992),	// BIFv16i8
    UINT64_C(786439168),	// BIFv8i8
    UINT64_C(1855986688),	// BITv16i8
    UINT64_C(782244864),	// BITv8i8
    UINT64_C(2483027968),	// BL
    UINT64_C(3594452992),	// BLR
    UINT64_C(3611232256),	// BLRAA
    UINT64_C(3594455071),	// BLRAAZ
    UINT64_C(3611233280),	// BLRAB
    UINT64_C(3594456095),	// BLRABZ
    UINT64_C(2155872264),	// BMOPA_MPPZZ_S
    UINT64_C(2155872280),	// BMOPS_MPPZZ_S
    UINT64_C(3592355840),	// BR
    UINT64_C(3609135104),	// BRAA
    UINT64_C(3592357919),	// BRAAZ
    UINT64_C(3609136128),	// BRAB
    UINT64_C(3592358943),	// BRABZ
    UINT64_C(3574166175),	// BRB_IALL
    UINT64_C(3574166207),	// BRB_INJ
    UINT64_C(3558866944),	// BRK
    UINT64_C(626016256),	// BRKAS_PPzP
    UINT64_C(621821968),	// BRKA_PPmP
    UINT64_C(621821952),	// BRKA_PPzP
    UINT64_C(634404864),	// BRKBS_PPzP
    UINT64_C(630210576),	// BRKB_PPmP
    UINT64_C(630210560),	// BRKB_PPzP
    UINT64_C(626540544),	// BRKNS_PPzP
    UINT64_C(622346240),	// BRKN_PPzP
    UINT64_C(625000448),	// BRKPAS_PPzPP
    UINT64_C(620806144),	// BRKPA_PPzPP
    UINT64_C(625000464),	// BRKPBS_PPzPP
    UINT64_C(620806160),	// BRKPB_PPzPP
    UINT64_C(73415680),	// BSL1N_ZZZZ
    UINT64_C(77609984),	// BSL2N_ZZZZ
    UINT64_C(69221376),	// BSL_ZZZZ
    UINT64_C(1851792384),	// BSLv16i8
    UINT64_C(778050560),	// BSLv8i8
    UINT64_C(1409286144),	// Bcc
    UINT64_C(1157683200),	// CADD_ZZI_B
    UINT64_C(1170266112),	// CADD_ZZI_D
    UINT64_C(1161877504),	// CADD_ZZI_H
    UINT64_C(1166071808),	// CADD_ZZI_S
    UINT64_C(148929536),	// CASAB
    UINT64_C(1222671360),	// CASAH
    UINT64_C(148962304),	// CASALB
    UINT64_C(1222704128),	// CASALH
    UINT64_C(3384867840),	// CASALTX
    UINT64_C(2296445952),	// CASALW
    UINT64_C(3370187776),	// CASALX
    UINT64_C(3384835072),	// CASATX
    UINT64_C(2296413184),	// CASAW
    UINT64_C(3370155008),	// CASAX
    UINT64_C(144735232),	// CASB
    UINT64_C(1218477056),	// CASH
    UINT64_C(144768000),	// CASLB
    UINT64_C(1218509824),	// CASLH
    UINT64_C(3380673536),	// CASLTX
    UINT64_C(2292251648),	// CASLW
    UINT64_C(3365993472),	// CASLX
    UINT64_C(1237384192),	// CASPALTX
    UINT64_C(140573696),	// CASPALW
    UINT64_C(1214315520),	// CASPALX
    UINT64_C(1237351424),	// CASPATX
    UINT64_C(140540928),	// CASPAW
    UINT64_C(1214282752),	// CASPAX
    UINT64_C(1233189888),	// CASPLTX
    UINT64_C(136379392),	// CASPLW
    UINT64_C(1210121216),	// CASPLX
    UINT64_C(1233157120),	// CASPTX
    UINT64_C(136346624),	// CASPW
    UINT64_C(1210088448),	// CASPX
    UINT64_C(3380640768),	// CASTX
    UINT64_C(2292218880),	// CASW
    UINT64_C(3365960704),	// CASX
    UINT64_C(1958772736),	// CBBEQWrr
    UINT64_C(1948286976),	// CBBGEWrr
    UINT64_C(1946189824),	// CBBGTWrr
    UINT64_C(1950384128),	// CBBHIWrr
    UINT64_C(1952481280),	// CBBHSWrr
    UINT64_C(1960869888),	// CBBNEWrr
    UINT64_C(1975517184),	// CBEQWri
    UINT64_C(1958739968),	// CBEQWrr
    UINT64_C(4123000832),	// CBEQXri
    UINT64_C(4106223616),	// CBEQXrr
    UINT64_C(1948254208),	// CBGEWrr
    UINT64_C(4095737856),	// CBGEXrr
    UINT64_C(1962934272),	// CBGTWri
    UINT64_C(1946157056),	// CBGTWrr
    UINT64_C(4110417920),	// CBGTXri
    UINT64_C(4093640704),	// CBGTXrr
    UINT64_C(1958789120),	// CBHEQWrr
    UINT64_C(1948303360),	// CBHGEWrr
    UINT64_C(1946206208),	// CBHGTWrr
    UINT64_C(1950400512),	// CBHHIWrr
    UINT64_C(1952497664),	// CBHHSWrr
    UINT64_C(1967128576),	// CBHIWri
    UINT64_C(1950351360),	// CBHIWrr
    UINT64_C(4114612224),	// CBHIXri
    UINT64_C(4097835008),	// CBHIXrr
    UINT64_C(1960886272),	// CBHNEWrr
    UINT64_C(1952448512),	// CBHSWrr
    UINT64_C(4099932160),	// CBHSXrr
    UINT64_C(1969225728),	// CBLOWri
    UINT64_C(4116709376),	// CBLOXri
    UINT64_C(1965031424),	// CBLTWri
    UINT64_C(4112515072),	// CBLTXri
    UINT64_C(1977614336),	// CBNEWri
    UINT64_C(1960837120),	// CBNEWrr
    UINT64_C(4125097984),	// CBNEXri
    UINT64_C(4108320768),	// CBNEXrr
    UINT64_C(889192448),	// CBNZW
    UINT64_C(3036676096),	// CBNZX
    UINT64_C(872415232),	// CBZW
    UINT64_C(3019898880),	// CBZX
    UINT64_C(977274880),	// CCMNWi
    UINT64_C(977272832),	// CCMNWr
    UINT64_C(3124758528),	// CCMNXi
    UINT64_C(3124756480),	// CCMNXr
    UINT64_C(2051016704),	// CCMPWi
    UINT64_C(2051014656),	// CCMPWr
    UINT64_C(4198500352),	// CCMPXi
    UINT64_C(4198498304),	// CCMPXr
    UINT64_C(1155547136),	// CDOT_ZZZI_D
    UINT64_C(1151352832),	// CDOT_ZZZI_S
    UINT64_C(1153437696),	// CDOT_ZZZ_D
    UINT64_C(1149243392),	// CDOT_ZZZ_S
    UINT64_C(3573563423),	// CFINV
    UINT64_C(3573753119),	// CHKFEAT
    UINT64_C(87072768),	// CLASTA_RPZ_B
    UINT64_C(99655680),	// CLASTA_RPZ_D
    UINT64_C(91267072),	// CLASTA_RPZ_H
    UINT64_C(95461376),	// CLASTA_RPZ_S
    UINT64_C(86671360),	// CLASTA_VPZ_B
    UINT64_C(99254272),	// CLASTA_VPZ_D
    UINT64_C(90865664),	// CLASTA_VPZ_H
    UINT64_C(95059968),	// CLASTA_VPZ_S
    UINT64_C(86540288),	// CLASTA_ZPZ_B
    UINT64_C(99123200),	// CLASTA_ZPZ_D
    UINT64_C(90734592),	// CLASTA_ZPZ_H
    UINT64_C(94928896),	// CLASTA_ZPZ_S
    UINT64_C(87138304),	// CLASTB_RPZ_B
    UINT64_C(99721216),	// CLASTB_RPZ_D
    UINT64_C(91332608),	// CLASTB_RPZ_H
    UINT64_C(95526912),	// CLASTB_RPZ_S
    UINT64_C(86736896),	// CLASTB_VPZ_B
    UINT64_C(99319808),	// CLASTB_VPZ_D
    UINT64_C(90931200),	// CLASTB_VPZ_H
    UINT64_C(95125504),	// CLASTB_VPZ_S
    UINT64_C(86605824),	// CLASTB_ZPZ_B
    UINT64_C(99188736),	// CLASTB_ZPZ_D
    UINT64_C(90800128),	// CLASTB_ZPZ_H
    UINT64_C(94994432),	// CLASTB_ZPZ_S
    UINT64_C(3573755999),	// CLREX
    UINT64_C(1522537472),	// CLSWr
    UINT64_C(3670021120),	// CLSXr
    UINT64_C(68722688),	// CLS_ZPmZ_B
    UINT64_C(81305600),	// CLS_ZPmZ_D
    UINT64_C(72916992),	// CLS_ZPmZ_H
    UINT64_C(77111296),	// CLS_ZPmZ_S
    UINT64_C(67674112),	// CLS_ZPzZ_B
    UINT64_C(80257024),	// CLS_ZPzZ_D
    UINT64_C(71868416),	// CLS_ZPzZ_H
    UINT64_C(76062720),	// CLS_ZPzZ_S
    UINT64_C(1310738432),	// CLSv16i8
    UINT64_C(245385216),	// CLSv2i32
    UINT64_C(241190912),	// CLSv4i16
    UINT64_C(1319127040),	// CLSv4i32
    UINT64_C(1314932736),	// CLSv8i16
    UINT64_C(236996608),	// CLSv8i8
    UINT64_C(1522536448),	// CLZWr
    UINT64_C(3670020096),	// CLZXr
    UINT64_C(68788224),	// CLZ_ZPmZ_B
    UINT64_C(81371136),	// CLZ_ZPmZ_D
    UINT64_C(72982528),	// CLZ_ZPmZ_H
    UINT64_C(77176832),	// CLZ_ZPmZ_S
    UINT64_C(67739648),	// CLZ_ZPzZ_B
    UINT64_C(80322560),	// CLZ_ZPzZ_D
    UINT64_C(71933952),	// CLZ_ZPzZ_H
    UINT64_C(76128256),	// CLZ_ZPzZ_S
    UINT64_C(1847609344),	// CLZv16i8
    UINT64_C(782256128),	// CLZv2i32
    UINT64_C(778061824),	// CLZv4i16
    UINT64_C(1855997952),	// CLZv4i32
    UINT64_C(1851803648),	// CLZv8i16
    UINT64_C(773867520),	// CLZv8i8
    UINT64_C(1847626752),	// CMEQv16i8
    UINT64_C(1310758912),	// CMEQv16i8rz
    UINT64_C(2128645120),	// CMEQv1i64
    UINT64_C(1591777280),	// CMEQv1i64rz
    UINT64_C(782273536),	// CMEQv2i32
    UINT64_C(245405696),	// CMEQv2i32rz
    UINT64_C(1860209664),	// CMEQv2i64
    UINT64_C(1323341824),	// CMEQv2i64rz
    UINT64_C(778079232),	// CMEQv4i16
    UINT64_C(241211392),	// CMEQv4i16rz
    UINT64_C(1856015360),	// CMEQv4i32
    UINT64_C(1319147520),	// CMEQv4i32rz
    UINT64_C(1851821056),	// CMEQv8i16
    UINT64_C(1314953216),	// CMEQv8i16rz
    UINT64_C(773884928),	// CMEQv8i8
    UINT64_C(237017088),	// CMEQv8i8rz
    UINT64_C(1310735360),	// CMGEv16i8
    UINT64_C(1847625728),	// CMGEv16i8rz
    UINT64_C(1591753728),	// CMGEv1i64
    UINT64_C(2128644096),	// CMGEv1i64rz
    UINT64_C(245382144),	// CMGEv2i32
    UINT64_C(782272512),	// CMGEv2i32rz
    UINT64_C(1323318272),	// CMGEv2i64
    UINT64_C(1860208640),	// CMGEv2i64rz
    UINT64_C(241187840),	// CMGEv4i16
    UINT64_C(778078208),	// CMGEv4i16rz
    UINT64_C(1319123968),	// CMGEv4i32
    UINT64_C(1856014336),	// CMGEv4i32rz
    UINT64_C(1314929664),	// CMGEv8i16
    UINT64_C(1851820032),	// CMGEv8i16rz
    UINT64_C(236993536),	// CMGEv8i8
    UINT64_C(773883904),	// CMGEv8i8rz
    UINT64_C(1310733312),	// CMGTv16i8
    UINT64_C(1310754816),	// CMGTv16i8rz
    UINT64_C(1591751680),	// CMGTv1i64
    UINT64_C(1591773184),	// CMGTv1i64rz
    UINT64_C(245380096),	// CMGTv2i32
    UINT64_C(245401600),	// CMGTv2i32rz
    UINT64_C(1323316224),	// CMGTv2i64
    UINT64_C(1323337728),	// CMGTv2i64rz
    UINT64_C(241185792),	// CMGTv4i16
    UINT64_C(241207296),	// CMGTv4i16rz
    UINT64_C(1319121920),	// CMGTv4i32
    UINT64_C(1319143424),	// CMGTv4i32rz
    UINT64_C(1314927616),	// CMGTv8i16
    UINT64_C(1314949120),	// CMGTv8i16rz
    UINT64_C(236991488),	// CMGTv8i8
    UINT64_C(237012992),	// CMGTv8i8rz
    UINT64_C(1847604224),	// CMHIv16i8
    UINT64_C(2128622592),	// CMHIv1i64
    UINT64_C(782251008),	// CMHIv2i32
    UINT64_C(1860187136),	// CMHIv2i64
    UINT64_C(778056704),	// CMHIv4i16
    UINT64_C(1855992832),	// CMHIv4i32
    UINT64_C(1851798528),	// CMHIv8i16
    UINT64_C(773862400),	// CMHIv8i8
    UINT64_C(1847606272),	// CMHSv16i8
    UINT64_C(2128624640),	// CMHSv1i64
    UINT64_C(782253056),	// CMHSv2i32
    UINT64_C(1860189184),	// CMHSv2i64
    UINT64_C(778058752),	// CMHSv4i16
    UINT64_C(1855994880),	// CMHSv4i32
    UINT64_C(1851800576),	// CMHSv8i16
    UINT64_C(773864448),	// CMHSv8i8
    UINT64_C(1151361024),	// CMLA_ZZZI_H
    UINT64_C(1155555328),	// CMLA_ZZZI_S
    UINT64_C(1140858880),	// CMLA_ZZZ_B
    UINT64_C(1153441792),	// CMLA_ZZZ_D
    UINT64_C(1145053184),	// CMLA_ZZZ_H
    UINT64_C(1149247488),	// CMLA_ZZZ_S
    UINT64_C(1847629824),	// CMLEv16i8rz
    UINT64_C(2128648192),	// CMLEv1i64rz
    UINT64_C(782276608),	// CMLEv2i32rz
    UINT64_C(1860212736),	// CMLEv2i64rz
    UINT64_C(778082304),	// CMLEv4i16rz
    UINT64_C(1856018432),	// CMLEv4i32rz
    UINT64_C(1851824128),	// CMLEv8i16rz
    UINT64_C(773888000),	// CMLEv8i8rz
    UINT64_C(1310763008),	// CMLTv16i8rz
    UINT64_C(1591781376),	// CMLTv1i64rz
    UINT64_C(245409792),	// CMLTv2i32rz
    UINT64_C(1323345920),	// CMLTv2i64rz
    UINT64_C(241215488),	// CMLTv4i16rz
    UINT64_C(1319151616),	// CMLTv4i32rz
    UINT64_C(1314957312),	// CMLTv8i16rz
    UINT64_C(237021184),	// CMLTv8i8rz
    UINT64_C(620789760),	// CMPEQ_PPzZI_B
    UINT64_C(633372672),	// CMPEQ_PPzZI_D
    UINT64_C(624984064),	// CMPEQ_PPzZI_H
    UINT64_C(629178368),	// CMPEQ_PPzZI_S
    UINT64_C(604020736),	// CMPEQ_PPzZZ_B
    UINT64_C(616603648),	// CMPEQ_PPzZZ_D
    UINT64_C(608215040),	// CMPEQ_PPzZZ_H
    UINT64_C(612409344),	// CMPEQ_PPzZZ_S
    UINT64_C(603987968),	// CMPEQ_WIDE_PPzZZ_B
    UINT64_C(608182272),	// CMPEQ_WIDE_PPzZZ_H
    UINT64_C(612376576),	// CMPEQ_WIDE_PPzZZ_S
    UINT64_C(620756992),	// CMPGE_PPzZI_B
    UINT64_C(633339904),	// CMPGE_PPzZI_D
    UINT64_C(624951296),	// CMPGE_PPzZI_H
    UINT64_C(629145600),	// CMPGE_PPzZI_S
    UINT64_C(604012544),	// CMPGE_PPzZZ_B
    UINT64_C(616595456),	// CMPGE_PPzZZ_D
    UINT64_C(608206848),	// CMPGE_PPzZZ_H
    UINT64_C(612401152),	// CMPGE_PPzZZ_S
    UINT64_C(603996160),	// CMPGE_WIDE_PPzZZ_B
    UINT64_C(608190464),	// CMPGE_WIDE_PPzZZ_H
    UINT64_C(612384768),	// CMPGE_WIDE_PPzZZ_S
    UINT64_C(620757008),	// CMPGT_PPzZI_B
    UINT64_C(633339920),	// CMPGT_PPzZI_D
    UINT64_C(624951312),	// CMPGT_PPzZI_H
    UINT64_C(629145616),	// CMPGT_PPzZI_S
    UINT64_C(604012560),	// CMPGT_PPzZZ_B
    UINT64_C(616595472),	// CMPGT_PPzZZ_D
    UINT64_C(608206864),	// CMPGT_PPzZZ_H
    UINT64_C(612401168),	// CMPGT_PPzZZ_S
    UINT64_C(603996176),	// CMPGT_WIDE_PPzZZ_B
    UINT64_C(608190480),	// CMPGT_WIDE_PPzZZ_H
    UINT64_C(612384784),	// CMPGT_WIDE_PPzZZ_S
    UINT64_C(606076944),	// CMPHI_PPzZI_B
    UINT64_C(618659856),	// CMPHI_PPzZI_D
    UINT64_C(610271248),	// CMPHI_PPzZI_H
    UINT64_C(614465552),	// CMPHI_PPzZI_S
    UINT64_C(603979792),	// CMPHI_PPzZZ_B
    UINT64_C(616562704),	// CMPHI_PPzZZ_D
    UINT64_C(608174096),	// CMPHI_PPzZZ_H
    UINT64_C(612368400),	// CMPHI_PPzZZ_S
    UINT64_C(604028944),	// CMPHI_WIDE_PPzZZ_B
    UINT64_C(608223248),	// CMPHI_WIDE_PPzZZ_H
    UINT64_C(612417552),	// CMPHI_WIDE_PPzZZ_S
    UINT64_C(606076928),	// CMPHS_PPzZI_B
    UINT64_C(618659840),	// CMPHS_PPzZI_D
    UINT64_C(610271232),	// CMPHS_PPzZI_H
    UINT64_C(614465536),	// CMPHS_PPzZI_S
    UINT64_C(603979776),	// CMPHS_PPzZZ_B
    UINT64_C(616562688),	// CMPHS_PPzZZ_D
    UINT64_C(608174080),	// CMPHS_PPzZZ_H
    UINT64_C(612368384),	// CMPHS_PPzZZ_S
    UINT64_C(604028928),	// CMPHS_WIDE_PPzZZ_B
    UINT64_C(608223232),	// CMPHS_WIDE_PPzZZ_H
    UINT64_C(612417536),	// CMPHS_WIDE_PPzZZ_S
    UINT64_C(620765200),	// CMPLE_PPzZI_B
    UINT64_C(633348112),	// CMPLE_PPzZI_D
    UINT64_C(624959504),	// CMPLE_PPzZI_H
    UINT64_C(629153808),	// CMPLE_PPzZI_S
    UINT64_C(604004368),	// CMPLE_WIDE_PPzZZ_B
    UINT64_C(608198672),	// CMPLE_WIDE_PPzZZ_H
    UINT64_C(612392976),	// CMPLE_WIDE_PPzZZ_S
    UINT64_C(606085120),	// CMPLO_PPzZI_B
    UINT64_C(618668032),	// CMPLO_PPzZI_D
    UINT64_C(610279424),	// CMPLO_PPzZI_H
    UINT64_C(614473728),	// CMPLO_PPzZI_S
    UINT64_C(604037120),	// CMPLO_WIDE_PPzZZ_B
    UINT64_C(608231424),	// CMPLO_WIDE_PPzZZ_H
    UINT64_C(612425728),	// CMPLO_WIDE_PPzZZ_S
    UINT64_C(606085136),	// CMPLS_PPzZI_B
    UINT64_C(618668048),	// CMPLS_PPzZI_D
    UINT64_C(610279440),	// CMPLS_PPzZI_H
    UINT64_C(614473744),	// CMPLS_PPzZI_S
    UINT64_C(604037136),	// CMPLS_WIDE_PPzZZ_B
    UINT64_C(608231440),	// CMPLS_WIDE_PPzZZ_H
    UINT64_C(612425744),	// CMPLS_WIDE_PPzZZ_S
    UINT64_C(620765184),	// CMPLT_PPzZI_B
    UINT64_C(633348096),	// CMPLT_PPzZI_D
    UINT64_C(624959488),	// CMPLT_PPzZI_H
    UINT64_C(629153792),	// CMPLT_PPzZI_S
    UINT64_C(604004352),	// CMPLT_WIDE_PPzZZ_B
    UINT64_C(608198656),	// CMPLT_WIDE_PPzZZ_H
    UINT64_C(612392960),	// CMPLT_WIDE_PPzZZ_S
    UINT64_C(620789776),	// CMPNE_PPzZI_B
    UINT64_C(633372688),	// CMPNE_PPzZI_D
    UINT64_C(624984080),	// CMPNE_PPzZI_H
    UINT64_C(629178384),	// CMPNE_PPzZI_S
    UINT64_C(604020752),	// CMPNE_PPzZZ_B
    UINT64_C(616603664),	// CMPNE_PPzZZ_D
    UINT64_C(608215056),	// CMPNE_PPzZZ_H
    UINT64_C(612409360),	// CMPNE_PPzZZ_S
    UINT64_C(603987984),	// CMPNE_WIDE_PPzZZ_B
    UINT64_C(608182288),	// CMPNE_WIDE_PPzZZ_H
    UINT64_C(612376592),	// CMPNE_WIDE_PPzZZ_S
    UINT64_C(1310755840),	// CMTSTv16i8
    UINT64_C(1591774208),	// CMTSTv1i64
    UINT64_C(245402624),	// CMTSTv2i32
    UINT64_C(1323338752),	// CMTSTv2i64
    UINT64_C(241208320),	// CMTSTv4i16
    UINT64_C(1319144448),	// CMTSTv4i32
    UINT64_C(1314950144),	// CMTSTv8i16
    UINT64_C(237014016),	// CMTSTv8i8
    UINT64_C(68919296),	// CNOT_ZPmZ_B
    UINT64_C(81502208),	// CNOT_ZPmZ_D
    UINT64_C(73113600),	// CNOT_ZPmZ_H
    UINT64_C(77307904),	// CNOT_ZPmZ_S
    UINT64_C(67870720),	// CNOT_ZPzZ_B
    UINT64_C(80453632),	// CNOT_ZPzZ_D
    UINT64_C(72065024),	// CNOT_ZPzZ_H
    UINT64_C(76259328),	// CNOT_ZPzZ_S
    UINT64_C(69263360),	// CNTB_XPiI
    UINT64_C(81846272),	// CNTD_XPiI
    UINT64_C(73457664),	// CNTH_XPiI
    UINT64_C(622887424),	// CNTP_XCI_B
    UINT64_C(635470336),	// CNTP_XCI_D
    UINT64_C(627081728),	// CNTP_XCI_H
    UINT64_C(631276032),	// CNTP_XCI_S
    UINT64_C(622886912),	// CNTP_XPP_B
    UINT64_C(635469824),	// CNTP_XPP_D
    UINT64_C(627081216),	// CNTP_XPP_H
    UINT64_C(631275520),	// CNTP_XPP_S
    UINT64_C(77651968),	// CNTW_XPiI
    UINT64_C(1522539520),	// CNTWr
    UINT64_C(3670023168),	// CNTXr
    UINT64_C(68853760),	// CNT_ZPmZ_B
    UINT64_C(81436672),	// CNT_ZPmZ_D
    UINT64_C(73048064),	// CNT_ZPmZ_H
    UINT64_C(77242368),	// CNT_ZPmZ_S
    UINT64_C(67805184),	// CNT_ZPzZ_B
    UINT64_C(80388096),	// CNT_ZPzZ_D
    UINT64_C(71999488),	// CNT_ZPzZ_H
    UINT64_C(76193792),	// CNT_ZPzZ_S
    UINT64_C(1310742528),	// CNTv16i8
    UINT64_C(237000704),	// CNTv8i8
    UINT64_C(86081536),	// COMPACT_ZPZ_B
    UINT64_C(98664448),	// COMPACT_ZPZ_D
    UINT64_C(90275840),	// COMPACT_ZPZ_H
    UINT64_C(94470144),	// COMPACT_ZPZ_S
    UINT64_C(494928896),	// CPYE
    UINT64_C(494978048),	// CPYEN
    UINT64_C(494961664),	// CPYERN
    UINT64_C(494937088),	// CPYERT
    UINT64_C(494986240),	// CPYERTN
    UINT64_C(494969856),	// CPYERTRN
    UINT64_C(494953472),	// CPYERTWN
    UINT64_C(494941184),	// CPYET
    UINT64_C(494990336),	// CPYETN
    UINT64_C(494973952),	// CPYETRN
    UINT64_C(494957568),	// CPYETWN
    UINT64_C(494945280),	// CPYEWN
    UINT64_C(494932992),	// CPYEWT
    UINT64_C(494982144),	// CPYEWTN
    UINT64_C(494965760),	// CPYEWTRN
    UINT64_C(494949376),	// CPYEWTWN
    UINT64_C(427820032),	// CPYFE
    UINT64_C(427869184),	// CPYFEN
    UINT64_C(427852800),	// CPYFERN
    UINT64_C(427828224),	// CPYFERT
    UINT64_C(427877376),	// CPYFERTN
    UINT64_C(427860992),	// CPYFERTRN
    UINT64_C(427844608),	// CPYFERTWN
    UINT64_C(427832320),	// CPYFET
    UINT64_C(427881472),	// CPYFETN
    UINT64_C(427865088),	// CPYFETRN
    UINT64_C(427848704),	// CPYFETWN
    UINT64_C(427836416),	// CPYFEWN
    UINT64_C(427824128),	// CPYFEWT
    UINT64_C(427873280),	// CPYFEWTN
    UINT64_C(427856896),	// CPYFEWTRN
    UINT64_C(427840512),	// CPYFEWTWN
    UINT64_C(423625728),	// CPYFM
    UINT64_C(423674880),	// CPYFMN
    UINT64_C(423658496),	// CPYFMRN
    UINT64_C(423633920),	// CPYFMRT
    UINT64_C(423683072),	// CPYFMRTN
    UINT64_C(423666688),	// CPYFMRTRN
    UINT64_C(423650304),	// CPYFMRTWN
    UINT64_C(423638016),	// CPYFMT
    UINT64_C(423687168),	// CPYFMTN
    UINT64_C(423670784),	// CPYFMTRN
    UINT64_C(423654400),	// CPYFMTWN
    UINT64_C(423642112),	// CPYFMWN
    UINT64_C(423629824),	// CPYFMWT
    UINT64_C(423678976),	// CPYFMWTN
    UINT64_C(423662592),	// CPYFMWTRN
    UINT64_C(423646208),	// CPYFMWTWN
    UINT64_C(419431424),	// CPYFP
    UINT64_C(419480576),	// CPYFPN
    UINT64_C(419464192),	// CPYFPRN
    UINT64_C(419439616),	// CPYFPRT
    UINT64_C(419488768),	// CPYFPRTN
    UINT64_C(419472384),	// CPYFPRTRN
    UINT64_C(419456000),	// CPYFPRTWN
    UINT64_C(419443712),	// CPYFPT
    UINT64_C(419492864),	// CPYFPTN
    UINT64_C(419476480),	// CPYFPTRN
    UINT64_C(419460096),	// CPYFPTWN
    UINT64_C(419447808),	// CPYFPWN
    UINT64_C(419435520),	// CPYFPWT
    UINT64_C(419484672),	// CPYFPWTN
    UINT64_C(419468288),	// CPYFPWTRN
    UINT64_C(419451904),	// CPYFPWTWN
    UINT64_C(490734592),	// CPYM
    UINT64_C(490783744),	// CPYMN
    UINT64_C(490767360),	// CPYMRN
    UINT64_C(490742784),	// CPYMRT
    UINT64_C(490791936),	// CPYMRTN
    UINT64_C(490775552),	// CPYMRTRN
    UINT64_C(490759168),	// CPYMRTWN
    UINT64_C(490746880),	// CPYMT
    UINT64_C(490796032),	// CPYMTN
    UINT64_C(490779648),	// CPYMTRN
    UINT64_C(490763264),	// CPYMTWN
    UINT64_C(490750976),	// CPYMWN
    UINT64_C(490738688),	// CPYMWT
    UINT64_C(490787840),	// CPYMWTN
    UINT64_C(490771456),	// CPYMWTRN
    UINT64_C(490755072),	// CPYMWTWN
    UINT64_C(486540288),	// CPYP
    UINT64_C(486589440),	// CPYPN
    UINT64_C(486573056),	// CPYPRN
    UINT64_C(486548480),	// CPYPRT
    UINT64_C(486597632),	// CPYPRTN
    UINT64_C(486581248),	// CPYPRTRN
    UINT64_C(486564864),	// CPYPRTWN
    UINT64_C(486552576),	// CPYPT
    UINT64_C(486601728),	// CPYPTN
    UINT64_C(486585344),	// CPYPTRN
    UINT64_C(486568960),	// CPYPTWN
    UINT64_C(486556672),	// CPYPWN
    UINT64_C(486544384),	// CPYPWT
    UINT64_C(486593536),	// CPYPWTN
    UINT64_C(486577152),	// CPYPWTRN
    UINT64_C(486560768),	// CPYPWTWN
    UINT64_C(84951040),	// CPY_ZPmI_B
    UINT64_C(97533952),	// CPY_ZPmI_D
    UINT64_C(89145344),	// CPY_ZPmI_H
    UINT64_C(93339648),	// CPY_ZPmI_S
    UINT64_C(86548480),	// CPY_ZPmR_B
    UINT64_C(99131392),	// CPY_ZPmR_D
    UINT64_C(90742784),	// CPY_ZPmR_H
    UINT64_C(94937088),	// CPY_ZPmR_S
    UINT64_C(86016000),	// CPY_ZPmV_B
    UINT64_C(98598912),	// CPY_ZPmV_D
    UINT64_C(90210304),	// CPY_ZPmV_H
    UINT64_C(94404608),	// CPY_ZPmV_S
    UINT64_C(84934656),	// CPY_ZPzI_B
    UINT64_C(97517568),	// CPY_ZPzI_D
    UINT64_C(89128960),	// CPY_ZPzI_H
    UINT64_C(93323264),	// CPY_ZPzI_S
    UINT64_C(448806912),	// CRC32Brr
    UINT64_C(448811008),	// CRC32CBrr
    UINT64_C(448812032),	// CRC32CHrr
    UINT64_C(448813056),	// CRC32CWrr
    UINT64_C(2596297728),	// CRC32CXrr
    UINT64_C(448807936),	// CRC32Hrr
    UINT64_C(448808960),	// CRC32Wrr
    UINT64_C(2596293632),	// CRC32Xrr
    UINT64_C(444596224),	// CSELWr
    UINT64_C(2592079872),	// CSELXr
    UINT64_C(444597248),	// CSINCWr
    UINT64_C(2592080896),	// CSINCXr
    UINT64_C(1518338048),	// CSINVWr
    UINT64_C(3665821696),	// CSINVXr
    UINT64_C(1518339072),	// CSNEGWr
    UINT64_C(3665822720),	// CSNEGXr
    UINT64_C(631250944),	// CTERMEQ_WW
    UINT64_C(635445248),	// CTERMEQ_XX
    UINT64_C(631250960),	// CTERMNE_WW
    UINT64_C(635445264),	// CTERMNE_XX
    UINT64_C(1522538496),	// CTZWr
    UINT64_C(3670022144),	// CTZXr
    UINT64_C(3567255553),	// DCPS1
    UINT64_C(3567255554),	// DCPS2
    UINT64_C(3567255555),	// DCPS3
    UINT64_C(70312960),	// DECB_XPiI
    UINT64_C(82895872),	// DECD_XPiI
    UINT64_C(82887680),	// DECD_ZPiI
    UINT64_C(74507264),	// DECH_XPiI
    UINT64_C(74499072),	// DECH_ZPiI
    UINT64_C(623740928),	// DECP_XP_B
    UINT64_C(636323840),	// DECP_XP_D
    UINT64_C(627935232),	// DECP_XP_H
    UINT64_C(632129536),	// DECP_XP_S
    UINT64_C(636321792),	// DECP_ZP_D
    UINT64_C(627933184),	// DECP_ZP_H
    UINT64_C(632127488),	// DECP_ZP_S
    UINT64_C(78701568),	// DECW_XPiI
    UINT64_C(78693376),	// DECW_ZPiI
    UINT64_C(3573756095),	// DMB
    UINT64_C(3602842592),	// DRPS
    UINT64_C(3573756063),	// DSB
    UINT64_C(3573756479),	// DSBnXS
    UINT64_C(96468992),	// DUPM_ZI
    UINT64_C(86057984),	// DUPQ_ZZI_B
    UINT64_C(86516736),	// DUPQ_ZZI_D
    UINT64_C(86123520),	// DUPQ_ZZI_H
    UINT64_C(86254592),	// DUPQ_ZZI_S
    UINT64_C(624476160),	// DUP_ZI_B
    UINT64_C(637059072),	// DUP_ZI_D
    UINT64_C(628670464),	// DUP_ZI_H
    UINT64_C(632864768),	// DUP_ZI_S
    UINT64_C(85997568),	// DUP_ZR_B
    UINT64_C(98580480),	// DUP_ZR_D
    UINT64_C(90191872),	// DUP_ZR_H
    UINT64_C(94386176),	// DUP_ZR_S
    UINT64_C(86056960),	// DUP_ZZI_B
    UINT64_C(86515712),	// DUP_ZZI_D
    UINT64_C(86122496),	// DUP_ZZI_H
    UINT64_C(87040000),	// DUP_ZZI_Q
    UINT64_C(86253568),	// DUP_ZZI_S
    UINT64_C(1577190400),	// DUPi16
    UINT64_C(1577321472),	// DUPi32
    UINT64_C(1577583616),	// DUPi64
    UINT64_C(1577124864),	// DUPi8
    UINT64_C(1308691456),	// DUPv16i8gpr
    UINT64_C(1308689408),	// DUPv16i8lane
    UINT64_C(235146240),	// DUPv2i32gpr
    UINT64_C(235144192),	// DUPv2i32lane
    UINT64_C(1309150208),	// DUPv2i64gpr
    UINT64_C(1309148160),	// DUPv2i64lane
    UINT64_C(235015168),	// DUPv4i16gpr
    UINT64_C(235013120),	// DUPv4i16lane
    UINT64_C(1308888064),	// DUPv4i32gpr
    UINT64_C(1308886016),	// DUPv4i32lane
    UINT64_C(1308756992),	// DUPv8i16gpr
    UINT64_C(1308754944),	// DUPv8i16lane
    UINT64_C(234949632),	// DUPv8i8gpr
    UINT64_C(234947584),	// DUPv8i8lane
    UINT64_C(1243611136),	// EONWrs
    UINT64_C(3391094784),	// EONXrs
    UINT64_C(3456106496),	// EOR3
    UINT64_C(69220352),	// EOR3_ZZZZ
    UINT64_C(1157664768),	// EORBT_ZZZ_B
    UINT64_C(1170247680),	// EORBT_ZZZ_D
    UINT64_C(1161859072),	// EORBT_ZZZ_H
    UINT64_C(1166053376),	// EORBT_ZZZ_S
    UINT64_C(69017600),	// EORQV_VPZ_B
    UINT64_C(81600512),	// EORQV_VPZ_D
    UINT64_C(73211904),	// EORQV_VPZ_H
    UINT64_C(77406208),	// EORQV_VPZ_S
    UINT64_C(624968192),	// EORS_PPzPP
    UINT64_C(1157665792),	// EORTB_ZZZ_B
    UINT64_C(1170248704),	// EORTB_ZZZ_D
    UINT64_C(1161860096),	// EORTB_ZZZ_H
    UINT64_C(1166054400),	// EORTB_ZZZ_S
    UINT64_C(68755456),	// EORV_VPZ_B
    UINT64_C(81338368),	// EORV_VPZ_D
    UINT64_C(72949760),	// EORV_VPZ_H
    UINT64_C(77144064),	// EORV_VPZ_S
    UINT64_C(1375731712),	// EORWri
    UINT64_C(1241513984),	// EORWrs
    UINT64_C(3523215360),	// EORXri
    UINT64_C(3388997632),	// EORXrs
    UINT64_C(620773888),	// EOR_PPzPP
    UINT64_C(88080384),	// EOR_ZI
    UINT64_C(68747264),	// EOR_ZPmZ_B
    UINT64_C(81330176),	// EOR_ZPmZ_D
    UINT64_C(72941568),	// EOR_ZPmZ_H
    UINT64_C(77135872),	// EOR_ZPmZ_S
    UINT64_C(77606912),	// EOR_ZZZ
    UINT64_C(1847598080),	// EORv16i8
    UINT64_C(773856256),	// EORv8i8
    UINT64_C(3600745440),	// ERET
    UINT64_C(3600747519),	// ERETAA
    UINT64_C(3600748543),	// ERETAB
    UINT64_C(87130112),	// EXPAND_ZPZ_B
    UINT64_C(99713024),	// EXPAND_ZPZ_D
    UINT64_C(91324416),	// EXPAND_ZPZ_H
    UINT64_C(95518720),	// EXPAND_ZPZ_S
    UINT64_C(90186752),	// EXTQ_ZZI
    UINT64_C(3221356544),	// EXTRACT_ZPMXI_H_B
    UINT64_C(3233939456),	// EXTRACT_ZPMXI_H_D
    UINT64_C(3225550848),	// EXTRACT_ZPMXI_H_H
    UINT64_C(3234004992),	// EXTRACT_ZPMXI_H_Q
    UINT64_C(3229745152),	// EXTRACT_ZPMXI_H_S
    UINT64_C(3221389312),	// EXTRACT_ZPMXI_V_B
    UINT64_C(3233972224),	// EXTRACT_ZPMXI_V_D
    UINT64_C(3225583616),	// EXTRACT_ZPMXI_V_H
    UINT64_C(3234037760),	// EXTRACT_ZPMXI_V_Q
    UINT64_C(3229777920),	// EXTRACT_ZPMXI_V_S
    UINT64_C(327155712),	// EXTRWrri
    UINT64_C(2478833664),	// EXTRXrri
    UINT64_C(85983232),	// EXT_ZZI
    UINT64_C(90177536),	// EXT_ZZI_B
    UINT64_C(1845493760),	// EXTv16i8
    UINT64_C(771751936),	// EXTv8i8
    UINT64_C(773945344),	// F1CVTL
    UINT64_C(1847687168),	// F1CVTL2
    UINT64_C(1695100928),	// F1CVTLT_ZZ_BtoH
    UINT64_C(3240550401),	// F1CVTL_2ZZ_BtoH
    UINT64_C(3240550400),	// F1CVT_2ZZ_BtoH
    UINT64_C(1695035392),	// F1CVT_ZZ_BtoH
    UINT64_C(778139648),	// F2CVTL
    UINT64_C(1851881472),	// F2CVTL2
    UINT64_C(1695101952),	// F2CVTLT_ZZ_BtoH
    UINT64_C(3248939009),	// F2CVTL_2ZZ_BtoH
    UINT64_C(3248939008),	// F2CVT_2ZZ_BtoH
    UINT64_C(1695036416),	// F2CVT_ZZ_BtoH
    UINT64_C(2126517248),	// FABD16
    UINT64_C(2124469248),	// FABD32
    UINT64_C(2128663552),	// FABD64
    UINT64_C(1707638784),	// FABD_ZPmZ_D
    UINT64_C(1699250176),	// FABD_ZPmZ_H
    UINT64_C(1703444480),	// FABD_ZPmZ_S
    UINT64_C(782291968),	// FABDv2f32
    UINT64_C(1860228096),	// FABDv2f64
    UINT64_C(784339968),	// FABDv4f16
    UINT64_C(1856033792),	// FABDv4f32
    UINT64_C(1858081792),	// FABDv8f16
    UINT64_C(509657088),	// FABSDr
    UINT64_C(518045696),	// FABSHr
    UINT64_C(505462784),	// FABSSr
    UINT64_C(81567744),	// FABS_ZPmZ_D
    UINT64_C(73179136),	// FABS_ZPmZ_H
    UINT64_C(77373440),	// FABS_ZPmZ_S
    UINT64_C(80519168),	// FABS_ZPzZ_D
    UINT64_C(72130560),	// FABS_ZPzZ_H
    UINT64_C(76324864),	// FABS_ZPzZ_S
    UINT64_C(245430272),	// FABSv2f32
    UINT64_C(1323366400),	// FABSv2f64
    UINT64_C(251197440),	// FABSv4f16
    UINT64_C(1319172096),	// FABSv4f32
    UINT64_C(1324939264),	// FABSv8f16
    UINT64_C(2118134784),	// FACGE16
    UINT64_C(2116086784),	// FACGE32
    UINT64_C(2120281088),	// FACGE64
    UINT64_C(1707130896),	// FACGE_PPzZZ_D
    UINT64_C(1698742288),	// FACGE_PPzZZ_H
    UINT64_C(1702936592),	// FACGE_PPzZZ_S
    UINT64_C(773909504),	// FACGEv2f32
    UINT64_C(1851845632),	// FACGEv2f64
    UINT64_C(775957504),	// FACGEv4f16
    UINT64_C(1847651328),	// FACGEv4f32
    UINT64_C(1849699328),	// FACGEv8f16
    UINT64_C(2126523392),	// FACGT16
    UINT64_C(2124475392),	// FACGT32
    UINT64_C(2128669696),	// FACGT64
    UINT64_C(1707139088),	// FACGT_PPzZZ_D
    UINT64_C(1698750480),	// FACGT_PPzZZ_H
    UINT64_C(1702944784),	// FACGT_PPzZZ_S
    UINT64_C(782298112),	// FACGTv2f32
    UINT64_C(1860234240),	// FACGTv2f64
    UINT64_C(784346112),	// FACGTv4f16
    UINT64_C(1856039936),	// FACGTv4f32
    UINT64_C(1858087936),	// FACGTv8f16
    UINT64_C(1708662784),	// FADDA_VPZ_D
    UINT64_C(1700274176),	// FADDA_VPZ_H
    UINT64_C(1704468480),	// FADDA_VPZ_S
    UINT64_C(509618176),	// FADDDrr
    UINT64_C(518006784),	// FADDHrr
    UINT64_C(1691385856),	// FADDP_ZPmZZ_D
    UINT64_C(1682997248),	// FADDP_ZPmZZ_H
    UINT64_C(1687191552),	// FADDP_ZPmZZ_S
    UINT64_C(773903360),	// FADDPv2f32
    UINT64_C(1851839488),	// FADDPv2f64
    UINT64_C(1580259328),	// FADDPv2i16p
    UINT64_C(2117130240),	// FADDPv2i32p
    UINT64_C(2121324544),	// FADDPv2i64p
    UINT64_C(775951360),	// FADDPv4f16
    UINT64_C(1847645184),	// FADDPv4f32
    UINT64_C(1849693184),	// FADDPv8f16
    UINT64_C(1691394048),	// FADDQV_D
    UINT64_C(1683005440),	// FADDQV_H
    UINT64_C(1687199744),	// FADDQV_S
    UINT64_C(505423872),	// FADDSrr
    UINT64_C(1707089920),	// FADDV_VPZ_D
    UINT64_C(1698701312),	// FADDV_VPZ_H
    UINT64_C(1702895616),	// FADDV_VPZ_S
    UINT64_C(3252689920),	// FADD_VG2_M2Z_D
    UINT64_C(3248757760),	// FADD_VG2_M2Z_H
    UINT64_C(3248495616),	// FADD_VG2_M2Z_S
    UINT64_C(3252755456),	// FADD_VG4_M4Z_D
    UINT64_C(3248823296),	// FADD_VG4_M4Z_H
    UINT64_C(3248561152),	// FADD_VG4_M4Z_S
    UINT64_C(1708687360),	// FADD_ZPmI_D
    UINT64_C(1700298752),	// FADD_ZPmI_H
    UINT64_C(1704493056),	// FADD_ZPmI_S
    UINT64_C(1707114496),	// FADD_ZPmZ_D
    UINT64_C(1698725888),	// FADD_ZPmZ_H
    UINT64_C(1702920192),	// FADD_ZPmZ_S
    UINT64_C(1707081728),	// FADD_ZZZ_D
    UINT64_C(1698693120),	// FADD_ZZZ_H
    UINT64_C(1702887424),	// FADD_ZZZ_S
    UINT64_C(237032448),	// FADDv2f32
    UINT64_C(1314968576),	// FADDv2f64
    UINT64_C(239080448),	// FADDv4f16
    UINT64_C(1310774272),	// FADDv4f32
    UINT64_C(1312822272),	// FADDv8f16
    UINT64_C(3252728128),	// FAMAX_2Z2Z_D
    UINT64_C(3244339520),	// FAMAX_2Z2Z_H
    UINT64_C(3248533824),	// FAMAX_2Z2Z_S
    UINT64_C(3252730176),	// FAMAX_4Z4Z_D
    UINT64_C(3244341568),	// FAMAX_4Z4Z_H
    UINT64_C(3248535872),	// FAMAX_4Z4Z_S
    UINT64_C(1708032000),	// FAMAX_ZPmZ_D
    UINT64_C(1699643392),	// FAMAX_ZPmZ_H
    UINT64_C(1703837696),	// FAMAX_ZPmZ_S
    UINT64_C(245423104),	// FAMAXv2f32
    UINT64_C(1323359232),	// FAMAXv2f64
    UINT64_C(247471104),	// FAMAXv4f16
    UINT64_C(1319164928),	// FAMAXv4f32
    UINT64_C(1321212928),	// FAMAXv8f16
    UINT64_C(3252728129),	// FAMIN_2Z2Z_D
    UINT64_C(3244339521),	// FAMIN_2Z2Z_H
    UINT64_C(3248533825),	// FAMIN_2Z2Z_S
    UINT64_C(3252730177),	// FAMIN_4Z4Z_D
    UINT64_C(3244341569),	// FAMIN_4Z4Z_H
    UINT64_C(3248535873),	// FAMIN_4Z4Z_S
    UINT64_C(1708097536),	// FAMIN_ZPmZ_D
    UINT64_C(1699708928),	// FAMIN_ZPmZ_H
    UINT64_C(1703903232),	// FAMIN_ZPmZ_S
    UINT64_C(782294016),	// FAMINv2f32
    UINT64_C(1860230144),	// FAMINv2f64
    UINT64_C(784342016),	// FAMINv4f16
    UINT64_C(1856035840),	// FAMINv4f32
    UINT64_C(1858083840),	// FAMINv8f16
    UINT64_C(1690337280),	// FCADD_ZPmZ_D
    UINT64_C(1681948672),	// FCADD_ZPmZ_H
    UINT64_C(1686142976),	// FCADD_ZPmZ_S
    UINT64_C(780198912),	// FCADDv2f32
    UINT64_C(1858135040),	// FCADDv2f64
    UINT64_C(776004608),	// FCADDv4f16
    UINT64_C(1853940736),	// FCADDv4f32
    UINT64_C(1849746432),	// FCADDv8f16
    UINT64_C(509608960),	// FCCMPDrr
    UINT64_C(509608976),	// FCCMPEDrr
    UINT64_C(517997584),	// FCCMPEHrr
    UINT64_C(505414672),	// FCCMPESrr
    UINT64_C(517997568),	// FCCMPHrr
    UINT64_C(505414656),	// FCCMPSrr
    UINT64_C(3252731904),	// FCLAMP_VG2_2Z2Z_D
    UINT64_C(3244343296),	// FCLAMP_VG2_2Z2Z_H
    UINT64_C(3248537600),	// FCLAMP_VG2_2Z2Z_S
    UINT64_C(3252733952),	// FCLAMP_VG4_4Z4Z_D
    UINT64_C(3244345344),	// FCLAMP_VG4_4Z4Z_H
    UINT64_C(3248539648),	// FCLAMP_VG4_4Z4Z_S
    UINT64_C(1692410880),	// FCLAMP_ZZZ_D
    UINT64_C(1684022272),	// FCLAMP_ZZZ_H
    UINT64_C(1688216576),	// FCLAMP_ZZZ_S
    UINT64_C(1581261824),	// FCMEQ16
    UINT64_C(1579213824),	// FCMEQ32
    UINT64_C(1583408128),	// FCMEQ64
    UINT64_C(1708269568),	// FCMEQ_PPzZ0_D
    UINT64_C(1699880960),	// FCMEQ_PPzZ0_H
    UINT64_C(1704075264),	// FCMEQ_PPzZ0_S
    UINT64_C(1707106304),	// FCMEQ_PPzZZ_D
    UINT64_C(1698717696),	// FCMEQ_PPzZZ_H
    UINT64_C(1702912000),	// FCMEQ_PPzZZ_S
    UINT64_C(1593366528),	// FCMEQv1i16rz
    UINT64_C(1587599360),	// FCMEQv1i32rz
    UINT64_C(1591793664),	// FCMEQv1i64rz
    UINT64_C(237036544),	// FCMEQv2f32
    UINT64_C(1314972672),	// FCMEQv2f64
    UINT64_C(245422080),	// FCMEQv2i32rz
    UINT64_C(1323358208),	// FCMEQv2i64rz
    UINT64_C(239084544),	// FCMEQv4f16
    UINT64_C(1310778368),	// FCMEQv4f32
    UINT64_C(251189248),	// FCMEQv4i16rz
    UINT64_C(1319163904),	// FCMEQv4i32rz
    UINT64_C(1312826368),	// FCMEQv8f16
    UINT64_C(1324931072),	// FCMEQv8i16rz
    UINT64_C(2118132736),	// FCMGE16
    UINT64_C(2116084736),	// FCMGE32
    UINT64_C(2120279040),	// FCMGE64
    UINT64_C(1708138496),	// FCMGE_PPzZ0_D
    UINT64_C(1699749888),	// FCMGE_PPzZ0_H
    UINT64_C(1703944192),	// FCMGE_PPzZ0_S
    UINT64_C(1707098112),	// FCMGE_PPzZZ_D
    UINT64_C(1698709504),	// FCMGE_PPzZZ_H
    UINT64_C(1702903808),	// FCMGE_PPzZZ_S
    UINT64_C(2130233344),	// FCMGEv1i16rz
    UINT64_C(2124466176),	// FCMGEv1i32rz
    UINT64_C(2128660480),	// FCMGEv1i64rz
    UINT64_C(773907456),	// FCMGEv2f32
    UINT64_C(1851843584),	// FCMGEv2f64
    UINT64_C(782288896),	// FCMGEv2i32rz
    UINT64_C(1860225024),	// FCMGEv2i64rz
    UINT64_C(775955456),	// FCMGEv4f16
    UINT64_C(1847649280),	// FCMGEv4f32
    UINT64_C(788056064),	// FCMGEv4i16rz
    UINT64_C(1856030720),	// FCMGEv4i32rz
    UINT64_C(1849697280),	// FCMGEv8f16
    UINT64_C(1861797888),	// FCMGEv8i16rz
    UINT64_C(2126521344),	// FCMGT16
    UINT64_C(2124473344),	// FCMGT32
    UINT64_C(2128667648),	// FCMGT64
    UINT64_C(1708138512),	// FCMGT_PPzZ0_D
    UINT64_C(1699749904),	// FCMGT_PPzZ0_H
    UINT64_C(1703944208),	// FCMGT_PPzZ0_S
    UINT64_C(1707098128),	// FCMGT_PPzZZ_D
    UINT64_C(1698709520),	// FCMGT_PPzZZ_H
    UINT64_C(1702903824),	// FCMGT_PPzZZ_S
    UINT64_C(1593362432),	// FCMGTv1i16rz
    UINT64_C(1587595264),	// FCMGTv1i32rz
    UINT64_C(1591789568),	// FCMGTv1i64rz
    UINT64_C(782296064),	// FCMGTv2f32
    UINT64_C(1860232192),	// FCMGTv2f64
    UINT64_C(245417984),	// FCMGTv2i32rz
    UINT64_C(1323354112),	// FCMGTv2i64rz
    UINT64_C(784344064),	// FCMGTv4f16
    UINT64_C(1856037888),	// FCMGTv4f32
    UINT64_C(251185152),	// FCMGTv4i16rz
    UINT64_C(1319159808),	// FCMGTv4i32rz
    UINT64_C(1858085888),	// FCMGTv8f16
    UINT64_C(1324926976),	// FCMGTv8i16rz
    UINT64_C(1690304512),	// FCMLA_ZPmZZ_D
    UINT64_C(1681915904),	// FCMLA_ZPmZZ_H
    UINT64_C(1686110208),	// FCMLA_ZPmZZ_S
    UINT64_C(1688211456),	// FCMLA_ZZZI_H
    UINT64_C(1692405760),	// FCMLA_ZZZI_S
    UINT64_C(780190720),	// FCMLAv2f32
    UINT64_C(1858126848),	// FCMLAv2f64
    UINT64_C(775996416),	// FCMLAv4f16
    UINT64_C(792727552),	// FCMLAv4f16_indexed
    UINT64_C(1853932544),	// FCMLAv4f32
    UINT64_C(1870663680),	// FCMLAv4f32_indexed
    UINT64_C(1849738240),	// FCMLAv8f16
    UINT64_C(1866469376),	// FCMLAv8f16_indexed
    UINT64_C(1708204048),	// FCMLE_PPzZ0_D
    UINT64_C(1699815440),	// FCMLE_PPzZ0_H
    UINT64_C(1704009744),	// FCMLE_PPzZ0_S
    UINT64_C(2130237440),	// FCMLEv1i16rz
    UINT64_C(2124470272),	// FCMLEv1i32rz
    UINT64_C(2128664576),	// FCMLEv1i64rz
    UINT64_C(782292992),	// FCMLEv2i32rz
    UINT64_C(1860229120),	// FCMLEv2i64rz
    UINT64_C(788060160),	// FCMLEv4i16rz
    UINT64_C(1856034816),	// FCMLEv4i32rz
    UINT64_C(1861801984),	// FCMLEv8i16rz
    UINT64_C(1708204032),	// FCMLT_PPzZ0_D
    UINT64_C(1699815424),	// FCMLT_PPzZ0_H
    UINT64_C(1704009728),	// FCMLT_PPzZ0_S
    UINT64_C(1593370624),	// FCMLTv1i16rz
    UINT64_C(1587603456),	// FCMLTv1i32rz
    UINT64_C(1591797760),	// FCMLTv1i64rz
    UINT64_C(245426176),	// FCMLTv2i32rz
    UINT64_C(1323362304),	// FCMLTv2i64rz
    UINT64_C(251193344),	// FCMLTv4i16rz
    UINT64_C(1319168000),	// FCMLTv4i32rz
    UINT64_C(1324935168),	// FCMLTv8i16rz
    UINT64_C(1708335104),	// FCMNE_PPzZ0_D
    UINT64_C(1699946496),	// FCMNE_PPzZ0_H
    UINT64_C(1704140800),	// FCMNE_PPzZ0_S
    UINT64_C(1707106320),	// FCMNE_PPzZZ_D
    UINT64_C(1698717712),	// FCMNE_PPzZZ_H
    UINT64_C(1702912016),	// FCMNE_PPzZZ_S
    UINT64_C(509616136),	// FCMPDri
    UINT64_C(509616128),	// FCMPDrr
    UINT64_C(509616152),	// FCMPEDri
    UINT64_C(509616144),	// FCMPEDrr
    UINT64_C(518004760),	// FCMPEHri
    UINT64_C(518004752),	// FCMPEHrr
    UINT64_C(505421848),	// FCMPESri
    UINT64_C(505421840),	// FCMPESrr
    UINT64_C(518004744),	// FCMPHri
    UINT64_C(518004736),	// FCMPHrr
    UINT64_C(505421832),	// FCMPSri
    UINT64_C(505421824),	// FCMPSrr
    UINT64_C(1707130880),	// FCMUO_PPzZZ_D
    UINT64_C(1698742272),	// FCMUO_PPzZZ_H
    UINT64_C(1702936576),	// FCMUO_PPzZZ_S
    UINT64_C(97566720),	// FCPY_ZPmI_D
    UINT64_C(89178112),	// FCPY_ZPmI_H
    UINT64_C(93372416),	// FCPY_ZPmI_S
    UINT64_C(509611008),	// FCSELDrrr
    UINT64_C(517999616),	// FCSELHrrr
    UINT64_C(505416704),	// FCSELSrrr
    UINT64_C(2667184128),	// FCVTASDHr
    UINT64_C(2654601216),	// FCVTASDSr
    UINT64_C(511311872),	// FCVTASSDr
    UINT64_C(519700480),	// FCVTASSHr
    UINT64_C(509870080),	// FCVTASUWDr
    UINT64_C(518258688),	// FCVTASUWHr
    UINT64_C(505675776),	// FCVTASUWSr
    UINT64_C(2657353728),	// FCVTASUXDr
    UINT64_C(2665742336),	// FCVTASUXHr
    UINT64_C(2653159424),	// FCVTASUXSr
    UINT64_C(1585039360),	// FCVTASv1f16
    UINT64_C(1579272192),	// FCVTASv1i32
    UINT64_C(1583466496),	// FCVTASv1i64
    UINT64_C(237094912),	// FCVTASv2f32
    UINT64_C(1315031040),	// FCVTASv2f64
    UINT64_C(242862080),	// FCVTASv4f16
    UINT64_C(1310836736),	// FCVTASv4f32
    UINT64_C(1316603904),	// FCVTASv8f16
    UINT64_C(2667249664),	// FCVTAUDHr
    UINT64_C(2654666752),	// FCVTAUDSr
    UINT64_C(511377408),	// FCVTAUSDr
    UINT64_C(519766016),	// FCVTAUSHr
    UINT64_C(509935616),	// FCVTAUUWDr
    UINT64_C(518324224),	// FCVTAUUWHr
    UINT64_C(505741312),	// FCVTAUUWSr
    UINT64_C(2657419264),	// FCVTAUUXDr
    UINT64_C(2665807872),	// FCVTAUUXHr
    UINT64_C(2653224960),	// FCVTAUUXSr
    UINT64_C(2121910272),	// FCVTAUv1f16
    UINT64_C(2116143104),	// FCVTAUv1i32
    UINT64_C(2120337408),	// FCVTAUv1i64
    UINT64_C(773965824),	// FCVTAUv2f32
    UINT64_C(1851901952),	// FCVTAUv2f64
    UINT64_C(779732992),	// FCVTAUv4f16
    UINT64_C(1847707648),	// FCVTAUv4f32
    UINT64_C(1853474816),	// FCVTAUv8f16
    UINT64_C(518176768),	// FCVTDHr
    UINT64_C(505593856),	// FCVTDSr
    UINT64_C(509853696),	// FCVTHDr
    UINT64_C(505659392),	// FCVTHSr
    UINT64_C(1686740992),	// FCVTLT_ZPmZ_HtoS
    UINT64_C(1691066368),	// FCVTLT_ZPmZ_StoD
    UINT64_C(1686216704),	// FCVTLT_ZPzZ_HtoS
    UINT64_C(1690542080),	// FCVTLT_ZPzZ_StoD
    UINT64_C(3248545793),	// FCVTL_2ZZ_H_S
    UINT64_C(241268736),	// FCVTLv2i32
    UINT64_C(237074432),	// FCVTLv4i16
    UINT64_C(1315010560),	// FCVTLv4i32
    UINT64_C(1310816256),	// FCVTLv8i16
    UINT64_C(2666790912),	// FCVTMSDHr
    UINT64_C(2654208000),	// FCVTMSDSr
    UINT64_C(510918656),	// FCVTMSSDr
    UINT64_C(519307264),	// FCVTMSSHr
    UINT64_C(510656512),	// FCVTMSUWDr
    UINT64_C(519045120),	// FCVTMSUWHr
    UINT64_C(506462208),	// FCVTMSUWSr
    UINT64_C(2658140160),	// FCVTMSUXDr
    UINT64_C(2666528768),	// FCVTMSUXHr
    UINT64_C(2653945856),	// FCVTMSUXSr
    UINT64_C(1585035264),	// FCVTMSv1f16
    UINT64_C(1579268096),	// FCVTMSv1i32
    UINT64_C(1583462400),	// FCVTMSv1i64
    UINT64_C(237090816),	// FCVTMSv2f32
    UINT64_C(1315026944),	// FCVTMSv2f64
    UINT64_C(242857984),	// FCVTMSv4f16
    UINT64_C(1310832640),	// FCVTMSv4f32
    UINT64_C(1316599808),	// FCVTMSv8f16
    UINT64_C(2666856448),	// FCVTMUDHr
    UINT64_C(2654273536),	// FCVTMUDSr
    UINT64_C(510984192),	// FCVTMUSDr
    UINT64_C(519372800),	// FCVTMUSHr
    UINT64_C(510722048),	// FCVTMUUWDr
    UINT64_C(519110656),	// FCVTMUUWHr
    UINT64_C(506527744),	// FCVTMUUWSr
    UINT64_C(2658205696),	// FCVTMUUXDr
    UINT64_C(2666594304),	// FCVTMUUXHr
    UINT64_C(2654011392),	// FCVTMUUXSr
    UINT64_C(2121906176),	// FCVTMUv1f16
    UINT64_C(2116139008),	// FCVTMUv1i32
    UINT64_C(2120333312),	// FCVTMUv1i64
    UINT64_C(773961728),	// FCVTMUv2f32
    UINT64_C(1851897856),	// FCVTMUv2f64
    UINT64_C(779728896),	// FCVTMUv4f16
    UINT64_C(1847703552),	// FCVTMUv4f32
    UINT64_C(1853470720),	// FCVTMUv8f16
    UINT64_C(1695167488),	// FCVTNB_Z2Z_StoB
    UINT64_C(2666135552),	// FCVTNSDHr
    UINT64_C(2653552640),	// FCVTNSDSr
    UINT64_C(510263296),	// FCVTNSSDr
    UINT64_C(518651904),	// FCVTNSSHr
    UINT64_C(509607936),	// FCVTNSUWDr
    UINT64_C(517996544),	// FCVTNSUWHr
    UINT64_C(505413632),	// FCVTNSUWSr
    UINT64_C(2657091584),	// FCVTNSUXDr
    UINT64_C(2665480192),	// FCVTNSUXHr
    UINT64_C(2652897280),	// FCVTNSUXSr
    UINT64_C(1585031168),	// FCVTNSv1f16
    UINT64_C(1579264000),	// FCVTNSv1i32
    UINT64_C(1583458304),	// FCVTNSv1i64
    UINT64_C(237086720),	// FCVTNSv2f32
    UINT64_C(1315022848),	// FCVTNSv2f64
    UINT64_C(242853888),	// FCVTNSv4f16
    UINT64_C(1310828544),	// FCVTNSv4f32
    UINT64_C(1316595712),	// FCVTNSv8f16
    UINT64_C(1695169536),	// FCVTNT_Z2Z_StoB
    UINT64_C(1691000832),	// FCVTNT_ZPmZ_DtoS
    UINT64_C(1686675456),	// FCVTNT_ZPmZ_StoH
    UINT64_C(1690476544),	// FCVTNT_ZPzZ_DtoS
    UINT64_C(1686151168),	// FCVTNT_ZPzZ_StoH
    UINT64_C(2666201088),	// FCVTNUDHr
    UINT64_C(2653618176),	// FCVTNUDSr
    UINT64_C(510328832),	// FCVTNUSDr
    UINT64_C(518717440),	// FCVTNUSHr
    UINT64_C(509673472),	// FCVTNUUWDr
    UINT64_C(518062080),	// FCVTNUUWHr
    UINT64_C(505479168),	// FCVTNUUWSr
    UINT64_C(2657157120),	// FCVTNUUXDr
    UINT64_C(2665545728),	// FCVTNUUXHr
    UINT64_C(2652962816),	// FCVTNUUXSr
    UINT64_C(2121902080),	// FCVTNUv1f16
    UINT64_C(2116134912),	// FCVTNUv1i32
    UINT64_C(2120329216),	// FCVTNUv1i64
    UINT64_C(773957632),	// FCVTNUv2f32
    UINT64_C(1851893760),	// FCVTNUv2f64
    UINT64_C(779724800),	// FCVTNUv4f16
    UINT64_C(1847699456),	// FCVTNUv4f32
    UINT64_C(1853466624),	// FCVTNUv8f16
    UINT64_C(1312879616),	// FCVTN_F16v16f8
    UINT64_C(239137792),	// FCVTN_F16v8f8
    UINT64_C(1308685312),	// FCVTN_F322v16f8
    UINT64_C(234943488),	// FCVTN_F32v8f8
    UINT64_C(1695166464),	// FCVTN_Z2Z_HtoB
    UINT64_C(3240157216),	// FCVTN_Z2Z_StoH
    UINT64_C(3241467936),	// FCVTN_Z4Z_StoB
    UINT64_C(241264640),	// FCVTNv2i32
    UINT64_C(237070336),	// FCVTNv4i16
    UINT64_C(1315006464),	// FCVTNv4i32
    UINT64_C(1310812160),	// FCVTNv8i16
    UINT64_C(2666659840),	// FCVTPSDHr
    UINT64_C(2654076928),	// FCVTPSDSr
    UINT64_C(510787584),	// FCVTPSSDr
    UINT64_C(519176192),	// FCVTPSSHr
    UINT64_C(510132224),	// FCVTPSUWDr
    UINT64_C(518520832),	// FCVTPSUWHr
    UINT64_C(505937920),	// FCVTPSUWSr
    UINT64_C(2657615872),	// FCVTPSUXDr
    UINT64_C(2666004480),	// FCVTPSUXHr
    UINT64_C(2653421568),	// FCVTPSUXSr
    UINT64_C(1593419776),	// FCVTPSv1f16
    UINT64_C(1587652608),	// FCVTPSv1i32
    UINT64_C(1591846912),	// FCVTPSv1i64
    UINT64_C(245475328),	// FCVTPSv2f32
    UINT64_C(1323411456),	// FCVTPSv2f64
    UINT64_C(251242496),	// FCVTPSv4f16
    UINT64_C(1319217152),	// FCVTPSv4f32
    UINT64_C(1324984320),	// FCVTPSv8f16
    UINT64_C(2666725376),	// FCVTPUDHr
    UINT64_C(2654142464),	// FCVTPUDSr
    UINT64_C(510853120),	// FCVTPUSDr
    UINT64_C(519241728),	// FCVTPUSHr
    UINT64_C(510197760),	// FCVTPUUWDr
    UINT64_C(518586368),	// FCVTPUUWHr
    UINT64_C(506003456),	// FCVTPUUWSr
    UINT64_C(2657681408),	// FCVTPUUXDr
    UINT64_C(2666070016),	// FCVTPUUXHr
    UINT64_C(2653487104),	// FCVTPUUXSr
    UINT64_C(2130290688),	// FCVTPUv1f16
    UINT64_C(2124523520),	// FCVTPUv1i32
    UINT64_C(2128717824),	// FCVTPUv1i64
    UINT64_C(782346240),	// FCVTPUv2f32
    UINT64_C(1860282368),	// FCVTPUv2f64
    UINT64_C(788113408),	// FCVTPUv4f16
    UINT64_C(1856088064),	// FCVTPUv4f32
    UINT64_C(1861855232),	// FCVTPUv8f16
    UINT64_C(509755392),	// FCVTSDr
    UINT64_C(518144000),	// FCVTSHr
    UINT64_C(1678417920),	// FCVTXNT_ZPmZ_DtoS
    UINT64_C(1677893632),	// FCVTXNT_ZPzZ_StoD
    UINT64_C(2120312832),	// FCVTXNv1i64
    UINT64_C(778135552),	// FCVTXNv2f32
    UINT64_C(1851877376),	// FCVTXNv4f32
    UINT64_C(1695195136),	// FCVTX_ZPmZ_DtoS
    UINT64_C(1679474688),	// FCVTX_ZPzZ_DtoS
    UINT64_C(2666921984),	// FCVTZSDHr
    UINT64_C(2654339072),	// FCVTZSDSr
    UINT64_C(1707945984),	// FCVTZSN_Z2Z_DtoS
    UINT64_C(1699557376),	// FCVTZSN_Z2Z_HtoB
    UINT64_C(1703751680),	// FCVTZSN_Z2Z_StoH
    UINT64_C(511049728),	// FCVTZSSDr
    UINT64_C(519438336),	// FCVTZSSHr
    UINT64_C(509116416),	// FCVTZSSWDri
    UINT64_C(517505024),	// FCVTZSSWHri
    UINT64_C(504922112),	// FCVTZSSWSri
    UINT64_C(2656567296),	// FCVTZSSXDri
    UINT64_C(2664955904),	// FCVTZSSXHri
    UINT64_C(2652372992),	// FCVTZSSXSri
    UINT64_C(511180800),	// FCVTZSUWDr
    UINT64_C(519569408),	// FCVTZSUWHr
    UINT64_C(506986496),	// FCVTZSUWSr
    UINT64_C(2658664448),	// FCVTZSUXDr
    UINT64_C(2667053056),	// FCVTZSUXHr
    UINT64_C(2654470144),	// FCVTZSUXSr
    UINT64_C(3240222720),	// FCVTZS_2Z2Z_StoS
    UINT64_C(3241271296),	// FCVTZS_4Z4Z_StoS
    UINT64_C(1709088768),	// FCVTZS_ZPmZ_DtoD
    UINT64_C(1708695552),	// FCVTZS_ZPmZ_DtoS
    UINT64_C(1700700160),	// FCVTZS_ZPmZ_HtoD
    UINT64_C(1700438016),	// FCVTZS_ZPmZ_HtoH
    UINT64_C(1700569088),	// FCVTZS_ZPmZ_HtoS
    UINT64_C(1708957696),	// FCVTZS_ZPmZ_StoD
    UINT64_C(1704763392),	// FCVTZS_ZPmZ_StoS
    UINT64_C(1692385280),	// FCVTZS_ZPzZ_DtoD
    UINT64_C(1692303360),	// FCVTZS_ZPzZ_DtoS
    UINT64_C(1683996672),	// FCVTZS_ZPzZ_HtoD
    UINT64_C(1683931136),	// FCVTZS_ZPzZ_HtoH
    UINT64_C(1683980288),	// FCVTZS_ZPzZ_HtoS
    UINT64_C(1692368896),	// FCVTZS_ZPzZ_StoD
    UINT64_C(1688174592),	// FCVTZS_ZPzZ_StoS
    UINT64_C(1598094336),	// FCVTZSd
    UINT64_C(1594948608),	// FCVTZSh
    UINT64_C(1595997184),	// FCVTZSs
    UINT64_C(1593423872),	// FCVTZSv1f16
    UINT64_C(1587656704),	// FCVTZSv1i32
    UINT64_C(1591851008),	// FCVTZSv1i64
    UINT64_C(245479424),	// FCVTZSv2f32
    UINT64_C(1323415552),	// FCVTZSv2f64
    UINT64_C(253819904),	// FCVTZSv2i32_shift
    UINT64_C(1329658880),	// FCVTZSv2i64_shift
    UINT64_C(251246592),	// FCVTZSv4f16
    UINT64_C(1319221248),	// FCVTZSv4f32
    UINT64_C(252771328),	// FCVTZSv4i16_shift
    UINT64_C(1327561728),	// FCVTZSv4i32_shift
    UINT64_C(1324988416),	// FCVTZSv8f16
    UINT64_C(1326513152),	// FCVTZSv8i16_shift
    UINT64_C(2666987520),	// FCVTZUDHr
    UINT64_C(2654404608),	// FCVTZUDSr
    UINT64_C(1707947008),	// FCVTZUN_Z2Z_DtoS
    UINT64_C(1699558400),	// FCVTZUN_Z2Z_HtoB
    UINT64_C(1703752704),	// FCVTZUN_Z2Z_StoH
    UINT64_C(511115264),	// FCVTZUSDr
    UINT64_C(519503872),	// FCVTZUSHr
    UINT64_C(509181952),	// FCVTZUSWDri
    UINT64_C(517570560),	// FCVTZUSWHri
    UINT64_C(504987648),	// FCVTZUSWSri
    UINT64_C(2656632832),	// FCVTZUSXDri
    UINT64_C(2665021440),	// FCVTZUSXHri
    UINT64_C(2652438528),	// FCVTZUSXSri
    UINT64_C(511246336),	// FCVTZUUWDr
    UINT64_C(519634944),	// FCVTZUUWHr
    UINT64_C(507052032),	// FCVTZUUWSr
    UINT64_C(2658729984),	// FCVTZUUXDr
    UINT64_C(2667118592),	// FCVTZUUXHr
    UINT64_C(2654535680),	// FCVTZUUXSr
    UINT64_C(3240222752),	// FCVTZU_2Z2Z_StoS
    UINT64_C(3241271328),	// FCVTZU_4Z4Z_StoS
    UINT64_C(1709154304),	// FCVTZU_ZPmZ_DtoD
    UINT64_C(1708761088),	// FCVTZU_ZPmZ_DtoS
    UINT64_C(1700765696),	// FCVTZU_ZPmZ_HtoD
    UINT64_C(1700503552),	// FCVTZU_ZPmZ_HtoH
    UINT64_C(1700634624),	// FCVTZU_ZPmZ_HtoS
    UINT64_C(1709023232),	// FCVTZU_ZPmZ_StoD
    UINT64_C(1704828928),	// FCVTZU_ZPmZ_StoS
    UINT64_C(1692393472),	// FCVTZU_ZPzZ_DtoD
    UINT64_C(1692311552),	// FCVTZU_ZPzZ_DtoS
    UINT64_C(1684004864),	// FCVTZU_ZPzZ_HtoD
    UINT64_C(1683939328),	// FCVTZU_ZPzZ_HtoH
    UINT64_C(1683988480),	// FCVTZU_ZPzZ_HtoS
    UINT64_C(1692377088),	// FCVTZU_ZPzZ_StoD
    UINT64_C(1688182784),	// FCVTZU_ZPzZ_StoS
    UINT64_C(2134965248),	// FCVTZUd
    UINT64_C(2131819520),	// FCVTZUh
    UINT64_C(2132868096),	// FCVTZUs
    UINT64_C(2130294784),	// FCVTZUv1f16
    UINT64_C(2124527616),	// FCVTZUv1i32
    UINT64_C(2128721920),	// FCVTZUv1i64
    UINT64_C(782350336),	// FCVTZUv2f32
    UINT64_C(1860286464),	// FCVTZUv2f64
    UINT64_C(790690816),	// FCVTZUv2i32_shift
    UINT64_C(1866529792),	// FCVTZUv2i64_shift
    UINT64_C(788117504),	// FCVTZUv4f16
    UINT64_C(1856092160),	// FCVTZUv4f32
    UINT64_C(789642240),	// FCVTZUv4i16_shift
    UINT64_C(1864432640),	// FCVTZUv4i32_shift
    UINT64_C(1861859328),	// FCVTZUv8f16
    UINT64_C(1863384064),	// FCVTZUv8i16_shift
    UINT64_C(3248545792),	// FCVT_2ZZ_H_S
    UINT64_C(3240419328),	// FCVT_Z2Z_HtoB
    UINT64_C(3240157184),	// FCVT_Z2Z_StoH
    UINT64_C(3241467904),	// FCVT_Z4Z_StoB
    UINT64_C(1707646976),	// FCVT_ZPmZ_DtoH
    UINT64_C(1707778048),	// FCVT_ZPmZ_DtoS
    UINT64_C(1707712512),	// FCVT_ZPmZ_HtoD
    UINT64_C(1703518208),	// FCVT_ZPmZ_HtoS
    UINT64_C(1707843584),	// FCVT_ZPmZ_StoD
    UINT64_C(1703452672),	// FCVT_ZPmZ_StoH
    UINT64_C(1692041216),	// FCVT_ZPzZ_DtoH
    UINT64_C(1692057600),	// FCVT_ZPzZ_DtoS
    UINT64_C(1692049408),	// FCVT_ZPzZ_HtoD
    UINT64_C(1687855104),	// FCVT_ZPzZ_HtoS
    UINT64_C(1692065792),	// FCVT_ZPzZ_StoD
    UINT64_C(1687846912),	// FCVT_ZPzZ_StoH
    UINT64_C(509614080),	// FDIVDrr
    UINT64_C(518002688),	// FDIVHrr
    UINT64_C(1707900928),	// FDIVR_ZPmZ_D
    UINT64_C(1699512320),	// FDIVR_ZPmZ_H
    UINT64_C(1703706624),	// FDIVR_ZPmZ_S
    UINT64_C(505419776),	// FDIVSrr
    UINT64_C(1707966464),	// FDIV_ZPmZ_D
    UINT64_C(1699577856),	// FDIV_ZPmZ_H
    UINT64_C(1703772160),	// FDIV_ZPmZ_S
    UINT64_C(773913600),	// FDIVv2f32
    UINT64_C(1851849728),	// FDIVv2f64
    UINT64_C(775961600),	// FDIVv4f16
    UINT64_C(1847655424),	// FDIVv4f32
    UINT64_C(1849703424),	// FDIVv8f16
    UINT64_C(3248492576),	// FDOT_VG2_M2Z2Z_BtoH
    UINT64_C(3248492592),	// FDOT_VG2_M2Z2Z_BtoS
    UINT64_C(3248492544),	// FDOT_VG2_M2Z2Z_HtoS
    UINT64_C(3251634208),	// FDOT_VG2_M2ZZI_BtoH
    UINT64_C(3243245624),	// FDOT_VG2_M2ZZI_BtoS
    UINT64_C(3243249672),	// FDOT_VG2_M2ZZI_HtoS
    UINT64_C(3240103944),	// FDOT_VG2_M2ZZ_BtoH
    UINT64_C(3240103960),	// FDOT_VG2_M2ZZ_BtoS
    UINT64_C(3240103936),	// FDOT_VG2_M2ZZ_HtoS
    UINT64_C(3248558112),	// FDOT_VG4_M4Z4Z_BtoH
    UINT64_C(3248558128),	// FDOT_VG4_M4Z4Z_BtoS
    UINT64_C(3248558080),	// FDOT_VG4_M4Z4Z_HtoS
    UINT64_C(3239088192),	// FDOT_VG4_M4ZZI_BtoH
    UINT64_C(3243278344),	// FDOT_VG4_M4ZZI_BtoS
    UINT64_C(3243282440),	// FDOT_VG4_M4ZZI_HtoS
    UINT64_C(3241152520),	// FDOT_VG4_M4ZZ_BtoH
    UINT64_C(3241152536),	// FDOT_VG4_M4ZZ_BtoS
    UINT64_C(3241152512),	// FDOT_VG4_M4ZZ_HtoS
    UINT64_C(1679836160),	// FDOT_ZZZI_BtoH
    UINT64_C(1684030464),	// FDOT_ZZZI_BtoS
    UINT64_C(1679835136),	// FDOT_ZZZI_S
    UINT64_C(1679852544),	// FDOT_ZZZ_BtoH
    UINT64_C(1684046848),	// FDOT_ZZZ_BtoS
    UINT64_C(1679851520),	// FDOT_ZZZ_S
    UINT64_C(251658240),	// FDOTlanev2f32
    UINT64_C(255852544),	// FDOTlanev4f16
    UINT64_C(255889408),	// FDOTlanev4f16_v2f32
    UINT64_C(1325400064),	// FDOTlanev4f32
    UINT64_C(1329594368),	// FDOTlanev8f16
    UINT64_C(1329631232),	// FDOTlanev8f16_v4f32
    UINT64_C(234945536),	// FDOTv2f32
    UINT64_C(239139840),	// FDOTv4f16
    UINT64_C(243334144),	// FDOTv4f16_v2f32
    UINT64_C(1308687360),	// FDOTv4f32
    UINT64_C(1312881664),	// FDOTv8f16
    UINT64_C(1317075968),	// FDOTv8f16_v4f32
    UINT64_C(637124608),	// FDUP_ZI_D
    UINT64_C(628736000),	// FDUP_ZI_H
    UINT64_C(632930304),	// FDUP_ZI_S
    UINT64_C(81836032),	// FEXPA_ZZ_D
    UINT64_C(73447424),	// FEXPA_ZZ_H
    UINT64_C(77641728),	// FEXPA_ZZ_S
    UINT64_C(622952448),	// FIRSTP_XPP_B
    UINT64_C(635535360),	// FIRSTP_XPP_D
    UINT64_C(627146752),	// FIRSTP_XPP_H
    UINT64_C(631341056),	// FIRSTP_XPP_S
    UINT64_C(511574016),	// FJCVTZS
    UINT64_C(1696505856),	// FLOGB_ZPmZ_D
    UINT64_C(1696243712),	// FLOGB_ZPmZ_H
    UINT64_C(1696374784),	// FLOGB_ZPmZ_S
    UINT64_C(1679745024),	// FLOGB_ZPzZ_D
    UINT64_C(1679728640),	// FLOGB_ZPzZ_H
    UINT64_C(1679736832),	// FLOGB_ZPzZ_S
    UINT64_C(524288000),	// FMADDDrrr
    UINT64_C(532676608),	// FMADDHrrr
    UINT64_C(520093696),	// FMADDSrrr
    UINT64_C(1709211648),	// FMAD_ZPmZZ_D
    UINT64_C(1700823040),	// FMAD_ZPmZZ_H
    UINT64_C(1705017344),	// FMAD_ZPmZZ_S
    UINT64_C(509626368),	// FMAXDrr
    UINT64_C(518014976),	// FMAXHrr
    UINT64_C(509634560),	// FMAXNMDrr
    UINT64_C(518023168),	// FMAXNMHrr
    UINT64_C(1691648000),	// FMAXNMP_ZPmZZ_D
    UINT64_C(1683259392),	// FMAXNMP_ZPmZZ_H
    UINT64_C(1687453696),	// FMAXNMP_ZPmZZ_S
    UINT64_C(773899264),	// FMAXNMPv2f32
    UINT64_C(1851835392),	// FMAXNMPv2f64
    UINT64_C(1580255232),	// FMAXNMPv2i16p
    UINT64_C(2117126144),	// FMAXNMPv2i32p
    UINT64_C(2121320448),	// FMAXNMPv2i64p
    UINT64_C(775947264),	// FMAXNMPv4f16
    UINT64_C(1847641088),	// FMAXNMPv4f32
    UINT64_C(1849689088),	// FMAXNMPv8f16
    UINT64_C(1691656192),	// FMAXNMQV_D
    UINT64_C(1683267584),	// FMAXNMQV_H
    UINT64_C(1687461888),	// FMAXNMQV_S
    UINT64_C(505440256),	// FMAXNMSrr
    UINT64_C(1707352064),	// FMAXNMV_VPZ_D
    UINT64_C(1698963456),	// FMAXNMV_VPZ_H
    UINT64_C(1703157760),	// FMAXNMV_VPZ_S
    UINT64_C(238077952),	// FMAXNMVv4i16v
    UINT64_C(1848690688),	// FMAXNMVv4i32v
    UINT64_C(1311819776),	// FMAXNMVv8i16v
    UINT64_C(3252728096),	// FMAXNM_VG2_2Z2Z_D
    UINT64_C(3244339488),	// FMAXNM_VG2_2Z2Z_H
    UINT64_C(3248533792),	// FMAXNM_VG2_2Z2Z_S
    UINT64_C(3252724000),	// FMAXNM_VG2_2ZZ_D
    UINT64_C(3244335392),	// FMAXNM_VG2_2ZZ_H
    UINT64_C(3248529696),	// FMAXNM_VG2_2ZZ_S
    UINT64_C(3252730144),	// FMAXNM_VG4_4Z4Z_D
    UINT64_C(3244341536),	// FMAXNM_VG4_4Z4Z_H
    UINT64_C(3248535840),	// FMAXNM_VG4_4Z4Z_S
    UINT64_C(3252726048),	// FMAXNM_VG4_4ZZ_D
    UINT64_C(3244337440),	// FMAXNM_VG4_4ZZ_H
    UINT64_C(3248531744),	// FMAXNM_VG4_4ZZ_S
    UINT64_C(1708949504),	// FMAXNM_ZPmI_D
    UINT64_C(1700560896),	// FMAXNM_ZPmI_H
    UINT64_C(1704755200),	// FMAXNM_ZPmI_S
    UINT64_C(1707376640),	// FMAXNM_ZPmZ_D
    UINT64_C(1698988032),	// FMAXNM_ZPmZ_H
    UINT64_C(1703182336),	// FMAXNM_ZPmZ_S
    UINT64_C(237028352),	// FMAXNMv2f32
    UINT64_C(1314964480),	// FMAXNMv2f64
    UINT64_C(239076352),	// FMAXNMv4f16
    UINT64_C(1310770176),	// FMAXNMv4f32
    UINT64_C(1312818176),	// FMAXNMv8f16
    UINT64_C(1691779072),	// FMAXP_ZPmZZ_D
    UINT64_C(1683390464),	// FMAXP_ZPmZZ_H
    UINT64_C(1687584768),	// FMAXP_ZPmZZ_S
    UINT64_C(773911552),	// FMAXPv2f32
    UINT64_C(1851847680),	// FMAXPv2f64
    UINT64_C(1580267520),	// FMAXPv2i16p
    UINT64_C(2117138432),	// FMAXPv2i32p
    UINT64_C(2121332736),	// FMAXPv2i64p
    UINT64_C(775959552),	// FMAXPv4f16
    UINT64_C(1847653376),	// FMAXPv4f32
    UINT64_C(1849701376),	// FMAXPv8f16
    UINT64_C(1691787264),	// FMAXQV_D
    UINT64_C(1683398656),	// FMAXQV_H
    UINT64_C(1687592960),	// FMAXQV_S
    UINT64_C(505432064),	// FMAXSrr
    UINT64_C(1707483136),	// FMAXV_VPZ_D
    UINT64_C(1699094528),	// FMAXV_VPZ_H
    UINT64_C(1703288832),	// FMAXV_VPZ_S
    UINT64_C(238090240),	// FMAXVv4i16v
    UINT64_C(1848702976),	// FMAXVv4i32v
    UINT64_C(1311832064),	// FMAXVv8i16v
    UINT64_C(3252728064),	// FMAX_VG2_2Z2Z_D
    UINT64_C(3244339456),	// FMAX_VG2_2Z2Z_H
    UINT64_C(3248533760),	// FMAX_VG2_2Z2Z_S
    UINT64_C(3252723968),	// FMAX_VG2_2ZZ_D
    UINT64_C(3244335360),	// FMAX_VG2_2ZZ_H
    UINT64_C(3248529664),	// FMAX_VG2_2ZZ_S
    UINT64_C(3252730112),	// FMAX_VG4_4Z4Z_D
    UINT64_C(3244341504),	// FMAX_VG4_4Z4Z_H
    UINT64_C(3248535808),	// FMAX_VG4_4Z4Z_S
    UINT64_C(3252726016),	// FMAX_VG4_4ZZ_D
    UINT64_C(3244337408),	// FMAX_VG4_4ZZ_H
    UINT64_C(3248531712),	// FMAX_VG4_4ZZ_S
    UINT64_C(1709080576),	// FMAX_ZPmI_D
    UINT64_C(1700691968),	// FMAX_ZPmI_H
    UINT64_C(1704886272),	// FMAX_ZPmI_S
    UINT64_C(1707507712),	// FMAX_ZPmZ_D
    UINT64_C(1699119104),	// FMAX_ZPmZ_H
    UINT64_C(1703313408),	// FMAX_ZPmZ_S
    UINT64_C(237040640),	// FMAXv2f32
    UINT64_C(1314976768),	// FMAXv2f64
    UINT64_C(239088640),	// FMAXv4f16
    UINT64_C(1310782464),	// FMAXv4f32
    UINT64_C(1312830464),	// FMAXv8f16
    UINT64_C(509630464),	// FMINDrr
    UINT64_C(518019072),	// FMINHrr
    UINT64_C(509638656),	// FMINNMDrr
    UINT64_C(518027264),	// FMINNMHrr
    UINT64_C(1691713536),	// FMINNMP_ZPmZZ_D
    UINT64_C(1683324928),	// FMINNMP_ZPmZZ_H
    UINT64_C(1687519232),	// FMINNMP_ZPmZZ_S
    UINT64_C(782287872),	// FMINNMPv2f32
    UINT64_C(1860224000),	// FMINNMPv2f64
    UINT64_C(1588643840),	// FMINNMPv2i16p
    UINT64_C(2125514752),	// FMINNMPv2i32p
    UINT64_C(2129709056),	// FMINNMPv2i64p
    UINT64_C(784335872),	// FMINNMPv4f16
    UINT64_C(1856029696),	// FMINNMPv4f32
    UINT64_C(1858077696),	// FMINNMPv8f16
    UINT64_C(1691721728),	// FMINNMQV_D
    UINT64_C(1683333120),	// FMINNMQV_H
    UINT64_C(1687527424),	// FMINNMQV_S
    UINT64_C(505444352),	// FMINNMSrr
    UINT64_C(1707417600),	// FMINNMV_VPZ_D
    UINT64_C(1699028992),	// FMINNMV_VPZ_H
    UINT64_C(1703223296),	// FMINNMV_VPZ_S
    UINT64_C(246466560),	// FMINNMVv4i16v
    UINT64_C(1857079296),	// FMINNMVv4i32v
    UINT64_C(1320208384),	// FMINNMVv8i16v
    UINT64_C(3252728097),	// FMINNM_VG2_2Z2Z_D
    UINT64_C(3244339489),	// FMINNM_VG2_2Z2Z_H
    UINT64_C(3248533793),	// FMINNM_VG2_2Z2Z_S
    UINT64_C(3252724001),	// FMINNM_VG2_2ZZ_D
    UINT64_C(3244335393),	// FMINNM_VG2_2ZZ_H
    UINT64_C(3248529697),	// FMINNM_VG2_2ZZ_S
    UINT64_C(3252730145),	// FMINNM_VG4_4Z4Z_D
    UINT64_C(3244341537),	// FMINNM_VG4_4Z4Z_H
    UINT64_C(3248535841),	// FMINNM_VG4_4Z4Z_S
    UINT64_C(3252726049),	// FMINNM_VG4_4ZZ_D
    UINT64_C(3244337441),	// FMINNM_VG4_4ZZ_H
    UINT64_C(3248531745),	// FMINNM_VG4_4ZZ_S
    UINT64_C(1709015040),	// FMINNM_ZPmI_D
    UINT64_C(1700626432),	// FMINNM_ZPmI_H
    UINT64_C(1704820736),	// FMINNM_ZPmI_S
    UINT64_C(1707442176),	// FMINNM_ZPmZ_D
    UINT64_C(1699053568),	// FMINNM_ZPmZ_H
    UINT64_C(1703247872),	// FMINNM_ZPmZ_S
    UINT64_C(245416960),	// FMINNMv2f32
    UINT64_C(1323353088),	// FMINNMv2f64
    UINT64_C(247464960),	// FMINNMv4f16
    UINT64_C(1319158784),	// FMINNMv4f32
    UINT64_C(1321206784),	// FMINNMv8f16
    UINT64_C(1691844608),	// FMINP_ZPmZZ_D
    UINT64_C(1683456000),	// FMINP_ZPmZZ_H
    UINT64_C(1687650304),	// FMINP_ZPmZZ_S
    UINT64_C(782300160),	// FMINPv2f32
    UINT64_C(1860236288),	// FMINPv2f64
    UINT64_C(1588656128),	// FMINPv2i16p
    UINT64_C(2125527040),	// FMINPv2i32p
    UINT64_C(2129721344),	// FMINPv2i64p
    UINT64_C(784348160),	// FMINPv4f16
    UINT64_C(1856041984),	// FMINPv4f32
    UINT64_C(1858089984),	// FMINPv8f16
    UINT64_C(1691852800),	// FMINQV_D
    UINT64_C(1683464192),	// FMINQV_H
    UINT64_C(1687658496),	// FMINQV_S
    UINT64_C(505436160),	// FMINSrr
    UINT64_C(1707548672),	// FMINV_VPZ_D
    UINT64_C(1699160064),	// FMINV_VPZ_H
    UINT64_C(1703354368),	// FMINV_VPZ_S
    UINT64_C(246478848),	// FMINVv4i16v
    UINT64_C(1857091584),	// FMINVv4i32v
    UINT64_C(1320220672),	// FMINVv8i16v
    UINT64_C(3252728065),	// FMIN_VG2_2Z2Z_D
    UINT64_C(3244339457),	// FMIN_VG2_2Z2Z_H
    UINT64_C(3248533761),	// FMIN_VG2_2Z2Z_S
    UINT64_C(3252723969),	// FMIN_VG2_2ZZ_D
    UINT64_C(3244335361),	// FMIN_VG2_2ZZ_H
    UINT64_C(3248529665),	// FMIN_VG2_2ZZ_S
    UINT64_C(3252730113),	// FMIN_VG4_4Z4Z_D
    UINT64_C(3244341505),	// FMIN_VG4_4Z4Z_H
    UINT64_C(3248535809),	// FMIN_VG4_4Z4Z_S
    UINT64_C(3252726017),	// FMIN_VG4_4ZZ_D
    UINT64_C(3244337409),	// FMIN_VG4_4ZZ_H
    UINT64_C(3248531713),	// FMIN_VG4_4ZZ_S
    UINT64_C(1709146112),	// FMIN_ZPmI_D
    UINT64_C(1700757504),	// FMIN_ZPmI_H
    UINT64_C(1704951808),	// FMIN_ZPmI_S
    UINT64_C(1707573248),	// FMIN_ZPmZ_D
    UINT64_C(1699184640),	// FMIN_ZPmZ_H
    UINT64_C(1703378944),	// FMIN_ZPmZ_S
    UINT64_C(245429248),	// FMINv2f32
    UINT64_C(1323365376),	// FMINv2f64
    UINT64_C(247477248),	// FMINv4f16
    UINT64_C(1319171072),	// FMINv4f32
    UINT64_C(1321219072),	// FMINv8f16
    UINT64_C(796950528),	// FMLAL2lanev4f16
    UINT64_C(1870692352),	// FMLAL2lanev8f16
    UINT64_C(773901312),	// FMLAL2v4f16
    UINT64_C(1847643136),	// FMLAL2v8f16
    UINT64_C(1688242176),	// FMLALB_ZZZ
    UINT64_C(1679839232),	// FMLALB_ZZZI
    UINT64_C(1688223744),	// FMLALB_ZZZI_SHH
    UINT64_C(1688240128),	// FMLALB_ZZZ_SHH
    UINT64_C(264241152),	// FMLALBlanev8f16
    UINT64_C(247528448),	// FMLALBv16i8_v8f16
    UINT64_C(1679853568),	// FMLALLBB_ZZZ
    UINT64_C(1679867904),	// FMLALLBB_ZZZI
    UINT64_C(788561920),	// FMLALLBBlanev4f32
    UINT64_C(234931200),	// FMLALLBBv4f32
    UINT64_C(1679857664),	// FMLALLBT_ZZZ
    UINT64_C(1684062208),	// FMLALLBT_ZZZI
    UINT64_C(792756224),	// FMLALLBTlanev4f32
    UINT64_C(239125504),	// FMLALLBTv4f32
    UINT64_C(1679861760),	// FMLALLTB_ZZZ
    UINT64_C(1688256512),	// FMLALLTB_ZZZI
    UINT64_C(1862303744),	// FMLALLTBlanev4f32
    UINT64_C(1308673024),	// FMLALLTBv4f32
    UINT64_C(1679865856),	// FMLALLTT_ZZZ
    UINT64_C(1692450816),	// FMLALLTT_ZZZI
    UINT64_C(1866498048),	// FMLALLTTlanev4f32
    UINT64_C(1312867328),	// FMLALLTTv4f32
    UINT64_C(3242196992),	// FMLALL_MZZI_BtoS
    UINT64_C(3241149440),	// FMLALL_MZZ_BtoS
    UINT64_C(3248488480),	// FMLALL_VG2_M2Z2Z_BtoS
    UINT64_C(3247439904),	// FMLALL_VG2_M2ZZI_BtoS
    UINT64_C(3240099842),	// FMLALL_VG2_M2ZZ_BtoS
    UINT64_C(3248554016),	// FMLALL_VG4_M4Z4Z_BtoS
    UINT64_C(3239084096),	// FMLALL_VG4_M4ZZI_BtoS
    UINT64_C(3241148418),	// FMLALL_VG4_M4ZZ_BtoS
    UINT64_C(1688246272),	// FMLALT_ZZZ
    UINT64_C(1688227840),	// FMLALT_ZZZI
    UINT64_C(1688224768),	// FMLALT_ZZZI_SHH
    UINT64_C(1688241152),	// FMLALT_ZZZ_SHH
    UINT64_C(1337982976),	// FMLALTlanev8f16
    UINT64_C(1321270272),	// FMLALTv16i8_v8f16
    UINT64_C(3250585600),	// FMLAL_MZZI_BtoH
    UINT64_C(3246395392),	// FMLAL_MZZI_HtoS
    UINT64_C(3240102912),	// FMLAL_MZZ_HtoS
    UINT64_C(3248490528),	// FMLAL_VG2_M2Z2Z_BtoH
    UINT64_C(3248490496),	// FMLAL_VG2_M2Z2Z_HtoS
    UINT64_C(3247444016),	// FMLAL_VG2_M2ZZI_BtoH
    UINT64_C(3247443968),	// FMLAL_VG2_M2ZZI_HtoS
    UINT64_C(3240101892),	// FMLAL_VG2_M2ZZ_BtoH
    UINT64_C(3240101888),	// FMLAL_VG2_M2ZZ_HtoS
    UINT64_C(3241151488),	// FMLAL_VG2_MZZ_BtoH
    UINT64_C(3248556064),	// FMLAL_VG4_M4Z4Z_BtoH
    UINT64_C(3248556032),	// FMLAL_VG4_M4Z4Z_HtoS
    UINT64_C(3247476768),	// FMLAL_VG4_M4ZZI_BtoH
    UINT64_C(3247476736),	// FMLAL_VG4_M4ZZI_HtoS
    UINT64_C(3241150468),	// FMLAL_VG4_M4ZZ_BtoH
    UINT64_C(3241150464),	// FMLAL_VG4_M4ZZ_HtoS
    UINT64_C(260046848),	// FMLALlanev4f16
    UINT64_C(1333788672),	// FMLALlanev8f16
    UINT64_C(237038592),	// FMLALv4f16
    UINT64_C(1310780416),	// FMLALv8f16
    UINT64_C(3252688896),	// FMLA_VG2_M2Z2Z_D
    UINT64_C(3248492552),	// FMLA_VG2_M2Z2Z_H
    UINT64_C(3248494592),	// FMLA_VG2_M2Z2Z_S
    UINT64_C(3251634176),	// FMLA_VG2_M2ZZI_D
    UINT64_C(3239055360),	// FMLA_VG2_M2ZZI_H
    UINT64_C(3243245568),	// FMLA_VG2_M2ZZI_S
    UINT64_C(3244300288),	// FMLA_VG2_M2ZZ_D
    UINT64_C(3240107008),	// FMLA_VG2_M2ZZ_H
    UINT64_C(3240105984),	// FMLA_VG2_M2ZZ_S
    UINT64_C(3252754432),	// FMLA_VG4_M4Z4Z_D
    UINT64_C(3248558088),	// FMLA_VG4_M4Z4Z_H
    UINT64_C(3248560128),	// FMLA_VG4_M4Z4Z_S
    UINT64_C(3251666944),	// FMLA_VG4_M4ZZI_D
    UINT64_C(3239088128),	// FMLA_VG4_M4ZZI_H
    UINT64_C(3243278336),	// FMLA_VG4_M4ZZI_S
    UINT64_C(3245348864),	// FMLA_VG4_M4ZZ_D
    UINT64_C(3241155584),	// FMLA_VG4_M4ZZ_H
    UINT64_C(3241154560),	// FMLA_VG4_M4ZZ_S
    UINT64_C(1709178880),	// FMLA_ZPmZZ_D
    UINT64_C(1700790272),	// FMLA_ZPmZZ_H
    UINT64_C(1704984576),	// FMLA_ZPmZZ_S
    UINT64_C(1692401664),	// FMLA_ZZZI_D
    UINT64_C(1679818752),	// FMLA_ZZZI_H
    UINT64_C(1688207360),	// FMLA_ZZZI_S
    UINT64_C(1593839616),	// FMLAv1i16_indexed
    UINT64_C(1602228224),	// FMLAv1i32_indexed
    UINT64_C(1606422528),	// FMLAv1i64_indexed
    UINT64_C(237030400),	// FMLAv2f32
    UINT64_C(1314966528),	// FMLAv2f64
    UINT64_C(260050944),	// FMLAv2i32_indexed
    UINT64_C(1337987072),	// FMLAv2i64_indexed
    UINT64_C(239078400),	// FMLAv4f16
    UINT64_C(1310772224),	// FMLAv4f32
    UINT64_C(251662336),	// FMLAv4i16_indexed
    UINT64_C(1333792768),	// FMLAv4i32_indexed
    UINT64_C(1312820224),	// FMLAv8f16
    UINT64_C(1325404160),	// FMLAv8i16_indexed
    UINT64_C(1679877120),	// FMLLA_ZZZ_HtoS
    UINT64_C(796966912),	// FMLSL2lanev4f16
    UINT64_C(1870708736),	// FMLSL2lanev8f16
    UINT64_C(782289920),	// FMLSL2v4f16
    UINT64_C(1856031744),	// FMLSL2v8f16
    UINT64_C(1688231936),	// FMLSLB_ZZZI_SHH
    UINT64_C(1688248320),	// FMLSLB_ZZZ_SHH
    UINT64_C(1688232960),	// FMLSLT_ZZZI_SHH
    UINT64_C(1688249344),	// FMLSLT_ZZZ_SHH
    UINT64_C(3246395400),	// FMLSL_MZZI_HtoS
    UINT64_C(3240102920),	// FMLSL_MZZ_HtoS
    UINT64_C(3248490504),	// FMLSL_VG2_M2Z2Z_HtoS
    UINT64_C(3247443976),	// FMLSL_VG2_M2ZZI_HtoS
    UINT64_C(3240101896),	// FMLSL_VG2_M2ZZ_HtoS
    UINT64_C(3248556040),	// FMLSL_VG4_M4Z4Z_HtoS
    UINT64_C(3247476744),	// FMLSL_VG4_M4ZZI_HtoS
    UINT64_C(3241150472),	// FMLSL_VG4_M4ZZ_HtoS
    UINT64_C(260063232),	// FMLSLlanev4f16
    UINT64_C(1333805056),	// FMLSLlanev8f16
    UINT64_C(245427200),	// FMLSLv4f16
    UINT64_C(1319169024),	// FMLSLv8f16
    UINT64_C(3252688904),	// FMLS_VG2_M2Z2Z_D
    UINT64_C(3248492568),	// FMLS_VG2_M2Z2Z_H
    UINT64_C(3248494600),	// FMLS_VG2_M2Z2Z_S
    UINT64_C(3251634192),	// FMLS_VG2_M2ZZI_D
    UINT64_C(3239055376),	// FMLS_VG2_M2ZZI_H
    UINT64_C(3243245584),	// FMLS_VG2_M2ZZI_S
    UINT64_C(3244300296),	// FMLS_VG2_M2ZZ_D
    UINT64_C(3240107016),	// FMLS_VG2_M2ZZ_H
    UINT64_C(3240105992),	// FMLS_VG2_M2ZZ_S
    UINT64_C(3252754440),	// FMLS_VG4_M4Z4Z_D
    UINT64_C(3248558104),	// FMLS_VG4_M4Z4Z_H
    UINT64_C(3248560136),	// FMLS_VG4_M4Z4Z_S
    UINT64_C(3251666960),	// FMLS_VG4_M4ZZI_D
    UINT64_C(3239088144),	// FMLS_VG4_M4ZZI_H
    UINT64_C(3243278352),	// FMLS_VG4_M4ZZI_S
    UINT64_C(3245348872),	// FMLS_VG4_M4ZZ_D
    UINT64_C(3241155592),	// FMLS_VG4_M4ZZ_H
    UINT64_C(3241154568),	// FMLS_VG4_M4ZZ_S
    UINT64_C(1709187072),	// FMLS_ZPmZZ_D
    UINT64_C(1700798464),	// FMLS_ZPmZZ_H
    UINT64_C(1704992768),	// FMLS_ZPmZZ_S
    UINT64_C(1692402688),	// FMLS_ZZZI_D
    UINT64_C(1679819776),	// FMLS_ZZZI_H
    UINT64_C(1688208384),	// FMLS_ZZZI_S
    UINT64_C(1593856000),	// FMLSv1i16_indexed
    UINT64_C(1602244608),	// FMLSv1i32_indexed
    UINT64_C(1606438912),	// FMLSv1i64_indexed
    UINT64_C(245419008),	// FMLSv2f32
    UINT64_C(1323355136),	// FMLSv2f64
    UINT64_C(260067328),	// FMLSv2i32_indexed
    UINT64_C(1338003456),	// FMLSv2i64_indexed
    UINT64_C(247467008),	// FMLSv4f16
    UINT64_C(1319160832),	// FMLSv4f32
    UINT64_C(251678720),	// FMLSv4i16_indexed
    UINT64_C(1333809152),	// FMLSv4i32_indexed
    UINT64_C(1321208832),	// FMLSv8f16
    UINT64_C(1325420544),	// FMLSv8i16_indexed
    UINT64_C(1684070400),	// FMMLA_ZZZ_BtoH
    UINT64_C(1679876096),	// FMMLA_ZZZ_BtoS
    UINT64_C(1692460032),	// FMMLA_ZZZ_D
    UINT64_C(1688264704),	// FMMLA_ZZZ_H
    UINT64_C(1688265728),	// FMMLA_ZZZ_S
    UINT64_C(1853942784),	// FMMLAv4f32
    UINT64_C(1845554176),	// FMMLAv8f16
    UINT64_C(1312877568),	// FMMLAv8f16_v4f32
    UINT64_C(1321266176),	// FMMLAv8f16_v8f16
    UINT64_C(2150629896),	// FMOP4A_M2Z2Z_BtoH
    UINT64_C(2150629888),	// FMOP4A_M2Z2Z_BtoS
    UINT64_C(2161115656),	// FMOP4A_M2Z2Z_D
    UINT64_C(2165309960),	// FMOP4A_M2Z2Z_H
    UINT64_C(2167407104),	// FMOP4A_M2Z2Z_HtoS
    UINT64_C(2148532736),	// FMOP4A_M2Z2Z_S
    UINT64_C(2149581320),	// FMOP4A_M2ZZ_BtoH
    UINT64_C(2149581312),	// FMOP4A_M2ZZ_BtoS
    UINT64_C(2160067080),	// FMOP4A_M2ZZ_D
    UINT64_C(2164261384),	// FMOP4A_M2ZZ_H
    UINT64_C(2166358528),	// FMOP4A_M2ZZ_HtoS
    UINT64_C(2147484160),	// FMOP4A_M2ZZ_S
    UINT64_C(2150629384),	// FMOP4A_MZ2Z_BtoH
    UINT64_C(2150629376),	// FMOP4A_MZ2Z_BtoS
    UINT64_C(2161115144),	// FMOP4A_MZ2Z_D
    UINT64_C(2165309448),	// FMOP4A_MZ2Z_H
    UINT64_C(2167406592),	// FMOP4A_MZ2Z_HtoS
    UINT64_C(2148532224),	// FMOP4A_MZ2Z_S
    UINT64_C(2149580808),	// FMOP4A_MZZ_BtoH
    UINT64_C(2149580800),	// FMOP4A_MZZ_BtoS
    UINT64_C(2160066568),	// FMOP4A_MZZ_D
    UINT64_C(2164260872),	// FMOP4A_MZZ_H
    UINT64_C(2166358016),	// FMOP4A_MZZ_HtoS
    UINT64_C(2147483648),	// FMOP4A_MZZ_S
    UINT64_C(2161115672),	// FMOP4S_M2Z2Z_D
    UINT64_C(2165309976),	// FMOP4S_M2Z2Z_H
    UINT64_C(2167407120),	// FMOP4S_M2Z2Z_HtoS
    UINT64_C(2148532752),	// FMOP4S_M2Z2Z_S
    UINT64_C(2160067096),	// FMOP4S_M2ZZ_D
    UINT64_C(2164261400),	// FMOP4S_M2ZZ_H
    UINT64_C(2166358544),	// FMOP4S_M2ZZ_HtoS
    UINT64_C(2147484176),	// FMOP4S_M2ZZ_S
    UINT64_C(2161115160),	// FMOP4S_MZ2Z_D
    UINT64_C(2165309464),	// FMOP4S_MZ2Z_H
    UINT64_C(2167406608),	// FMOP4S_MZ2Z_HtoS
    UINT64_C(2148532240),	// FMOP4S_MZ2Z_S
    UINT64_C(2160066584),	// FMOP4S_MZZ_D
    UINT64_C(2164260888),	// FMOP4S_MZZ_H
    UINT64_C(2166358032),	// FMOP4S_MZZ_HtoS
    UINT64_C(2147483664),	// FMOP4S_MZZ_S
    UINT64_C(2174746624),	// FMOPAL_MPPZZ
    UINT64_C(2157969416),	// FMOPA_MPPZZ_BtoH
    UINT64_C(2157969408),	// FMOPA_MPPZZ_BtoS
    UINT64_C(2160066560),	// FMOPA_MPPZZ_D
    UINT64_C(2172649480),	// FMOPA_MPPZZ_H
    UINT64_C(2155872256),	// FMOPA_MPPZZ_S
    UINT64_C(2174746640),	// FMOPSL_MPPZZ
    UINT64_C(2160066576),	// FMOPS_MPPZZ_D
    UINT64_C(2172649496),	// FMOPS_MPPZZ_H
    UINT64_C(2155872272),	// FMOPS_MPPZZ_S
    UINT64_C(2662203392),	// FMOVDXHighr
    UINT64_C(2657484800),	// FMOVDXr
    UINT64_C(509612032),	// FMOVDi
    UINT64_C(509624320),	// FMOVDr
    UINT64_C(518389760),	// FMOVHWr
    UINT64_C(2665873408),	// FMOVHXr
    UINT64_C(518000640),	// FMOVHi
    UINT64_C(518012928),	// FMOVHr
    UINT64_C(505806848),	// FMOVSWr
    UINT64_C(505417728),	// FMOVSi
    UINT64_C(505430016),	// FMOVSr
    UINT64_C(518455296),	// FMOVWHr
    UINT64_C(505872384),	// FMOVWSr
    UINT64_C(2662268928),	// FMOVXDHighr
    UINT64_C(2657550336),	// FMOVXDr
    UINT64_C(2665938944),	// FMOVXHr
    UINT64_C(251720704),	// FMOVv2f32_ns
    UINT64_C(1862333440),	// FMOVv2f64_ns
    UINT64_C(251722752),	// FMOVv4f16_ns
    UINT64_C(1325462528),	// FMOVv4f32_ns
    UINT64_C(1325464576),	// FMOVv8f16_ns
    UINT64_C(1709219840),	// FMSB_ZPmZZ_D
    UINT64_C(1700831232),	// FMSB_ZPmZZ_H
    UINT64_C(1705025536),	// FMSB_ZPmZZ_S
    UINT64_C(524320768),	// FMSUBDrrr
    UINT64_C(532709376),	// FMSUBHrrr
    UINT64_C(520126464),	// FMSUBSrrr
    UINT64_C(509609984),	// FMULDrr
    UINT64_C(517998592),	// FMULHrr
    UINT64_C(505415680),	// FMULSrr
    UINT64_C(1581259776),	// FMULX16
    UINT64_C(1579211776),	// FMULX32
    UINT64_C(1583406080),	// FMULX64
    UINT64_C(1707769856),	// FMULX_ZPmZ_D
    UINT64_C(1699381248),	// FMULX_ZPmZ_H
    UINT64_C(1703575552),	// FMULX_ZPmZ_S
    UINT64_C(2130743296),	// FMULXv1i16_indexed
    UINT64_C(2139131904),	// FMULXv1i32_indexed
    UINT64_C(2143326208),	// FMULXv1i64_indexed
    UINT64_C(237034496),	// FMULXv2f32
    UINT64_C(1314970624),	// FMULXv2f64
    UINT64_C(796954624),	// FMULXv2i32_indexed
    UINT64_C(1874890752),	// FMULXv2i64_indexed
    UINT64_C(239082496),	// FMULXv4f16
    UINT64_C(1310776320),	// FMULXv4f32
    UINT64_C(788566016),	// FMULXv4i16_indexed
    UINT64_C(1870696448),	// FMULXv4i32_indexed
    UINT64_C(1312824320),	// FMULXv8f16
    UINT64_C(1862307840),	// FMULXv8i16_indexed
    UINT64_C(3252741120),	// FMUL_2Z2Z_D
    UINT64_C(3244352512),	// FMUL_2Z2Z_H
    UINT64_C(3248546816),	// FMUL_2Z2Z_S
    UINT64_C(3252742144),	// FMUL_2ZZ_D
    UINT64_C(3244353536),	// FMUL_2ZZ_H
    UINT64_C(3248547840),	// FMUL_2ZZ_S
    UINT64_C(3252806656),	// FMUL_4Z4Z_D
    UINT64_C(3244418048),	// FMUL_4Z4Z_H
    UINT64_C(3248612352),	// FMUL_4Z4Z_S
    UINT64_C(3252807680),	// FMUL_4ZZ_D
    UINT64_C(3244419072),	// FMUL_4ZZ_H
    UINT64_C(3248613376),	// FMUL_4ZZ_S
    UINT64_C(1708818432),	// FMUL_ZPmI_D
    UINT64_C(1700429824),	// FMUL_ZPmI_H
    UINT64_C(1704624128),	// FMUL_ZPmI_S
    UINT64_C(1707245568),	// FMUL_ZPmZ_D
    UINT64_C(1698856960),	// FMUL_ZPmZ_H
    UINT64_C(1703051264),	// FMUL_ZPmZ_S
    UINT64_C(1692409856),	// FMUL_ZZZI_D
    UINT64_C(1679826944),	// FMUL_ZZZI_H
    UINT64_C(1688215552),	// FMUL_ZZZI_S
    UINT64_C(1707083776),	// FMUL_ZZZ_D
    UINT64_C(1698695168),	// FMUL_ZZZ_H
    UINT64_C(1702889472),	// FMUL_ZZZ_S
    UINT64_C(1593872384),	// FMULv1i16_indexed
    UINT64_C(1602260992),	// FMULv1i32_indexed
    UINT64_C(1606455296),	// FMULv1i64_indexed
    UINT64_C(773905408),	// FMULv2f32
    UINT64_C(1851841536),	// FMULv2f64
    UINT64_C(260083712),	// FMULv2i32_indexed
    UINT64_C(1338019840),	// FMULv2i64_indexed
    UINT64_C(775953408),	// FMULv4f16
    UINT64_C(1847647232),	// FMULv4f32
    UINT64_C(251695104),	// FMULv4i16_indexed
    UINT64_C(1333825536),	// FMULv4i32_indexed
    UINT64_C(1849695232),	// FMULv8f16
    UINT64_C(1325436928),	// FMULv8i16_indexed
    UINT64_C(509689856),	// FNEGDr
    UINT64_C(518078464),	// FNEGHr
    UINT64_C(505495552),	// FNEGSr
    UINT64_C(81633280),	// FNEG_ZPmZ_D
    UINT64_C(73244672),	// FNEG_ZPmZ_H
    UINT64_C(77438976),	// FNEG_ZPmZ_S
    UINT64_C(80584704),	// FNEG_ZPzZ_D
    UINT64_C(72196096),	// FNEG_ZPzZ_H
    UINT64_C(76390400),	// FNEG_ZPzZ_S
    UINT64_C(782301184),	// FNEGv2f32
    UINT64_C(1860237312),	// FNEGv2f64
    UINT64_C(788068352),	// FNEGv4f16
    UINT64_C(1856043008),	// FNEGv4f32
    UINT64_C(1861810176),	// FNEGv8f16
    UINT64_C(526385152),	// FNMADDDrrr
    UINT64_C(534773760),	// FNMADDHrrr
    UINT64_C(522190848),	// FNMADDSrrr
    UINT64_C(1709228032),	// FNMAD_ZPmZZ_D
    UINT64_C(1700839424),	// FNMAD_ZPmZZ_H
    UINT64_C(1705033728),	// FNMAD_ZPmZZ_S
    UINT64_C(1709195264),	// FNMLA_ZPmZZ_D
    UINT64_C(1700806656),	// FNMLA_ZPmZZ_H
    UINT64_C(1705000960),	// FNMLA_ZPmZZ_S
    UINT64_C(1709203456),	// FNMLS_ZPmZZ_D
    UINT64_C(1700814848),	// FNMLS_ZPmZZ_H
    UINT64_C(1705009152),	// FNMLS_ZPmZZ_S
    UINT64_C(1709236224),	// FNMSB_ZPmZZ_D
    UINT64_C(1700847616),	// FNMSB_ZPmZZ_H
    UINT64_C(1705041920),	// FNMSB_ZPmZZ_S
    UINT64_C(526417920),	// FNMSUBDrrr
    UINT64_C(534806528),	// FNMSUBHrrr
    UINT64_C(522223616),	// FNMSUBSrrr
    UINT64_C(509642752),	// FNMULDrr
    UINT64_C(518031360),	// FNMULHrr
    UINT64_C(505448448),	// FNMULSrr
    UINT64_C(1708011520),	// FRECPE_ZZ_D
    UINT64_C(1699622912),	// FRECPE_ZZ_H
    UINT64_C(1703817216),	// FRECPE_ZZ_S
    UINT64_C(1593432064),	// FRECPEv1f16
    UINT64_C(1587664896),	// FRECPEv1i32
    UINT64_C(1591859200),	// FRECPEv1i64
    UINT64_C(245487616),	// FRECPEv2f32
    UINT64_C(1323423744),	// FRECPEv2f64
    UINT64_C(251254784),	// FRECPEv4f16
    UINT64_C(1319229440),	// FRECPEv4f32
    UINT64_C(1324996608),	// FRECPEv8f16
    UINT64_C(1581267968),	// FRECPS16
    UINT64_C(1579219968),	// FRECPS32
    UINT64_C(1583414272),	// FRECPS64
    UINT64_C(1707087872),	// FRECPS_ZZZ_D
    UINT64_C(1698699264),	// FRECPS_ZZZ_H
    UINT64_C(1702893568),	// FRECPS_ZZZ_S
    UINT64_C(237042688),	// FRECPSv2f32
    UINT64_C(1314978816),	// FRECPSv2f64
    UINT64_C(239090688),	// FRECPSv4f16
    UINT64_C(1310784512),	// FRECPSv4f32
    UINT64_C(1312832512),	// FRECPSv8f16
    UINT64_C(1707909120),	// FRECPX_ZPmZ_D
    UINT64_C(1699520512),	// FRECPX_ZPmZ_H
    UINT64_C(1703714816),	// FRECPX_ZPmZ_S
    UINT64_C(1692106752),	// FRECPX_ZPzZ_D
    UINT64_C(1683718144),	// FRECPX_ZPzZ_H
    UINT64_C(1687912448),	// FRECPX_ZPzZ_S
    UINT64_C(1593440256),	// FRECPXv1f16
    UINT64_C(1587673088),	// FRECPXv1i32
    UINT64_C(1591867392),	// FRECPXv1i64
    UINT64_C(510181376),	// FRINT32XDr
    UINT64_C(505987072),	// FRINT32XSr
    UINT64_C(1695784960),	// FRINT32X_ZPmZ_D
    UINT64_C(1695653888),	// FRINT32X_ZPmZ_S
    UINT64_C(1679613952),	// FRINT32X_ZPzZ_D
    UINT64_C(1679597568),	// FRINT32X_ZPzZ_S
    UINT64_C(773974016),	// FRINT32Xv2f32
    UINT64_C(1851910144),	// FRINT32Xv2f64
    UINT64_C(1847715840),	// FRINT32Xv4f32
    UINT64_C(510148608),	// FRINT32ZDr
    UINT64_C(505954304),	// FRINT32ZSr
    UINT64_C(1695719424),	// FRINT32Z_ZPmZ_D
    UINT64_C(1695588352),	// FRINT32Z_ZPmZ_S
    UINT64_C(1679605760),	// FRINT32Z_ZPzZ_D
    UINT64_C(1679589376),	// FRINT32Z_ZPzZ_S
    UINT64_C(237103104),	// FRINT32Zv2f32
    UINT64_C(1315039232),	// FRINT32Zv2f64
    UINT64_C(1310844928),	// FRINT32Zv4f32
    UINT64_C(510246912),	// FRINT64XDr
    UINT64_C(506052608),	// FRINT64XSr
    UINT64_C(1696047104),	// FRINT64X_ZPmZ_D
    UINT64_C(1695916032),	// FRINT64X_ZPmZ_S
    UINT64_C(1679679488),	// FRINT64X_ZPzZ_D
    UINT64_C(1679663104),	// FRINT64X_ZPzZ_S
    UINT64_C(773978112),	// FRINT64Xv2f32
    UINT64_C(1851914240),	// FRINT64Xv2f64
    UINT64_C(1847719936),	// FRINT64Xv4f32
    UINT64_C(510214144),	// FRINT64ZDr
    UINT64_C(506019840),	// FRINT64ZSr
    UINT64_C(1695981568),	// FRINT64Z_ZPmZ_D
    UINT64_C(1695850496),	// FRINT64Z_ZPmZ_S
    UINT64_C(1679671296),	// FRINT64Z_ZPzZ_D
    UINT64_C(1679654912),	// FRINT64Z_ZPzZ_S
    UINT64_C(237107200),	// FRINT64Zv2f32
    UINT64_C(1315043328),	// FRINT64Zv2f64
    UINT64_C(1310849024),	// FRINT64Zv4f32
    UINT64_C(510017536),	// FRINTADr
    UINT64_C(518406144),	// FRINTAHr
    UINT64_C(505823232),	// FRINTASr
    UINT64_C(3249332224),	// FRINTA_2Z2Z_S
    UINT64_C(3250380800),	// FRINTA_4Z4Z_S
    UINT64_C(1707384832),	// FRINTA_ZPmZ_D
    UINT64_C(1698996224),	// FRINTA_ZPmZ_H
    UINT64_C(1703190528),	// FRINTA_ZPmZ_S
    UINT64_C(1691975680),	// FRINTA_ZPzZ_D
    UINT64_C(1683587072),	// FRINTA_ZPzZ_H
    UINT64_C(1687781376),	// FRINTA_ZPzZ_S
    UINT64_C(773949440),	// FRINTAv2f32
    UINT64_C(1851885568),	// FRINTAv2f64
    UINT64_C(779716608),	// FRINTAv4f16
    UINT64_C(1847691264),	// FRINTAv4f32
    UINT64_C(1853458432),	// FRINTAv8f16
    UINT64_C(510115840),	// FRINTIDr
    UINT64_C(518504448),	// FRINTIHr
    UINT64_C(505921536),	// FRINTISr
    UINT64_C(1707581440),	// FRINTI_ZPmZ_D
    UINT64_C(1699192832),	// FRINTI_ZPmZ_H
    UINT64_C(1703387136),	// FRINTI_ZPmZ_S
    UINT64_C(1692000256),	// FRINTI_ZPzZ_D
    UINT64_C(1683611648),	// FRINTI_ZPzZ_H
    UINT64_C(1687805952),	// FRINTI_ZPzZ_S
    UINT64_C(782342144),	// FRINTIv2f32
    UINT64_C(1860278272),	// FRINTIv2f64
    UINT64_C(788109312),	// FRINTIv4f16
    UINT64_C(1856083968),	// FRINTIv4f32
    UINT64_C(1861851136),	// FRINTIv8f16
    UINT64_C(509952000),	// FRINTMDr
    UINT64_C(518340608),	// FRINTMHr
    UINT64_C(505757696),	// FRINTMSr
    UINT64_C(3249201152),	// FRINTM_2Z2Z_S
    UINT64_C(3250249728),	// FRINTM_4Z4Z_S
    UINT64_C(1707253760),	// FRINTM_ZPmZ_D
    UINT64_C(1698865152),	// FRINTM_ZPmZ_H
    UINT64_C(1703059456),	// FRINTM_ZPmZ_S
    UINT64_C(1691926528),	// FRINTM_ZPzZ_D
    UINT64_C(1683537920),	// FRINTM_ZPzZ_H
    UINT64_C(1687732224),	// FRINTM_ZPzZ_S
    UINT64_C(237082624),	// FRINTMv2f32
    UINT64_C(1315018752),	// FRINTMv2f64
    UINT64_C(242849792),	// FRINTMv4f16
    UINT64_C(1310824448),	// FRINTMv4f32
    UINT64_C(1316591616),	// FRINTMv8f16
    UINT64_C(509886464),	// FRINTNDr
    UINT64_C(518275072),	// FRINTNHr
    UINT64_C(505692160),	// FRINTNSr
    UINT64_C(3249070080),	// FRINTN_2Z2Z_S
    UINT64_C(3250118656),	// FRINTN_4Z4Z_S
    UINT64_C(1707122688),	// FRINTN_ZPmZ_D
    UINT64_C(1698734080),	// FRINTN_ZPmZ_H
    UINT64_C(1702928384),	// FRINTN_ZPmZ_S
    UINT64_C(1691910144),	// FRINTN_ZPzZ_D
    UINT64_C(1683521536),	// FRINTN_ZPzZ_H
    UINT64_C(1687715840),	// FRINTN_ZPzZ_S
    UINT64_C(237078528),	// FRINTNv2f32
    UINT64_C(1315014656),	// FRINTNv2f64
    UINT64_C(242845696),	// FRINTNv4f16
    UINT64_C(1310820352),	// FRINTNv4f32
    UINT64_C(1316587520),	// FRINTNv8f16
    UINT64_C(509919232),	// FRINTPDr
    UINT64_C(518307840),	// FRINTPHr
    UINT64_C(505724928),	// FRINTPSr
    UINT64_C(3249135616),	// FRINTP_2Z2Z_S
    UINT64_C(3250184192),	// FRINTP_4Z4Z_S
    UINT64_C(1707188224),	// FRINTP_ZPmZ_D
    UINT64_C(1698799616),	// FRINTP_ZPmZ_H
    UINT64_C(1702993920),	// FRINTP_ZPmZ_S
    UINT64_C(1691918336),	// FRINTP_ZPzZ_D
    UINT64_C(1683529728),	// FRINTP_ZPzZ_H
    UINT64_C(1687724032),	// FRINTP_ZPzZ_S
    UINT64_C(245467136),	// FRINTPv2f32
    UINT64_C(1323403264),	// FRINTPv2f64
    UINT64_C(251234304),	// FRINTPv4f16
    UINT64_C(1319208960),	// FRINTPv4f32
    UINT64_C(1324976128),	// FRINTPv8f16
    UINT64_C(510083072),	// FRINTXDr
    UINT64_C(518471680),	// FRINTXHr
    UINT64_C(505888768),	// FRINTXSr
    UINT64_C(1707515904),	// FRINTX_ZPmZ_D
    UINT64_C(1699127296),	// FRINTX_ZPmZ_H
    UINT64_C(1703321600),	// FRINTX_ZPmZ_S
    UINT64_C(1691992064),	// FRINTX_ZPzZ_D
    UINT64_C(1683603456),	// FRINTX_ZPzZ_H
    UINT64_C(1687797760),	// FRINTX_ZPzZ_S
    UINT64_C(773953536),	// FRINTXv2f32
    UINT64_C(1851889664),	// FRINTXv2f64
    UINT64_C(779720704),	// FRINTXv4f16
    UINT64_C(1847695360),	// FRINTXv4f32
    UINT64_C(1853462528),	// FRINTXv8f16
    UINT64_C(509984768),	// FRINTZDr
    UINT64_C(518373376),	// FRINTZHr
    UINT64_C(505790464),	// FRINTZSr
    UINT64_C(1707319296),	// FRINTZ_ZPmZ_D
    UINT64_C(1698930688),	// FRINTZ_ZPmZ_H
    UINT64_C(1703124992),	// FRINTZ_ZPmZ_S
    UINT64_C(1691934720),	// FRINTZ_ZPzZ_D
    UINT64_C(1683546112),	// FRINTZ_ZPzZ_H
    UINT64_C(1687740416),	// FRINTZ_ZPzZ_S
    UINT64_C(245471232),	// FRINTZv2f32
    UINT64_C(1323407360),	// FRINTZv2f64
    UINT64_C(251238400),	// FRINTZv4f16
    UINT64_C(1319213056),	// FRINTZv4f32
    UINT64_C(1324980224),	// FRINTZv8f16
    UINT64_C(1708077056),	// FRSQRTE_ZZ_D
    UINT64_C(1699688448),	// FRSQRTE_ZZ_H
    UINT64_C(1703882752),	// FRSQRTE_ZZ_S
    UINT64_C(2130302976),	// FRSQRTEv1f16
    UINT64_C(2124535808),	// FRSQRTEv1i32
    UINT64_C(2128730112),	// FRSQRTEv1i64
    UINT64_C(782358528),	// FRSQRTEv2f32
    UINT64_C(1860294656),	// FRSQRTEv2f64
    UINT64_C(788125696),	// FRSQRTEv4f16
    UINT64_C(1856100352),	// FRSQRTEv4f32
    UINT64_C(1861867520),	// FRSQRTEv8f16
    UINT64_C(1589656576),	// FRSQRTS16
    UINT64_C(1587608576),	// FRSQRTS32
    UINT64_C(1591802880),	// FRSQRTS64
    UINT64_C(1707088896),	// FRSQRTS_ZZZ_D
    UINT64_C(1698700288),	// FRSQRTS_ZZZ_H
    UINT64_C(1702894592),	// FRSQRTS_ZZZ_S
    UINT64_C(245431296),	// FRSQRTSv2f32
    UINT64_C(1323367424),	// FRSQRTSv2f64
    UINT64_C(247479296),	// FRSQRTSv4f16
    UINT64_C(1319173120),	// FRSQRTSv4f32
    UINT64_C(1321221120),	// FRSQRTSv8f16
    UINT64_C(3252728192),	// FSCALE_2Z2Z_D
    UINT64_C(3244339584),	// FSCALE_2Z2Z_H
    UINT64_C(3248533888),	// FSCALE_2Z2Z_S
    UINT64_C(3252724096),	// FSCALE_2ZZ_D
    UINT64_C(3244335488),	// FSCALE_2ZZ_H
    UINT64_C(3248529792),	// FSCALE_2ZZ_S
    UINT64_C(3252730240),	// FSCALE_4Z4Z_D
    UINT64_C(3244341632),	// FSCALE_4Z4Z_H
    UINT64_C(3248535936),	// FSCALE_4Z4Z_S
    UINT64_C(3252726144),	// FSCALE_4ZZ_D
    UINT64_C(3244337536),	// FSCALE_4ZZ_H
    UINT64_C(3248531840),	// FSCALE_4ZZ_S
    UINT64_C(1707704320),	// FSCALE_ZPmZ_D
    UINT64_C(1699315712),	// FSCALE_ZPmZ_H
    UINT64_C(1703510016),	// FSCALE_ZPmZ_S
    UINT64_C(782302208),	// FSCALEv2f32
    UINT64_C(1860238336),	// FSCALEv2f64
    UINT64_C(784350208),	// FSCALEv4f16
    UINT64_C(1856044032),	// FSCALEv4f32
    UINT64_C(1858092032),	// FSCALEv8f16
    UINT64_C(509722624),	// FSQRTDr
    UINT64_C(518111232),	// FSQRTHr
    UINT64_C(505528320),	// FSQRTSr
    UINT64_C(1692114944),	// FSQRT_ZPZz_D
    UINT64_C(1683726336),	// FSQRT_ZPZz_H
    UINT64_C(1687920640),	// FSQRT_ZPZz_S
    UINT64_C(1707974656),	// FSQRT_ZPmZ_D
    UINT64_C(1699586048),	// FSQRT_ZPmZ_H
    UINT64_C(1703780352),	// FSQRT_ZPmZ_S
    UINT64_C(782366720),	// FSQRTv2f32
    UINT64_C(1860302848),	// FSQRTv2f64
    UINT64_C(788133888),	// FSQRTv4f16
    UINT64_C(1856108544),	// FSQRTv4f32
    UINT64_C(1861875712),	// FSQRTv8f16
    UINT64_C(509622272),	// FSUBDrr
    UINT64_C(518010880),	// FSUBHrr
    UINT64_C(1708883968),	// FSUBR_ZPmI_D
    UINT64_C(1700495360),	// FSUBR_ZPmI_H
    UINT64_C(1704689664),	// FSUBR_ZPmI_S
    UINT64_C(1707311104),	// FSUBR_ZPmZ_D
    UINT64_C(1698922496),	// FSUBR_ZPmZ_H
    UINT64_C(1703116800),	// FSUBR_ZPmZ_S
    UINT64_C(505427968),	// FSUBSrr
    UINT64_C(3252689928),	// FSUB_VG2_M2Z_D
    UINT64_C(3248757768),	// FSUB_VG2_M2Z_H
    UINT64_C(3248495624),	// FSUB_VG2_M2Z_S
    UINT64_C(3252755464),	// FSUB_VG4_M4Z_D
    UINT64_C(3248823304),	// FSUB_VG4_M4Z_H
    UINT64_C(3248561160),	// FSUB_VG4_M4Z_S
    UINT64_C(1708752896),	// FSUB_ZPmI_D
    UINT64_C(1700364288),	// FSUB_ZPmI_H
    UINT64_C(1704558592),	// FSUB_ZPmI_S
    UINT64_C(1707180032),	// FSUB_ZPmZ_D
    UINT64_C(1698791424),	// FSUB_ZPmZ_H
    UINT64_C(1702985728),	// FSUB_ZPmZ_S
    UINT64_C(1707082752),	// FSUB_ZZZ_D
    UINT64_C(1698694144),	// FSUB_ZZZ_H
    UINT64_C(1702888448),	// FSUB_ZZZ_S
    UINT64_C(245421056),	// FSUBv2f32
    UINT64_C(1323357184),	// FSUBv2f64
    UINT64_C(247469056),	// FSUBv4f16
    UINT64_C(1319162880),	// FSUBv4f32
    UINT64_C(1321210880),	// FSUBv8f16
    UINT64_C(1708163072),	// FTMAD_ZZI_D
    UINT64_C(1699774464),	// FTMAD_ZZI_H
    UINT64_C(1703968768),	// FTMAD_ZZI_S
    UINT64_C(2153775112),	// FTMOPA_M2ZZZI_BtoH
    UINT64_C(2153775104),	// FTMOPA_M2ZZZI_BtoS
    UINT64_C(2168455176),	// FTMOPA_M2ZZZI_HtoH
    UINT64_C(2170552320),	// FTMOPA_M2ZZZI_HtoS
    UINT64_C(2151677952),	// FTMOPA_M2ZZZI_StoS
    UINT64_C(1707084800),	// FTSMUL_ZZZ_D
    UINT64_C(1698696192),	// FTSMUL_ZZZ_H
    UINT64_C(1702890496),	// FTSMUL_ZZZ_S
    UINT64_C(81833984),	// FTSSEL_ZZZ_D
    UINT64_C(73445376),	// FTSSEL_ZZZ_H
    UINT64_C(77639680),	// FTSSEL_ZZZ_S
    UINT64_C(3251636224),	// FVDOTB_VG4_M2ZZI_BtoS
    UINT64_C(3251636240),	// FVDOTT_VG4_M2ZZI_BtoS
    UINT64_C(3251638304),	// FVDOT_VG2_M2ZZI_BtoH
    UINT64_C(3243245576),	// FVDOT_VG2_M2ZZI_HtoS
    UINT64_C(3574101951),	// GCSPOPCX
    UINT64_C(3576395552),	// GCSPOPM
    UINT64_C(3574101983),	// GCSPOPX
    UINT64_C(3574298368),	// GCSPUSHM
    UINT64_C(3574101919),	// GCSPUSHX
    UINT64_C(3574298432),	// GCSSS1
    UINT64_C(3576395616),	// GCSSS2
    UINT64_C(3642690560),	// GCSSTR
    UINT64_C(3642694656),	// GCSSTTR
    UINT64_C(3292577792),	// GLD1B_D
    UINT64_C(3290480640),	// GLD1B_D_IMM
    UINT64_C(3292545024),	// GLD1B_D_SXTW
    UINT64_C(3288350720),	// GLD1B_D_UXTW
    UINT64_C(2216738816),	// GLD1B_S_IMM
    UINT64_C(2218803200),	// GLD1B_S_SXTW
    UINT64_C(2214608896),	// GLD1B_S_UXTW
    UINT64_C(3317743616),	// GLD1D
    UINT64_C(3315646464),	// GLD1D_IMM
    UINT64_C(3319840768),	// GLD1D_SCALED
    UINT64_C(3317710848),	// GLD1D_SXTW
    UINT64_C(3319808000),	// GLD1D_SXTW_SCALED
    UINT64_C(3313516544),	// GLD1D_UXTW
    UINT64_C(3315613696),	// GLD1D_UXTW_SCALED
    UINT64_C(3300966400),	// GLD1H_D
    UINT64_C(3298869248),	// GLD1H_D_IMM
    UINT64_C(3303063552),	// GLD1H_D_SCALED
    UINT64_C(3300933632),	// GLD1H_D_SXTW
    UINT64_C(3303030784),	// GLD1H_D_SXTW_SCALED
    UINT64_C(3296739328),	// GLD1H_D_UXTW
    UINT64_C(3298836480),	// GLD1H_D_UXTW_SCALED
    UINT64_C(2225127424),	// GLD1H_S_IMM
    UINT64_C(2227191808),	// GLD1H_S_SXTW
    UINT64_C(2229288960),	// GLD1H_S_SXTW_SCALED
    UINT64_C(2222997504),	// GLD1H_S_UXTW
    UINT64_C(2225094656),	// GLD1H_S_UXTW_SCALED
    UINT64_C(3288375296),	// GLD1Q
    UINT64_C(3292561408),	// GLD1SB_D
    UINT64_C(3290464256),	// GLD1SB_D_IMM
    UINT64_C(3292528640),	// GLD1SB_D_SXTW
    UINT64_C(3288334336),	// GLD1SB_D_UXTW
    UINT64_C(2216722432),	// GLD1SB_S_IMM
    UINT64_C(2218786816),	// GLD1SB_S_SXTW
    UINT64_C(2214592512),	// GLD1SB_S_UXTW
    UINT64_C(3300950016),	// GLD1SH_D
    UINT64_C(3298852864),	// GLD1SH_D_IMM
    UINT64_C(3303047168),	// GLD1SH_D_SCALED
    UINT64_C(3300917248),	// GLD1SH_D_SXTW
    UINT64_C(3303014400),	// GLD1SH_D_SXTW_SCALED
    UINT64_C(3296722944),	// GLD1SH_D_UXTW
    UINT64_C(3298820096),	// GLD1SH_D_UXTW_SCALED
    UINT64_C(2225111040),	// GLD1SH_S_IMM
    UINT64_C(2227175424),	// GLD1SH_S_SXTW
    UINT64_C(2229272576),	// GLD1SH_S_SXTW_SCALED
    UINT64_C(2222981120),	// GLD1SH_S_UXTW
    UINT64_C(2225078272),	// GLD1SH_S_UXTW_SCALED
    UINT64_C(3309338624),	// GLD1SW_D
    UINT64_C(3307241472),	// GLD1SW_D_IMM
    UINT64_C(3311435776),	// GLD1SW_D_SCALED
    UINT64_C(3309305856),	// GLD1SW_D_SXTW
    UINT64_C(3311403008),	// GLD1SW_D_SXTW_SCALED
    UINT64_C(3305111552),	// GLD1SW_D_UXTW
    UINT64_C(3307208704),	// GLD1SW_D_UXTW_SCALED
    UINT64_C(3309355008),	// GLD1W_D
    UINT64_C(3307257856),	// GLD1W_D_IMM
    UINT64_C(3311452160),	// GLD1W_D_SCALED
    UINT64_C(3309322240),	// GLD1W_D_SXTW
    UINT64_C(3311419392),	// GLD1W_D_SXTW_SCALED
    UINT64_C(3305127936),	// GLD1W_D_UXTW
    UINT64_C(3307225088),	// GLD1W_D_UXTW_SCALED
    UINT64_C(2233516032),	// GLD1W_IMM
    UINT64_C(2235580416),	// GLD1W_SXTW
    UINT64_C(2237677568),	// GLD1W_SXTW_SCALED
    UINT64_C(2231386112),	// GLD1W_UXTW
    UINT64_C(2233483264),	// GLD1W_UXTW_SCALED
    UINT64_C(3292585984),	// GLDFF1B_D
    UINT64_C(3290488832),	// GLDFF1B_D_IMM
    UINT64_C(3292553216),	// GLDFF1B_D_SXTW
    UINT64_C(3288358912),	// GLDFF1B_D_UXTW
    UINT64_C(2216747008),	// GLDFF1B_S_IMM
    UINT64_C(2218811392),	// GLDFF1B_S_SXTW
    UINT64_C(2214617088),	// GLDFF1B_S_UXTW
    UINT64_C(3317751808),	// GLDFF1D
    UINT64_C(3315654656),	// GLDFF1D_IMM
    UINT64_C(3319848960),	// GLDFF1D_SCALED
    UINT64_C(3317719040),	// GLDFF1D_SXTW
    UINT64_C(3319816192),	// GLDFF1D_SXTW_SCALED
    UINT64_C(3313524736),	// GLDFF1D_UXTW
    UINT64_C(3315621888),	// GLDFF1D_UXTW_SCALED
    UINT64_C(3300974592),	// GLDFF1H_D
    UINT64_C(3298877440),	// GLDFF1H_D_IMM
    UINT64_C(3303071744),	// GLDFF1H_D_SCALED
    UINT64_C(3300941824),	// GLDFF1H_D_SXTW
    UINT64_C(3303038976),	// GLDFF1H_D_SXTW_SCALED
    UINT64_C(3296747520),	// GLDFF1H_D_UXTW
    UINT64_C(3298844672),	// GLDFF1H_D_UXTW_SCALED
    UINT64_C(2225135616),	// GLDFF1H_S_IMM
    UINT64_C(2227200000),	// GLDFF1H_S_SXTW
    UINT64_C(2229297152),	// GLDFF1H_S_SXTW_SCALED
    UINT64_C(2223005696),	// GLDFF1H_S_UXTW
    UINT64_C(2225102848),	// GLDFF1H_S_UXTW_SCALED
    UINT64_C(3292569600),	// GLDFF1SB_D
    UINT64_C(3290472448),	// GLDFF1SB_D_IMM
    UINT64_C(3292536832),	// GLDFF1SB_D_SXTW
    UINT64_C(3288342528),	// GLDFF1SB_D_UXTW
    UINT64_C(2216730624),	// GLDFF1SB_S_IMM
    UINT64_C(2218795008),	// GLDFF1SB_S_SXTW
    UINT64_C(2214600704),	// GLDFF1SB_S_UXTW
    UINT64_C(3300958208),	// GLDFF1SH_D
    UINT64_C(3298861056),	// GLDFF1SH_D_IMM
    UINT64_C(3303055360),	// GLDFF1SH_D_SCALED
    UINT64_C(3300925440),	// GLDFF1SH_D_SXTW
    UINT64_C(3303022592),	// GLDFF1SH_D_SXTW_SCALED
    UINT64_C(3296731136),	// GLDFF1SH_D_UXTW
    UINT64_C(3298828288),	// GLDFF1SH_D_UXTW_SCALED
    UINT64_C(2225119232),	// GLDFF1SH_S_IMM
    UINT64_C(2227183616),	// GLDFF1SH_S_SXTW
    UINT64_C(2229280768),	// GLDFF1SH_S_SXTW_SCALED
    UINT64_C(2222989312),	// GLDFF1SH_S_UXTW
    UINT64_C(2225086464),	// GLDFF1SH_S_UXTW_SCALED
    UINT64_C(3309346816),	// GLDFF1SW_D
    UINT64_C(3307249664),	// GLDFF1SW_D_IMM
    UINT64_C(3311443968),	// GLDFF1SW_D_SCALED
    UINT64_C(3309314048),	// GLDFF1SW_D_SXTW
    UINT64_C(3311411200),	// GLDFF1SW_D_SXTW_SCALED
    UINT64_C(3305119744),	// GLDFF1SW_D_UXTW
    UINT64_C(3307216896),	// GLDFF1SW_D_UXTW_SCALED
    UINT64_C(3309363200),	// GLDFF1W_D
    UINT64_C(3307266048),	// GLDFF1W_D_IMM
    UINT64_C(3311460352),	// GLDFF1W_D_SCALED
    UINT64_C(3309330432),	// GLDFF1W_D_SXTW
    UINT64_C(3311427584),	// GLDFF1W_D_SXTW_SCALED
    UINT64_C(3305136128),	// GLDFF1W_D_UXTW
    UINT64_C(3307233280),	// GLDFF1W_D_UXTW_SCALED
    UINT64_C(2233524224),	// GLDFF1W_IMM
    UINT64_C(2235588608),	// GLDFF1W_SXTW
    UINT64_C(2237685760),	// GLDFF1W_SXTW_SCALED
    UINT64_C(2231394304),	// GLDFF1W_UXTW
    UINT64_C(2233491456),	// GLDFF1W_UXTW_SCALED
    UINT64_C(2596279296),	// GMI
    UINT64_C(3573751839),	// HINT
    UINT64_C(1172357120),	// HISTCNT_ZPzZZ_D
    UINT64_C(1168162816),	// HISTCNT_ZPzZZ_S
    UINT64_C(1159766016),	// HISTSEG_ZZZ
    UINT64_C(3560964096),	// HLT
    UINT64_C(3556769794),	// HVC
    UINT64_C(70311936),	// INCB_XPiI
    UINT64_C(82894848),	// INCD_XPiI
    UINT64_C(82886656),	// INCD_ZPiI
    UINT64_C(74506240),	// INCH_XPiI
    UINT64_C(74498048),	// INCH_ZPiI
    UINT64_C(623675392),	// INCP_XP_B
    UINT64_C(636258304),	// INCP_XP_D
    UINT64_C(627869696),	// INCP_XP_H
    UINT64_C(632064000),	// INCP_XP_S
    UINT64_C(636256256),	// INCP_ZP_D
    UINT64_C(627867648),	// INCP_ZP_H
    UINT64_C(632061952),	// INCP_ZP_S
    UINT64_C(78700544),	// INCW_XPiI
    UINT64_C(78692352),	// INCW_ZPiI
    UINT64_C(69222400),	// INDEX_II_B
    UINT64_C(81805312),	// INDEX_II_D
    UINT64_C(73416704),	// INDEX_II_H
    UINT64_C(77611008),	// INDEX_II_S
    UINT64_C(69224448),	// INDEX_IR_B
    UINT64_C(81807360),	// INDEX_IR_D
    UINT64_C(73418752),	// INDEX_IR_H
    UINT64_C(77613056),	// INDEX_IR_S
    UINT64_C(69223424),	// INDEX_RI_B
    UINT64_C(81806336),	// INDEX_RI_D
    UINT64_C(73417728),	// INDEX_RI_H
    UINT64_C(77612032),	// INDEX_RI_S
    UINT64_C(69225472),	// INDEX_RR_B
    UINT64_C(81808384),	// INDEX_RR_D
    UINT64_C(73419776),	// INDEX_RR_H
    UINT64_C(77614080),	// INDEX_RR_S
    UINT64_C(3221225472),	// INSERT_MXIPZ_H_B
    UINT64_C(3233808384),	// INSERT_MXIPZ_H_D
    UINT64_C(3225419776),	// INSERT_MXIPZ_H_H
    UINT64_C(3233873920),	// INSERT_MXIPZ_H_Q
    UINT64_C(3229614080),	// INSERT_MXIPZ_H_S
    UINT64_C(3221258240),	// INSERT_MXIPZ_V_B
    UINT64_C(3233841152),	// INSERT_MXIPZ_V_D
    UINT64_C(3225452544),	// INSERT_MXIPZ_V_H
    UINT64_C(3233906688),	// INSERT_MXIPZ_V_Q
    UINT64_C(3229646848),	// INSERT_MXIPZ_V_S
    UINT64_C(86259712),	// INSR_ZR_B
    UINT64_C(98842624),	// INSR_ZR_D
    UINT64_C(90454016),	// INSR_ZR_H
    UINT64_C(94648320),	// INSR_ZR_S
    UINT64_C(87308288),	// INSR_ZV_B
    UINT64_C(99891200),	// INSR_ZV_D
    UINT64_C(91502592),	// INSR_ZV_H
    UINT64_C(95696896),	// INSR_ZV_S
    UINT64_C(1308761088),	// INSvi16gpr
    UINT64_C(1845625856),	// INSvi16lane
    UINT64_C(1308892160),	// INSvi32gpr
    UINT64_C(1845756928),	// INSvi32lane
    UINT64_C(1309154304),	// INSvi64gpr
    UINT64_C(1846019072),	// INSvi64lane
    UINT64_C(1308695552),	// INSvi8gpr
    UINT64_C(1845560320),	// INSvi8lane
    UINT64_C(2596278272),	// IRG
    UINT64_C(3573756127),	// ISB
    UINT64_C(86024192),	// LASTA_RPZ_B
    UINT64_C(98607104),	// LASTA_RPZ_D
    UINT64_C(90218496),	// LASTA_RPZ_H
    UINT64_C(94412800),	// LASTA_RPZ_S
    UINT64_C(86147072),	// LASTA_VPZ_B
    UINT64_C(98729984),	// LASTA_VPZ_D
    UINT64_C(90341376),	// LASTA_VPZ_H
    UINT64_C(94535680),	// LASTA_VPZ_S
    UINT64_C(86089728),	// LASTB_RPZ_B
    UINT64_C(98672640),	// LASTB_RPZ_D
    UINT64_C(90284032),	// LASTB_RPZ_H
    UINT64_C(94478336),	// LASTB_RPZ_S
    UINT64_C(86212608),	// LASTB_VPZ_B
    UINT64_C(98795520),	// LASTB_VPZ_D
    UINT64_C(90406912),	// LASTB_VPZ_H
    UINT64_C(94601216),	// LASTB_VPZ_S
    UINT64_C(623017984),	// LASTP_XPP_B
    UINT64_C(635600896),	// LASTP_XPP_D
    UINT64_C(627212288),	// LASTP_XPP_H
    UINT64_C(631406592),	// LASTP_XPP_S
    UINT64_C(2751479808),	// LD1B
    UINT64_C(2684354560),	// LD1B_2Z
    UINT64_C(2688548864),	// LD1B_2Z_IMM
    UINT64_C(2701131776),	// LD1B_2Z_STRIDED
    UINT64_C(2705326080),	// LD1B_2Z_STRIDED_IMM
    UINT64_C(2684387328),	// LD1B_4Z
    UINT64_C(2688581632),	// LD1B_4Z_IMM
    UINT64_C(2701164544),	// LD1B_4Z_STRIDED
    UINT64_C(2705358848),	// LD1B_4Z_STRIDED_IMM
    UINT64_C(2757771264),	// LD1B_D
    UINT64_C(2757795840),	// LD1B_D_IMM
    UINT64_C(2753576960),	// LD1B_H
    UINT64_C(2753601536),	// LD1B_H_IMM
    UINT64_C(2751504384),	// LD1B_IMM
    UINT64_C(2755674112),	// LD1B_S
    UINT64_C(2755698688),	// LD1B_S_IMM
    UINT64_C(2782937088),	// LD1D
    UINT64_C(2684379136),	// LD1D_2Z
    UINT64_C(2688573440),	// LD1D_2Z_IMM
    UINT64_C(2701156352),	// LD1D_2Z_STRIDED
    UINT64_C(2705350656),	// LD1D_2Z_STRIDED_IMM
    UINT64_C(2684411904),	// LD1D_4Z
    UINT64_C(2688606208),	// LD1D_4Z_IMM
    UINT64_C(2701189120),	// LD1D_4Z_STRIDED
    UINT64_C(2705383424),	// LD1D_4Z_STRIDED_IMM
    UINT64_C(2782961664),	// LD1D_IMM
    UINT64_C(2776662016),	// LD1D_Q
    UINT64_C(2777686016),	// LD1D_Q_IMM
    UINT64_C(1279270912),	// LD1Fourv16b
    UINT64_C(1287659520),	// LD1Fourv16b_POST
    UINT64_C(205532160),	// LD1Fourv1d
    UINT64_C(213920768),	// LD1Fourv1d_POST
    UINT64_C(1279273984),	// LD1Fourv2d
    UINT64_C(1287662592),	// LD1Fourv2d_POST
    UINT64_C(205531136),	// LD1Fourv2s
    UINT64_C(213919744),	// LD1Fourv2s_POST
    UINT64_C(205530112),	// LD1Fourv4h
    UINT64_C(213918720),	// LD1Fourv4h_POST
    UINT64_C(1279272960),	// LD1Fourv4s
    UINT64_C(1287661568),	// LD1Fourv4s_POST
    UINT64_C(205529088),	// LD1Fourv8b
    UINT64_C(213917696),	// LD1Fourv8b_POST
    UINT64_C(1279271936),	// LD1Fourv8h
    UINT64_C(1287660544),	// LD1Fourv8h_POST
    UINT64_C(2761965568),	// LD1H
    UINT64_C(2684362752),	// LD1H_2Z
    UINT64_C(2688557056),	// LD1H_2Z_IMM
    UINT64_C(2701139968),	// LD1H_2Z_STRIDED
    UINT64_C(2705334272),	// LD1H_2Z_STRIDED_IMM
    UINT64_C(2684395520),	// LD1H_4Z
    UINT64_C(2688589824),	// LD1H_4Z_IMM
    UINT64_C(2701172736),	// LD1H_4Z_STRIDED
    UINT64_C(2705367040),	// LD1H_4Z_STRIDED_IMM
    UINT64_C(2766159872),	// LD1H_D
    UINT64_C(2766184448),	// LD1H_D_IMM
    UINT64_C(2761990144),	// LD1H_IMM
    UINT64_C(2764062720),	// LD1H_S
    UINT64_C(2764087296),	// LD1H_S_IMM
    UINT64_C(1279291392),	// LD1Onev16b
    UINT64_C(1287680000),	// LD1Onev16b_POST
    UINT64_C(205552640),	// LD1Onev1d
    UINT64_C(213941248),	// LD1Onev1d_POST
    UINT64_C(1279294464),	// LD1Onev2d
    UINT64_C(1287683072),	// LD1Onev2d_POST
    UINT64_C(205551616),	// LD1Onev2s
    UINT64_C(213940224),	// LD1Onev2s_POST
    UINT64_C(205550592),	// LD1Onev4h
    UINT64_C(213939200),	// LD1Onev4h_POST
    UINT64_C(1279293440),	// LD1Onev4s
    UINT64_C(1287682048),	// LD1Onev4s_POST
    UINT64_C(205549568),	// LD1Onev8b
    UINT64_C(213938176),	// LD1Onev8b_POST
    UINT64_C(1279292416),	// LD1Onev8h
    UINT64_C(1287681024),	// LD1Onev8h_POST
    UINT64_C(2218844160),	// LD1RB_D_IMM
    UINT64_C(2218827776),	// LD1RB_H_IMM
    UINT64_C(2218819584),	// LD1RB_IMM
    UINT64_C(2218835968),	// LD1RB_S_IMM
    UINT64_C(2244009984),	// LD1RD_IMM
    UINT64_C(2227232768),	// LD1RH_D_IMM
    UINT64_C(2227216384),	// LD1RH_IMM
    UINT64_C(2227224576),	// LD1RH_S_IMM
    UINT64_C(2753560576),	// LD1RO_B
    UINT64_C(2753568768),	// LD1RO_B_IMM
    UINT64_C(2778726400),	// LD1RO_D
    UINT64_C(2778734592),	// LD1RO_D_IMM
    UINT64_C(2761949184),	// LD1RO_H
    UINT64_C(2761957376),	// LD1RO_H_IMM
    UINT64_C(2770337792),	// LD1RO_W
    UINT64_C(2770345984),	// LD1RO_W_IMM
    UINT64_C(2751463424),	// LD1RQ_B
    UINT64_C(2751471616),	// LD1RQ_B_IMM
    UINT64_C(2776629248),	// LD1RQ_D
    UINT64_C(2776637440),	// LD1RQ_D_IMM
    UINT64_C(2759852032),	// LD1RQ_H
    UINT64_C(2759860224),	// LD1RQ_H_IMM
    UINT64_C(2768240640),	// LD1RQ_W
    UINT64_C(2768248832),	// LD1RQ_W_IMM
    UINT64_C(2243985408),	// LD1RSB_D_IMM
    UINT64_C(2244001792),	// LD1RSB_H_IMM
    UINT64_C(2243993600),	// LD1RSB_S_IMM
    UINT64_C(2235596800),	// LD1RSH_D_IMM
    UINT64_C(2235604992),	// LD1RSH_S_IMM
    UINT64_C(2227208192),	// LD1RSW_IMM
    UINT64_C(2235621376),	// LD1RW_D_IMM
    UINT64_C(2235613184),	// LD1RW_IMM
    UINT64_C(1296089088),	// LD1Rv16b
    UINT64_C(1304477696),	// LD1Rv16b_POST
    UINT64_C(222350336),	// LD1Rv1d
    UINT64_C(230738944),	// LD1Rv1d_POST
    UINT64_C(1296092160),	// LD1Rv2d
    UINT64_C(1304480768),	// LD1Rv2d_POST
    UINT64_C(222349312),	// LD1Rv2s
    UINT64_C(230737920),	// LD1Rv2s_POST
    UINT64_C(222348288),	// LD1Rv4h
    UINT64_C(230736896),	// LD1Rv4h_POST
    UINT64_C(1296091136),	// LD1Rv4s
    UINT64_C(1304479744),	// LD1Rv4s_POST
    UINT64_C(222347264),	// LD1Rv8b
    UINT64_C(230735872),	// LD1Rv8b_POST
    UINT64_C(1296090112),	// LD1Rv8h
    UINT64_C(1304478720),	// LD1Rv8h_POST
    UINT64_C(2776645632),	// LD1SB_D
    UINT64_C(2776670208),	// LD1SB_D_IMM
    UINT64_C(2780839936),	// LD1SB_H
    UINT64_C(2780864512),	// LD1SB_H_IMM
    UINT64_C(2778742784),	// LD1SB_S
    UINT64_C(2778767360),	// LD1SB_S_IMM
    UINT64_C(2768257024),	// LD1SH_D
    UINT64_C(2768281600),	// LD1SH_D_IMM
    UINT64_C(2770354176),	// LD1SH_S
    UINT64_C(2770378752),	// LD1SH_S_IMM
    UINT64_C(2759868416),	// LD1SW_D
    UINT64_C(2759892992),	// LD1SW_D_IMM
    UINT64_C(1279287296),	// LD1Threev16b
    UINT64_C(1287675904),	// LD1Threev16b_POST
    UINT64_C(205548544),	// LD1Threev1d
    UINT64_C(213937152),	// LD1Threev1d_POST
    UINT64_C(1279290368),	// LD1Threev2d
    UINT64_C(1287678976),	// LD1Threev2d_POST
    UINT64_C(205547520),	// LD1Threev2s
    UINT64_C(213936128),	// LD1Threev2s_POST
    UINT64_C(205546496),	// LD1Threev4h
    UINT64_C(213935104),	// LD1Threev4h_POST
    UINT64_C(1279289344),	// LD1Threev4s
    UINT64_C(1287677952),	// LD1Threev4s_POST
    UINT64_C(205545472),	// LD1Threev8b
    UINT64_C(213934080),	// LD1Threev8b_POST
    UINT64_C(1279288320),	// LD1Threev8h
    UINT64_C(1287676928),	// LD1Threev8h_POST
    UINT64_C(1279303680),	// LD1Twov16b
    UINT64_C(1287692288),	// LD1Twov16b_POST
    UINT64_C(205564928),	// LD1Twov1d
    UINT64_C(213953536),	// LD1Twov1d_POST
    UINT64_C(1279306752),	// LD1Twov2d
    UINT64_C(1287695360),	// LD1Twov2d_POST
    UINT64_C(205563904),	// LD1Twov2s
    UINT64_C(213952512),	// LD1Twov2s_POST
    UINT64_C(205562880),	// LD1Twov4h
    UINT64_C(213951488),	// LD1Twov4h_POST
    UINT64_C(1279305728),	// LD1Twov4s
    UINT64_C(1287694336),	// LD1Twov4s_POST
    UINT64_C(205561856),	// LD1Twov8b
    UINT64_C(213950464),	// LD1Twov8b_POST
    UINT64_C(1279304704),	// LD1Twov8h
    UINT64_C(1287693312),	// LD1Twov8h_POST
    UINT64_C(2772451328),	// LD1W
    UINT64_C(2684370944),	// LD1W_2Z
    UINT64_C(2688565248),	// LD1W_2Z_IMM
    UINT64_C(2701148160),	// LD1W_2Z_STRIDED
    UINT64_C(2705342464),	// LD1W_2Z_STRIDED_IMM
    UINT64_C(2684403712),	// LD1W_4Z
    UINT64_C(2688598016),	// LD1W_4Z_IMM
    UINT64_C(2701180928),	// LD1W_4Z_STRIDED
    UINT64_C(2705375232),	// LD1W_4Z_STRIDED_IMM
    UINT64_C(2774548480),	// LD1W_D
    UINT64_C(2774573056),	// LD1W_D_IMM
    UINT64_C(2772475904),	// LD1W_IMM
    UINT64_C(2768273408),	// LD1W_Q
    UINT64_C(2769297408),	// LD1W_Q_IMM
    UINT64_C(3758096384),	// LD1_MXIPXX_H_B
    UINT64_C(3770679296),	// LD1_MXIPXX_H_D
    UINT64_C(3762290688),	// LD1_MXIPXX_H_H
    UINT64_C(3787456512),	// LD1_MXIPXX_H_Q
    UINT64_C(3766484992),	// LD1_MXIPXX_H_S
    UINT64_C(3758129152),	// LD1_MXIPXX_V_B
    UINT64_C(3770712064),	// LD1_MXIPXX_V_D
    UINT64_C(3762323456),	// LD1_MXIPXX_V_H
    UINT64_C(3787489280),	// LD1_MXIPXX_V_Q
    UINT64_C(3766517760),	// LD1_MXIPXX_V_S
    UINT64_C(222314496),	// LD1i16
    UINT64_C(230703104),	// LD1i16_POST
    UINT64_C(222330880),	// LD1i32
    UINT64_C(230719488),	// LD1i32_POST
    UINT64_C(222331904),	// LD1i64
    UINT64_C(230720512),	// LD1i64_POST
    UINT64_C(222298112),	// LD1i8
    UINT64_C(230686720),	// LD1i8_POST
    UINT64_C(2753609728),	// LD2B
    UINT64_C(2753617920),	// LD2B_IMM
    UINT64_C(2778775552),	// LD2D
    UINT64_C(2778783744),	// LD2D_IMM
    UINT64_C(2761998336),	// LD2H
    UINT64_C(2762006528),	// LD2H_IMM
    UINT64_C(2761981952),	// LD2Q
    UINT64_C(2760957952),	// LD2Q_IMM
    UINT64_C(1298186240),	// LD2Rv16b
    UINT64_C(1306574848),	// LD2Rv16b_POST
    UINT64_C(224447488),	// LD2Rv1d
    UINT64_C(232836096),	// LD2Rv1d_POST
    UINT64_C(1298189312),	// LD2Rv2d
    UINT64_C(1306577920),	// LD2Rv2d_POST
    UINT64_C(224446464),	// LD2Rv2s
    UINT64_C(232835072),	// LD2Rv2s_POST
    UINT64_C(224445440),	// LD2Rv4h
    UINT64_C(232834048),	// LD2Rv4h_POST
    UINT64_C(1298188288),	// LD2Rv4s
    UINT64_C(1306576896),	// LD2Rv4s_POST
    UINT64_C(224444416),	// LD2Rv8b
    UINT64_C(232833024),	// LD2Rv8b_POST
    UINT64_C(1298187264),	// LD2Rv8h
    UINT64_C(1306575872),	// LD2Rv8h_POST
    UINT64_C(1279295488),	// LD2Twov16b
    UINT64_C(1287684096),	// LD2Twov16b_POST
    UINT64_C(1279298560),	// LD2Twov2d
    UINT64_C(1287687168),	// LD2Twov2d_POST
    UINT64_C(205555712),	// LD2Twov2s
    UINT64_C(213944320),	// LD2Twov2s_POST
    UINT64_C(205554688),	// LD2Twov4h
    UINT64_C(213943296),	// LD2Twov4h_POST
    UINT64_C(1279297536),	// LD2Twov4s
    UINT64_C(1287686144),	// LD2Twov4s_POST
    UINT64_C(205553664),	// LD2Twov8b
    UINT64_C(213942272),	// LD2Twov8b_POST
    UINT64_C(1279296512),	// LD2Twov8h
    UINT64_C(1287685120),	// LD2Twov8h_POST
    UINT64_C(2770386944),	// LD2W
    UINT64_C(2770395136),	// LD2W_IMM
    UINT64_C(224411648),	// LD2i16
    UINT64_C(232800256),	// LD2i16_POST
    UINT64_C(224428032),	// LD2i32
    UINT64_C(232816640),	// LD2i32_POST
    UINT64_C(224429056),	// LD2i64
    UINT64_C(232817664),	// LD2i64_POST
    UINT64_C(224395264),	// LD2i8
    UINT64_C(232783872),	// LD2i8_POST
    UINT64_C(2755706880),	// LD3B
    UINT64_C(2755715072),	// LD3B_IMM
    UINT64_C(2780872704),	// LD3D
    UINT64_C(2780880896),	// LD3D_IMM
    UINT64_C(2764095488),	// LD3H
    UINT64_C(2764103680),	// LD3H_IMM
    UINT64_C(2770370560),	// LD3Q
    UINT64_C(2769346560),	// LD3Q_IMM
    UINT64_C(1296097280),	// LD3Rv16b
    UINT64_C(1304485888),	// LD3Rv16b_POST
    UINT64_C(222358528),	// LD3Rv1d
    UINT64_C(230747136),	// LD3Rv1d_POST
    UINT64_C(1296100352),	// LD3Rv2d
    UINT64_C(1304488960),	// LD3Rv2d_POST
    UINT64_C(222357504),	// LD3Rv2s
    UINT64_C(230746112),	// LD3Rv2s_POST
    UINT64_C(222356480),	// LD3Rv4h
    UINT64_C(230745088),	// LD3Rv4h_POST
    UINT64_C(1296099328),	// LD3Rv4s
    UINT64_C(1304487936),	// LD3Rv4s_POST
    UINT64_C(222355456),	// LD3Rv8b
    UINT64_C(230744064),	// LD3Rv8b_POST
    UINT64_C(1296098304),	// LD3Rv8h
    UINT64_C(1304486912),	// LD3Rv8h_POST
    UINT64_C(1279279104),	// LD3Threev16b
    UINT64_C(1287667712),	// LD3Threev16b_POST
    UINT64_C(1279282176),	// LD3Threev2d
    UINT64_C(1287670784),	// LD3Threev2d_POST
    UINT64_C(205539328),	// LD3Threev2s
    UINT64_C(213927936),	// LD3Threev2s_POST
    UINT64_C(205538304),	// LD3Threev4h
    UINT64_C(213926912),	// LD3Threev4h_POST
    UINT64_C(1279281152),	// LD3Threev4s
    UINT64_C(1287669760),	// LD3Threev4s_POST
    UINT64_C(205537280),	// LD3Threev8b
    UINT64_C(213925888),	// LD3Threev8b_POST
    UINT64_C(1279280128),	// LD3Threev8h
    UINT64_C(1287668736),	// LD3Threev8h_POST
    UINT64_C(2772484096),	// LD3W
    UINT64_C(2772492288),	// LD3W_IMM
    UINT64_C(222322688),	// LD3i16
    UINT64_C(230711296),	// LD3i16_POST
    UINT64_C(222339072),	// LD3i32
    UINT64_C(230727680),	// LD3i32_POST
    UINT64_C(222340096),	// LD3i64
    UINT64_C(230728704),	// LD3i64_POST
    UINT64_C(222306304),	// LD3i8
    UINT64_C(230694912),	// LD3i8_POST
    UINT64_C(2757804032),	// LD4B
    UINT64_C(2757812224),	// LD4B_IMM
    UINT64_C(2782969856),	// LD4D
    UINT64_C(2782978048),	// LD4D_IMM
    UINT64_C(1279262720),	// LD4Fourv16b
    UINT64_C(1287651328),	// LD4Fourv16b_POST
    UINT64_C(1279265792),	// LD4Fourv2d
    UINT64_C(1287654400),	// LD4Fourv2d_POST
    UINT64_C(205522944),	// LD4Fourv2s
    UINT64_C(213911552),	// LD4Fourv2s_POST
    UINT64_C(205521920),	// LD4Fourv4h
    UINT64_C(213910528),	// LD4Fourv4h_POST
    UINT64_C(1279264768),	// LD4Fourv4s
    UINT64_C(1287653376),	// LD4Fourv4s_POST
    UINT64_C(205520896),	// LD4Fourv8b
    UINT64_C(213909504),	// LD4Fourv8b_POST
    UINT64_C(1279263744),	// LD4Fourv8h
    UINT64_C(1287652352),	// LD4Fourv8h_POST
    UINT64_C(2766192640),	// LD4H
    UINT64_C(2766200832),	// LD4H_IMM
    UINT64_C(2778759168),	// LD4Q
    UINT64_C(2777735168),	// LD4Q_IMM
    UINT64_C(1298194432),	// LD4Rv16b
    UINT64_C(1306583040),	// LD4Rv16b_POST
    UINT64_C(224455680),	// LD4Rv1d
    UINT64_C(232844288),	// LD4Rv1d_POST
    UINT64_C(1298197504),	// LD4Rv2d
    UINT64_C(1306586112),	// LD4Rv2d_POST
    UINT64_C(224454656),	// LD4Rv2s
    UINT64_C(232843264),	// LD4Rv2s_POST
    UINT64_C(224453632),	// LD4Rv4h
    UINT64_C(232842240),	// LD4Rv4h_POST
    UINT64_C(1298196480),	// LD4Rv4s
    UINT64_C(1306585088),	// LD4Rv4s_POST
    UINT64_C(224452608),	// LD4Rv8b
    UINT64_C(232841216),	// LD4Rv8b_POST
    UINT64_C(1298195456),	// LD4Rv8h
    UINT64_C(1306584064),	// LD4Rv8h_POST
    UINT64_C(2774581248),	// LD4W
    UINT64_C(2774589440),	// LD4W_IMM
    UINT64_C(224419840),	// LD4i16
    UINT64_C(232808448),	// LD4i16_POST
    UINT64_C(224436224),	// LD4i32
    UINT64_C(232824832),	// LD4i32_POST
    UINT64_C(224437248),	// LD4i64
    UINT64_C(232825856),	// LD4i64_POST
    UINT64_C(224403456),	// LD4i8
    UINT64_C(232792064),	// LD4i8_POST
    UINT64_C(4164931584),	// LD64B
    UINT64_C(950009856),	// LDADDAB
    UINT64_C(2023751680),	// LDADDAH
    UINT64_C(954204160),	// LDADDALB
    UINT64_C(2027945984),	// LDADDALH
    UINT64_C(3101687808),	// LDADDALW
    UINT64_C(4175429632),	// LDADDALX
    UINT64_C(3097493504),	// LDADDAW
    UINT64_C(4171235328),	// LDADDAX
    UINT64_C(941621248),	// LDADDB
    UINT64_C(2015363072),	// LDADDH
    UINT64_C(945815552),	// LDADDLB
    UINT64_C(2019557376),	// LDADDLH
    UINT64_C(3093299200),	// LDADDLW
    UINT64_C(4167041024),	// LDADDLX
    UINT64_C(3089104896),	// LDADDW
    UINT64_C(4162846720),	// LDADDX
    UINT64_C(222397440),	// LDAP1
    UINT64_C(3644880896),	// LDAPPi
    UINT64_C(952090624),	// LDAPRB
    UINT64_C(2025832448),	// LDAPRH
    UINT64_C(3099574272),	// LDAPRW
    UINT64_C(2579499008),	// LDAPRWpost
    UINT64_C(4173316096),	// LDAPRX
    UINT64_C(3653240832),	// LDAPRXpost
    UINT64_C(423624704),	// LDAPURBi
    UINT64_C(1497366528),	// LDAPURHi
    UINT64_C(432013312),	// LDAPURSBWi
    UINT64_C(427819008),	// LDAPURSBXi
    UINT64_C(1505755136),	// LDAPURSHWi
    UINT64_C(1501560832),	// LDAPURSHXi
    UINT64_C(2575302656),	// LDAPURSWi
    UINT64_C(3644850176),	// LDAPURXi
    UINT64_C(490735616),	// LDAPURbi
    UINT64_C(3711961088),	// LDAPURdi
    UINT64_C(1564477440),	// LDAPURhi
    UINT64_C(2571108352),	// LDAPURi
    UINT64_C(499124224),	// LDAPURqi
    UINT64_C(2638219264),	// LDAPURsi
    UINT64_C(3644872704),	// LDAPi
    UINT64_C(148896768),	// LDARB
    UINT64_C(1222638592),	// LDARH
    UINT64_C(2296380416),	// LDARW
    UINT64_C(3370122240),	// LDARX
    UINT64_C(2304769024),	// LDATXRW
    UINT64_C(3378510848),	// LDATXRX
    UINT64_C(2290057216),	// LDAXPW
    UINT64_C(3363799040),	// LDAXPX
    UINT64_C(140508160),	// LDAXRB
    UINT64_C(1214249984),	// LDAXRH
    UINT64_C(2287991808),	// LDAXRW
    UINT64_C(3361733632),	// LDAXRX
    UINT64_C(1008730112),	// LDBFADD
    UINT64_C(1017118720),	// LDBFADDA
    UINT64_C(1021313024),	// LDBFADDAL
    UINT64_C(1012924416),	// LDBFADDL
    UINT64_C(1008746496),	// LDBFMAX
    UINT64_C(1017135104),	// LDBFMAXA
    UINT64_C(1021329408),	// LDBFMAXAL
    UINT64_C(1012940800),	// LDBFMAXL
    UINT64_C(1008754688),	// LDBFMAXNM
    UINT64_C(1017143296),	// LDBFMAXNMA
    UINT64_C(1021337600),	// LDBFMAXNMAL
    UINT64_C(1012948992),	// LDBFMAXNML
    UINT64_C(1008750592),	// LDBFMIN
    UINT64_C(1017139200),	// LDBFMINA
    UINT64_C(1021333504),	// LDBFMINAL
    UINT64_C(1012944896),	// LDBFMINL
    UINT64_C(1008758784),	// LDBFMINNM
    UINT64_C(1017147392),	// LDBFMINNMA
    UINT64_C(1021341696),	// LDBFMINNMAL
    UINT64_C(1012953088),	// LDBFMINNML
    UINT64_C(950013952),	// LDCLRAB
    UINT64_C(2023755776),	// LDCLRAH
    UINT64_C(954208256),	// LDCLRALB
    UINT64_C(2027950080),	// LDCLRALH
    UINT64_C(3101691904),	// LDCLRALW
    UINT64_C(4175433728),	// LDCLRALX
    UINT64_C(3097497600),	// LDCLRAW
    UINT64_C(4171239424),	// LDCLRAX
    UINT64_C(941625344),	// LDCLRB
    UINT64_C(2015367168),	// LDCLRH
    UINT64_C(945819648),	// LDCLRLB
    UINT64_C(2019561472),	// LDCLRLH
    UINT64_C(3093303296),	// LDCLRLW
    UINT64_C(4167045120),	// LDCLRLX
    UINT64_C(421531648),	// LDCLRP
    UINT64_C(429920256),	// LDCLRPA
    UINT64_C(434114560),	// LDCLRPAL
    UINT64_C(425725952),	// LDCLRPL
    UINT64_C(3089108992),	// LDCLRW
    UINT64_C(4162850816),	// LDCLRX
    UINT64_C(950018048),	// LDEORAB
    UINT64_C(2023759872),	// LDEORAH
    UINT64_C(954212352),	// LDEORALB
    UINT64_C(2027954176),	// LDEORALH
    UINT64_C(3101696000),	// LDEORALW
    UINT64_C(4175437824),	// LDEORALX
    UINT64_C(3097501696),	// LDEORAW
    UINT64_C(4171243520),	// LDEORAX
    UINT64_C(941629440),	// LDEORB
    UINT64_C(2015371264),	// LDEORH
    UINT64_C(945823744),	// LDEORLB
    UINT64_C(2019565568),	// LDEORLH
    UINT64_C(3093307392),	// LDEORLW
    UINT64_C(4167049216),	// LDEORLX
    UINT64_C(3089113088),	// LDEORW
    UINT64_C(4162854912),	// LDEORX
    UINT64_C(4238344192),	// LDFADDAD
    UINT64_C(2090860544),	// LDFADDAH
    UINT64_C(4242538496),	// LDFADDALD
    UINT64_C(2095054848),	// LDFADDALH
    UINT64_C(3168796672),	// LDFADDALS
    UINT64_C(3164602368),	// LDFADDAS
    UINT64_C(4229955584),	// LDFADDD
    UINT64_C(2082471936),	// LDFADDH
    UINT64_C(4234149888),	// LDFADDLD
    UINT64_C(2086666240),	// LDFADDLH
    UINT64_C(3160408064),	// LDFADDLS
    UINT64_C(3156213760),	// LDFADDS
    UINT64_C(2751488000),	// LDFF1B
    UINT64_C(2757779456),	// LDFF1B_D
    UINT64_C(2753585152),	// LDFF1B_H
    UINT64_C(2755682304),	// LDFF1B_S
    UINT64_C(2782945280),	// LDFF1D
    UINT64_C(2761973760),	// LDFF1H
    UINT64_C(2766168064),	// LDFF1H_D
    UINT64_C(2764070912),	// LDFF1H_S
    UINT64_C(2776653824),	// LDFF1SB_D
    UINT64_C(2780848128),	// LDFF1SB_H
    UINT64_C(2778750976),	// LDFF1SB_S
    UINT64_C(2768265216),	// LDFF1SH_D
    UINT64_C(2770362368),	// LDFF1SH_S
    UINT64_C(2759876608),	// LDFF1SW_D
    UINT64_C(2772459520),	// LDFF1W
    UINT64_C(2774556672),	// LDFF1W_D
    UINT64_C(4238360576),	// LDFMAXAD
    UINT64_C(2090876928),	// LDFMAXAH
    UINT64_C(4242554880),	// LDFMAXALD
    UINT64_C(2095071232),	// LDFMAXALH
    UINT64_C(3168813056),	// LDFMAXALS
    UINT64_C(3164618752),	// LDFMAXAS
    UINT64_C(4229971968),	// LDFMAXD
    UINT64_C(2082488320),	// LDFMAXH
    UINT64_C(4234166272),	// LDFMAXLD
    UINT64_C(2086682624),	// LDFMAXLH
    UINT64_C(3160424448),	// LDFMAXLS
    UINT64_C(4238368768),	// LDFMAXNMAD
    UINT64_C(2090885120),	// LDFMAXNMAH
    UINT64_C(4242563072),	// LDFMAXNMALD
    UINT64_C(2095079424),	// LDFMAXNMALH
    UINT64_C(3168821248),	// LDFMAXNMALS
    UINT64_C(3164626944),	// LDFMAXNMAS
    UINT64_C(4229980160),	// LDFMAXNMD
    UINT64_C(2082496512),	// LDFMAXNMH
    UINT64_C(4234174464),	// LDFMAXNMLD
    UINT64_C(2086690816),	// LDFMAXNMLH
    UINT64_C(3160432640),	// LDFMAXNMLS
    UINT64_C(3156238336),	// LDFMAXNMS
    UINT64_C(3156230144),	// LDFMAXS
    UINT64_C(4238364672),	// LDFMINAD
    UINT64_C(2090881024),	// LDFMINAH
    UINT64_C(4242558976),	// LDFMINALD
    UINT64_C(2095075328),	// LDFMINALH
    UINT64_C(3168817152),	// LDFMINALS
    UINT64_C(3164622848),	// LDFMINAS
    UINT64_C(4229976064),	// LDFMIND
    UINT64_C(2082492416),	// LDFMINH
    UINT64_C(4234170368),	// LDFMINLD
    UINT64_C(2086686720),	// LDFMINLH
    UINT64_C(3160428544),	// LDFMINLS
    UINT64_C(4238372864),	// LDFMINNMAD
    UINT64_C(2090889216),	// LDFMINNMAH
    UINT64_C(4242567168),	// LDFMINNMALD
    UINT64_C(2095083520),	// LDFMINNMALH
    UINT64_C(3168825344),	// LDFMINNMALS
    UINT64_C(3164631040),	// LDFMINNMAS
    UINT64_C(4229984256),	// LDFMINNMD
    UINT64_C(2082500608),	// LDFMINNMH
    UINT64_C(4234178560),	// LDFMINNMLD
    UINT64_C(2086694912),	// LDFMINNMLH
    UINT64_C(3160436736),	// LDFMINNMLS
    UINT64_C(3156242432),	// LDFMINNMS
    UINT64_C(3156234240),	// LDFMINS
    UINT64_C(3646947328),	// LDG
    UINT64_C(3655335936),	// LDGM
    UINT64_C(2571114496),	// LDIAPPW
    UINT64_C(2571110400),	// LDIAPPWpost
    UINT64_C(3644856320),	// LDIAPPX
    UINT64_C(3644852224),	// LDIAPPXpost
    UINT64_C(148864000),	// LDLARB
    UINT64_C(1222605824),	// LDLARH
    UINT64_C(2296347648),	// LDLARW
    UINT64_C(3370089472),	// LDLARX
    UINT64_C(2758844416),	// LDNF1B_D_IMM
    UINT64_C(2754650112),	// LDNF1B_H_IMM
    UINT64_C(2752552960),	// LDNF1B_IMM
    UINT64_C(2756747264),	// LDNF1B_S_IMM
    UINT64_C(2784010240),	// LDNF1D_IMM
    UINT64_C(2767233024),	// LDNF1H_D_IMM
    UINT64_C(2763038720),	// LDNF1H_IMM
    UINT64_C(2765135872),	// LDNF1H_S_IMM
    UINT64_C(2777718784),	// LDNF1SB_D_IMM
    UINT64_C(2781913088),	// LDNF1SB_H_IMM
    UINT64_C(2779815936),	// LDNF1SB_S_IMM
    UINT64_C(2769330176),	// LDNF1SH_D_IMM
    UINT64_C(2771427328),	// LDNF1SH_S_IMM
    UINT64_C(2760941568),	// LDNF1SW_D_IMM
    UINT64_C(2775621632),	// LDNF1W_D_IMM
    UINT64_C(2773524480),	// LDNF1W_IMM
    UINT64_C(1816133632),	// LDNPDi
    UINT64_C(2889875456),	// LDNPQi
    UINT64_C(742391808),	// LDNPSi
    UINT64_C(675282944),	// LDNPWi
    UINT64_C(2822766592),	// LDNPXi
    UINT64_C(2684354561),	// LDNT1B_2Z
    UINT64_C(2688548865),	// LDNT1B_2Z_IMM
    UINT64_C(2701131784),	// LDNT1B_2Z_STRIDED
    UINT64_C(2705326088),	// LDNT1B_2Z_STRIDED_IMM
    UINT64_C(2684387329),	// LDNT1B_4Z
    UINT64_C(2688581633),	// LDNT1B_4Z_IMM
    UINT64_C(2701164552),	// LDNT1B_4Z_STRIDED
    UINT64_C(2705358856),	// LDNT1B_4Z_STRIDED_IMM
    UINT64_C(2751520768),	// LDNT1B_ZRI
    UINT64_C(2751512576),	// LDNT1B_ZRR
    UINT64_C(3288383488),	// LDNT1B_ZZR_D
    UINT64_C(2214633472),	// LDNT1B_ZZR_S
    UINT64_C(2684379137),	// LDNT1D_2Z
    UINT64_C(2688573441),	// LDNT1D_2Z_IMM
    UINT64_C(2701156360),	// LDNT1D_2Z_STRIDED
    UINT64_C(2705350664),	// LDNT1D_2Z_STRIDED_IMM
    UINT64_C(2684411905),	// LDNT1D_4Z
    UINT64_C(2688606209),	// LDNT1D_4Z_IMM
    UINT64_C(2701189128),	// LDNT1D_4Z_STRIDED
    UINT64_C(2705383432),	// LDNT1D_4Z_STRIDED_IMM
    UINT64_C(2776686592),	// LDNT1D_ZRI
    UINT64_C(2776678400),	// LDNT1D_ZRR
    UINT64_C(3313549312),	// LDNT1D_ZZR_D
    UINT64_C(2684362753),	// LDNT1H_2Z
    UINT64_C(2688557057),	// LDNT1H_2Z_IMM
    UINT64_C(2701139976),	// LDNT1H_2Z_STRIDED
    UINT64_C(2705334280),	// LDNT1H_2Z_STRIDED_IMM
    UINT64_C(2684395521),	// LDNT1H_4Z
    UINT64_C(2688589825),	// LDNT1H_4Z_IMM
    UINT64_C(2701172744),	// LDNT1H_4Z_STRIDED
    UINT64_C(2705367048),	// LDNT1H_4Z_STRIDED_IMM
    UINT64_C(2759909376),	// LDNT1H_ZRI
    UINT64_C(2759901184),	// LDNT1H_ZRR
    UINT64_C(3296772096),	// LDNT1H_ZZR_D
    UINT64_C(2223022080),	// LDNT1H_ZZR_S
    UINT64_C(3288367104),	// LDNT1SB_ZZR_D
    UINT64_C(2214625280),	// LDNT1SB_ZZR_S
    UINT64_C(3296755712),	// LDNT1SH_ZZR_D
    UINT64_C(2223013888),	// LDNT1SH_ZZR_S
    UINT64_C(3305144320),	// LDNT1SW_ZZR_D
    UINT64_C(2684370945),	// LDNT1W_2Z
    UINT64_C(2688565249),	// LDNT1W_2Z_IMM
    UINT64_C(2701148168),	// LDNT1W_2Z_STRIDED
    UINT64_C(2705342472),	// LDNT1W_2Z_STRIDED_IMM
    UINT64_C(2684403713),	// LDNT1W_4Z
    UINT64_C(2688598017),	// LDNT1W_4Z_IMM
    UINT64_C(2701180936),	// LDNT1W_4Z_STRIDED
    UINT64_C(2705375240),	// LDNT1W_4Z_STRIDED_IMM
    UINT64_C(2768297984),	// LDNT1W_ZRI
    UINT64_C(2768289792),	// LDNT1W_ZRR
    UINT64_C(3305160704),	// LDNT1W_ZZR_D
    UINT64_C(2231410688),	// LDNT1W_ZZR_S
    UINT64_C(1832910848),	// LDPDi
    UINT64_C(1824522240),	// LDPDpost
    UINT64_C(1841299456),	// LDPDpre
    UINT64_C(2906652672),	// LDPQi
    UINT64_C(2898264064),	// LDPQpost
    UINT64_C(2915041280),	// LDPQpre
    UINT64_C(1765801984),	// LDPSWi
    UINT64_C(1757413376),	// LDPSWpost
    UINT64_C(1774190592),	// LDPSWpre
    UINT64_C(759169024),	// LDPSi
    UINT64_C(750780416),	// LDPSpost
    UINT64_C(767557632),	// LDPSpre
    UINT64_C(692060160),	// LDPWi
    UINT64_C(683671552),	// LDPWpost
    UINT64_C(700448768),	// LDPWpre
    UINT64_C(2839543808),	// LDPXi
    UINT64_C(2831155200),	// LDPXpost
    UINT64_C(2847932416),	// LDPXpre
    UINT64_C(4162847744),	// LDRAAindexed
    UINT64_C(4162849792),	// LDRAAwriteback
    UINT64_C(4171236352),	// LDRABindexed
    UINT64_C(4171238400),	// LDRABwriteback
    UINT64_C(943719424),	// LDRBBpost
    UINT64_C(943721472),	// LDRBBpre
    UINT64_C(945833984),	// LDRBBroW
    UINT64_C(945842176),	// LDRBBroX
    UINT64_C(960495616),	// LDRBBui
    UINT64_C(1010828288),	// LDRBpost
    UINT64_C(1010830336),	// LDRBpre
    UINT64_C(1012942848),	// LDRBroW
    UINT64_C(1012951040),	// LDRBroX
    UINT64_C(1027604480),	// LDRBui
    UINT64_C(1543503872),	// LDRDl
    UINT64_C(4232053760),	// LDRDpost
    UINT64_C(4232055808),	// LDRDpre
    UINT64_C(4234168320),	// LDRDroW
    UINT64_C(4234176512),	// LDRDroX
    UINT64_C(4248829952),	// LDRDui
    UINT64_C(2017461248),	// LDRHHpost
    UINT64_C(2017463296),	// LDRHHpre
    UINT64_C(2019575808),	// LDRHHroW
    UINT64_C(2019584000),	// LDRHHroX
    UINT64_C(2034237440),	// LDRHHui
    UINT64_C(2084570112),	// LDRHpost
    UINT64_C(2084572160),	// LDRHpre
    UINT64_C(2086684672),	// LDRHroW
    UINT64_C(2086692864),	// LDRHroX
    UINT64_C(2101346304),	// LDRHui
    UINT64_C(2617245696),	// LDRQl
    UINT64_C(1019216896),	// LDRQpost
    UINT64_C(1019218944),	// LDRQpre
    UINT64_C(1021331456),	// LDRQroW
    UINT64_C(1021339648),	// LDRQroX
    UINT64_C(1035993088),	// LDRQui
    UINT64_C(952108032),	// LDRSBWpost
    UINT64_C(952110080),	// LDRSBWpre
    UINT64_C(954222592),	// LDRSBWroW
    UINT64_C(954230784),	// LDRSBWroX
    UINT64_C(968884224),	// LDRSBWui
    UINT64_C(947913728),	// LDRSBXpost
    UINT64_C(947915776),	// LDRSBXpre
    UINT64_C(950028288),	// LDRSBXroW
    UINT64_C(950036480),	// LDRSBXroX
    UINT64_C(964689920),	// LDRSBXui
    UINT64_C(2025849856),	// LDRSHWpost
    UINT64_C(2025851904),	// LDRSHWpre
    UINT64_C(2027964416),	// LDRSHWroW
    UINT64_C(2027972608),	// LDRSHWroX
    UINT64_C(2042626048),	// LDRSHWui
    UINT64_C(2021655552),	// LDRSHXpost
    UINT64_C(2021657600),	// LDRSHXpre
    UINT64_C(2023770112),	// LDRSHXroW
    UINT64_C(2023778304),	// LDRSHXroX
    UINT64_C(2038431744),	// LDRSHXui
    UINT64_C(2550136832),	// LDRSWl
    UINT64_C(3095397376),	// LDRSWpost
    UINT64_C(3095399424),	// LDRSWpre
    UINT64_C(3097511936),	// LDRSWroW
    UINT64_C(3097520128),	// LDRSWroX
    UINT64_C(3112173568),	// LDRSWui
    UINT64_C(469762048),	// LDRSl
    UINT64_C(3158311936),	// LDRSpost
    UINT64_C(3158313984),	// LDRSpre
    UINT64_C(3160426496),	// LDRSroW
    UINT64_C(3160434688),	// LDRSroX
    UINT64_C(3175088128),	// LDRSui
    UINT64_C(402653184),	// LDRWl
    UINT64_C(3091203072),	// LDRWpost
    UINT64_C(3091205120),	// LDRWpre
    UINT64_C(3093317632),	// LDRWroW
    UINT64_C(3093325824),	// LDRWroX
    UINT64_C(3107979264),	// LDRWui
    UINT64_C(1476395008),	// LDRXl
    UINT64_C(4164944896),	// LDRXpost
    UINT64_C(4164946944),	// LDRXpre
    UINT64_C(4167059456),	// LDRXroW
    UINT64_C(4167067648),	// LDRXroX
    UINT64_C(4181721088),	// LDRXui
    UINT64_C(2239758336),	// LDR_PXI
    UINT64_C(3776937984),	// LDR_TX
    UINT64_C(3774873600),	// LDR_ZA
    UINT64_C(2239774720),	// LDR_ZXI
    UINT64_C(950022144),	// LDSETAB
    UINT64_C(2023763968),	// LDSETAH
    UINT64_C(954216448),	// LDSETALB
    UINT64_C(2027958272),	// LDSETALH
    UINT64_C(3101700096),	// LDSETALW
    UINT64_C(4175441920),	// LDSETALX
    UINT64_C(3097505792),	// LDSETAW
    UINT64_C(4171247616),	// LDSETAX
    UINT64_C(941633536),	// LDSETB
    UINT64_C(2015375360),	// LDSETH
    UINT64_C(945827840),	// LDSETLB
    UINT64_C(2019569664),	// LDSETLH
    UINT64_C(3093311488),	// LDSETLW
    UINT64_C(4167053312),	// LDSETLX
    UINT64_C(421539840),	// LDSETP
    UINT64_C(429928448),	// LDSETPA
    UINT64_C(434122752),	// LDSETPAL
    UINT64_C(425734144),	// LDSETPL
    UINT64_C(3089117184),	// LDSETW
    UINT64_C(4162859008),	// LDSETX
    UINT64_C(950026240),	// LDSMAXAB
    UINT64_C(2023768064),	// LDSMAXAH
    UINT64_C(954220544),	// LDSMAXALB
    UINT64_C(2027962368),	// LDSMAXALH
    UINT64_C(3101704192),	// LDSMAXALW
    UINT64_C(4175446016),	// LDSMAXALX
    UINT64_C(3097509888),	// LDSMAXAW
    UINT64_C(4171251712),	// LDSMAXAX
    UINT64_C(941637632),	// LDSMAXB
    UINT64_C(2015379456),	// LDSMAXH
    UINT64_C(945831936),	// LDSMAXLB
    UINT64_C(2019573760),	// LDSMAXLH
    UINT64_C(3093315584),	// LDSMAXLW
    UINT64_C(4167057408),	// LDSMAXLX
    UINT64_C(3089121280),	// LDSMAXW
    UINT64_C(4162863104),	// LDSMAXX
    UINT64_C(950030336),	// LDSMINAB
    UINT64_C(2023772160),	// LDSMINAH
    UINT64_C(954224640),	// LDSMINALB
    UINT64_C(2027966464),	// LDSMINALH
    UINT64_C(3101708288),	// LDSMINALW
    UINT64_C(4175450112),	// LDSMINALX
    UINT64_C(3097513984),	// LDSMINAW
    UINT64_C(4171255808),	// LDSMINAX
    UINT64_C(941641728),	// LDSMINB
    UINT64_C(2015383552),	// LDSMINH
    UINT64_C(945836032),	// LDSMINLB
    UINT64_C(2019577856),	// LDSMINLH
    UINT64_C(3093319680),	// LDSMINLW
    UINT64_C(4167061504),	// LDSMINLX
    UINT64_C(3089125376),	// LDSMINW
    UINT64_C(4162867200),	// LDSMINX
    UINT64_C(434111488),	// LDTADDALW
    UINT64_C(1507853312),	// LDTADDALX
    UINT64_C(429917184),	// LDTADDAW
    UINT64_C(1503659008),	// LDTADDAX
    UINT64_C(425722880),	// LDTADDLW
    UINT64_C(1499464704),	// LDTADDLX
    UINT64_C(421528576),	// LDTADDW
    UINT64_C(1495270400),	// LDTADDX
    UINT64_C(434115584),	// LDTCLRALW
    UINT64_C(1507857408),	// LDTCLRALX
    UINT64_C(429921280),	// LDTCLRAW
    UINT64_C(1503663104),	// LDTCLRAX
    UINT64_C(425726976),	// LDTCLRLW
    UINT64_C(1499468800),	// LDTCLRLX
    UINT64_C(421532672),	// LDTCLRW
    UINT64_C(1495274496),	// LDTCLRX
    UINT64_C(3963617280),	// LDTNPQi
    UINT64_C(3896508416),	// LDTNPXi
    UINT64_C(3980394496),	// LDTPQi
    UINT64_C(3972005888),	// LDTPQpost
    UINT64_C(3988783104),	// LDTPQpre
    UINT64_C(3913285632),	// LDTPi
    UINT64_C(3904897024),	// LDTPpost
    UINT64_C(3921674240),	// LDTPpre
    UINT64_C(943720448),	// LDTRBi
    UINT64_C(2017462272),	// LDTRHi
    UINT64_C(952109056),	// LDTRSBWi
    UINT64_C(947914752),	// LDTRSBXi
    UINT64_C(2025850880),	// LDTRSHWi
    UINT64_C(2021656576),	// LDTRSHXi
    UINT64_C(3095398400),	// LDTRSWi
    UINT64_C(3091204096),	// LDTRWi
    UINT64_C(4164945920),	// LDTRXi
    UINT64_C(434123776),	// LDTSETALW
    UINT64_C(1507865600),	// LDTSETALX
    UINT64_C(429929472),	// LDTSETAW
    UINT64_C(1503671296),	// LDTSETAX
    UINT64_C(425735168),	// LDTSETLW
    UINT64_C(1499476992),	// LDTSETLX
    UINT64_C(421540864),	// LDTSETW
    UINT64_C(1495282688),	// LDTSETX
    UINT64_C(2304736256),	// LDTXRWr
    UINT64_C(3378478080),	// LDTXRXr
    UINT64_C(950034432),	// LDUMAXAB
    UINT64_C(2023776256),	// LDUMAXAH
    UINT64_C(954228736),	// LDUMAXALB
    UINT64_C(2027970560),	// LDUMAXALH
    UINT64_C(3101712384),	// LDUMAXALW
    UINT64_C(4175454208),	// LDUMAXALX
    UINT64_C(3097518080),	// LDUMAXAW
    UINT64_C(4171259904),	// LDUMAXAX
    UINT64_C(941645824),	// LDUMAXB
    UINT64_C(2015387648),	// LDUMAXH
    UINT64_C(945840128),	// LDUMAXLB
    UINT64_C(2019581952),	// LDUMAXLH
    UINT64_C(3093323776),	// LDUMAXLW
    UINT64_C(4167065600),	// LDUMAXLX
    UINT64_C(3089129472),	// LDUMAXW
    UINT64_C(4162871296),	// LDUMAXX
    UINT64_C(950038528),	// LDUMINAB
    UINT64_C(2023780352),	// LDUMINAH
    UINT64_C(954232832),	// LDUMINALB
    UINT64_C(2027974656),	// LDUMINALH
    UINT64_C(3101716480),	// LDUMINALW
    UINT64_C(4175458304),	// LDUMINALX
    UINT64_C(3097522176),	// LDUMINAW
    UINT64_C(4171264000),	// LDUMINAX
    UINT64_C(941649920),	// LDUMINB
    UINT64_C(2015391744),	// LDUMINH
    UINT64_C(945844224),	// LDUMINLB
    UINT64_C(2019586048),	// LDUMINLH
    UINT64_C(3093327872),	// LDUMINLW
    UINT64_C(4167069696),	// LDUMINLX
    UINT64_C(3089133568),	// LDUMINW
    UINT64_C(4162875392),	// LDUMINX
    UINT64_C(943718400),	// LDURBBi
    UINT64_C(1010827264),	// LDURBi
    UINT64_C(4232052736),	// LDURDi
    UINT64_C(2017460224),	// LDURHHi
    UINT64_C(2084569088),	// LDURHi
    UINT64_C(1019215872),	// LDURQi
    UINT64_C(952107008),	// LDURSBWi
    UINT64_C(947912704),	// LDURSBXi
    UINT64_C(2025848832),	// LDURSHWi
    UINT64_C(2021654528),	// LDURSHXi
    UINT64_C(3095396352),	// LDURSWi
    UINT64_C(3158310912),	// LDURSi
    UINT64_C(3091202048),	// LDURWi
    UINT64_C(4164943872),	// LDURXi
    UINT64_C(2290024448),	// LDXPW
    UINT64_C(3363766272),	// LDXPX
    UINT64_C(140475392),	// LDXRB
    UINT64_C(1214217216),	// LDXRH
    UINT64_C(2287959040),	// LDXRW
    UINT64_C(3361700864),	// LDXRX
    UINT64_C(68648960),	// LSLR_ZPmZ_B
    UINT64_C(81231872),	// LSLR_ZPmZ_D
    UINT64_C(72843264),	// LSLR_ZPmZ_H
    UINT64_C(77037568),	// LSLR_ZPmZ_S
    UINT64_C(448798720),	// LSLVWr
    UINT64_C(2596282368),	// LSLVXr
    UINT64_C(68911104),	// LSL_WIDE_ZPmZ_B
    UINT64_C(73105408),	// LSL_WIDE_ZPmZ_H
    UINT64_C(77299712),	// LSL_WIDE_ZPmZ_S
    UINT64_C(69241856),	// LSL_WIDE_ZZZ_B
    UINT64_C(73436160),	// LSL_WIDE_ZZZ_H
    UINT64_C(77630464),	// LSL_WIDE_ZZZ_S
    UINT64_C(67338496),	// LSL_ZPmI_B
    UINT64_C(75726848),	// LSL_ZPmI_D
    UINT64_C(67338752),	// LSL_ZPmI_H
    UINT64_C(71532544),	// LSL_ZPmI_S
    UINT64_C(68386816),	// LSL_ZPmZ_B
    UINT64_C(80969728),	// LSL_ZPmZ_D
    UINT64_C(72581120),	// LSL_ZPmZ_H
    UINT64_C(76775424),	// LSL_ZPmZ_S
    UINT64_C(69770240),	// LSL_ZZI_B
    UINT64_C(77634560),	// LSL_ZZI_D
    UINT64_C(70294528),	// LSL_ZZI_H
    UINT64_C(73440256),	// LSL_ZZI_S
    UINT64_C(68517888),	// LSRR_ZPmZ_B
    UINT64_C(81100800),	// LSRR_ZPmZ_D
    UINT64_C(72712192),	// LSRR_ZPmZ_H
    UINT64_C(76906496),	// LSRR_ZPmZ_S
    UINT64_C(448799744),	// LSRVWr
    UINT64_C(2596283392),	// LSRVXr
    UINT64_C(68780032),	// LSR_WIDE_ZPmZ_B
    UINT64_C(72974336),	// LSR_WIDE_ZPmZ_H
    UINT64_C(77168640),	// LSR_WIDE_ZPmZ_S
    UINT64_C(69239808),	// LSR_WIDE_ZZZ_B
    UINT64_C(73434112),	// LSR_WIDE_ZZZ_H
    UINT64_C(77628416),	// LSR_WIDE_ZZZ_S
    UINT64_C(67207424),	// LSR_ZPmI_B
    UINT64_C(75595776),	// LSR_ZPmI_D
    UINT64_C(67207680),	// LSR_ZPmI_H
    UINT64_C(71401472),	// LSR_ZPmI_S
    UINT64_C(68255744),	// LSR_ZPmZ_B
    UINT64_C(80838656),	// LSR_ZPmZ_D
    UINT64_C(72450048),	// LSR_ZPmZ_H
    UINT64_C(76644352),	// LSR_ZPmZ_S
    UINT64_C(69768192),	// LSR_ZZI_B
    UINT64_C(77632512),	// LSR_ZZI_D
    UINT64_C(70292480),	// LSR_ZZI_H
    UINT64_C(73438208),	// LSR_ZZI_S
    UINT64_C(1317015552),	// LUT2_B
    UINT64_C(1321205760),	// LUT2_H
    UINT64_C(1312825344),	// LUT4_B
    UINT64_C(1312821248),	// LUT4_H
    UINT64_C(3230416896),	// LUTI2_2ZTZI_B
    UINT64_C(3230420992),	// LUTI2_2ZTZI_H
    UINT64_C(3230425088),	// LUTI2_2ZTZI_S
    UINT64_C(3230433280),	// LUTI2_4ZTZI_B
    UINT64_C(3230437376),	// LUTI2_4ZTZI_H
    UINT64_C(3230441472),	// LUTI2_4ZTZI_S
    UINT64_C(3231465472),	// LUTI2_S_2ZTZI_B
    UINT64_C(3231469568),	// LUTI2_S_2ZTZI_H
    UINT64_C(3231481856),	// LUTI2_S_4ZTZI_B
    UINT64_C(3231485952),	// LUTI2_S_4ZTZI_H
    UINT64_C(3234594816),	// LUTI2_ZTZI_B
    UINT64_C(3234598912),	// LUTI2_ZTZI_H
    UINT64_C(3234603008),	// LUTI2_ZTZI_S
    UINT64_C(1159770112),	// LUTI2_ZZZI_B
    UINT64_C(1159768064),	// LUTI2_ZZZI_H
    UINT64_C(3230285824),	// LUTI4_2ZTZI_B
    UINT64_C(3230289920),	// LUTI4_2ZTZI_H
    UINT64_C(3230294016),	// LUTI4_2ZTZI_S
    UINT64_C(3230306304),	// LUTI4_4ZTZI_H
    UINT64_C(3230310400),	// LUTI4_4ZTZI_S
    UINT64_C(3230334976),	// LUTI4_4ZZT2Z
    UINT64_C(3231334400),	// LUTI4_S_2ZTZI_B
    UINT64_C(3231338496),	// LUTI4_S_2ZTZI_H
    UINT64_C(3231354880),	// LUTI4_S_4ZTZI_H
    UINT64_C(3231383552),	// LUTI4_S_4ZZT2Z
    UINT64_C(1159771136),	// LUTI4_Z2ZZI
    UINT64_C(3234463744),	// LUTI4_ZTZI_B
    UINT64_C(3234467840),	// LUTI4_ZTZI_H
    UINT64_C(3234471936),	// LUTI4_ZTZI_S
    UINT64_C(1163961344),	// LUTI4_ZZZI_B
    UINT64_C(1159773184),	// LUTI4_ZZZI_H
    UINT64_C(3240162304),	// LUTI6_4Z2Z2ZI
    UINT64_C(3230269440),	// LUTI6_4ZT3Z
    UINT64_C(3240164352),	// LUTI6_S_4Z2Z2ZI
    UINT64_C(3231318016),	// LUTI6_S_4ZT3Z
    UINT64_C(1159769088),	// LUTI6_Z2ZZ
    UINT64_C(1163963392),	// LUTI6_Z2ZZI_H
    UINT64_C(3234349056),	// LUTI6_ZTZ
    UINT64_C(2606759936),	// MADDPT
    UINT64_C(452984832),	// MADDWrrr
    UINT64_C(2600468480),	// MADDXrrr
    UINT64_C(1153488896),	// MAD_CPA
    UINT64_C(67158016),	// MAD_ZPmZZ_B
    UINT64_C(79740928),	// MAD_ZPmZZ_D
    UINT64_C(71352320),	// MAD_ZPmZZ_H
    UINT64_C(75546624),	// MAD_ZPmZZ_S
    UINT64_C(1159757824),	// MATCH_PPzZZ_B
    UINT64_C(1163952128),	// MATCH_PPzZZ_H
    UINT64_C(1153486848),	// MLA_CPA
    UINT64_C(67125248),	// MLA_ZPmZZ_B
    UINT64_C(79708160),	// MLA_ZPmZZ_D
    UINT64_C(71319552),	// MLA_ZPmZZ_H
    UINT64_C(75513856),	// MLA_ZPmZZ_S
    UINT64_C(1155532800),	// MLA_ZZZI_D
    UINT64_C(1142949888),	// MLA_ZZZI_H
    UINT64_C(1151338496),	// MLA_ZZZI_S
    UINT64_C(1310757888),	// MLAv16i8
    UINT64_C(245404672),	// MLAv2i32
    UINT64_C(796917760),	// MLAv2i32_indexed
    UINT64_C(241210368),	// MLAv4i16
    UINT64_C(792723456),	// MLAv4i16_indexed
    UINT64_C(1319146496),	// MLAv4i32
    UINT64_C(1870659584),	// MLAv4i32_indexed
    UINT64_C(1314952192),	// MLAv8i16
    UINT64_C(1866465280),	// MLAv8i16_indexed
    UINT64_C(237016064),	// MLAv8i8
    UINT64_C(67133440),	// MLS_ZPmZZ_B
    UINT64_C(79716352),	// MLS_ZPmZZ_D
    UINT64_C(71327744),	// MLS_ZPmZZ_H
    UINT64_C(75522048),	// MLS_ZPmZZ_S
    UINT64_C(1155533824),	// MLS_ZZZI_D
    UINT64_C(1142950912),	// MLS_ZZZI_H
    UINT64_C(1151339520),	// MLS_ZZZI_S
    UINT64_C(1847628800),	// MLSv16i8
    UINT64_C(782275584),	// MLSv2i32
    UINT64_C(796934144),	// MLSv2i32_indexed
    UINT64_C(778081280),	// MLSv4i16
    UINT64_C(792739840),	// MLSv4i16_indexed
    UINT64_C(1856017408),	// MLSv4i32
    UINT64_C(1870675968),	// MLSv4i32_indexed
    UINT64_C(1851823104),	// MLSv8i16
    UINT64_C(1866481664),	// MLSv8i16_indexed
    UINT64_C(773886976),	// MLSv8i8
    UINT64_C(499155968),	// MOPSSETGE
    UINT64_C(499164160),	// MOPSSETGEN
    UINT64_C(499160064),	// MOPSSETGET
    UINT64_C(499168256),	// MOPSSETGETN
    UINT64_C(3221619200),	// MOVAZ_2ZMI_H_B
    UINT64_C(3234202112),	// MOVAZ_2ZMI_H_D
    UINT64_C(3225813504),	// MOVAZ_2ZMI_H_H
    UINT64_C(3230007808),	// MOVAZ_2ZMI_H_S
    UINT64_C(3221651968),	// MOVAZ_2ZMI_V_B
    UINT64_C(3234234880),	// MOVAZ_2ZMI_V_D
    UINT64_C(3225846272),	// MOVAZ_2ZMI_V_H
    UINT64_C(3230040576),	// MOVAZ_2ZMI_V_S
    UINT64_C(3221620224),	// MOVAZ_4ZMI_H_B
    UINT64_C(3234203136),	// MOVAZ_4ZMI_H_D
    UINT64_C(3225814528),	// MOVAZ_4ZMI_H_H
    UINT64_C(3230008832),	// MOVAZ_4ZMI_H_S
    UINT64_C(3221652992),	// MOVAZ_4ZMI_V_B
    UINT64_C(3234235904),	// MOVAZ_4ZMI_V_D
    UINT64_C(3225847296),	// MOVAZ_4ZMI_V_H
    UINT64_C(3230041600),	// MOVAZ_4ZMI_V_S
    UINT64_C(3221621248),	// MOVAZ_VG2_2ZMXI
    UINT64_C(3221622272),	// MOVAZ_VG4_4ZMXI
    UINT64_C(3221357056),	// MOVAZ_ZMI_H_B
    UINT64_C(3233939968),	// MOVAZ_ZMI_H_D
    UINT64_C(3225551360),	// MOVAZ_ZMI_H_H
    UINT64_C(3234005504),	// MOVAZ_ZMI_H_Q
    UINT64_C(3229745664),	// MOVAZ_ZMI_H_S
    UINT64_C(3221389824),	// MOVAZ_ZMI_V_B
    UINT64_C(3233972736),	// MOVAZ_ZMI_V_D
    UINT64_C(3225584128),	// MOVAZ_ZMI_V_H
    UINT64_C(3234038272),	// MOVAZ_ZMI_V_Q
    UINT64_C(3229778432),	// MOVAZ_ZMI_V_S
    UINT64_C(3221618688),	// MOVA_2ZMXI_H_B
    UINT64_C(3234201600),	// MOVA_2ZMXI_H_D
    UINT64_C(3225812992),	// MOVA_2ZMXI_H_H
    UINT64_C(3230007296),	// MOVA_2ZMXI_H_S
    UINT64_C(3221651456),	// MOVA_2ZMXI_V_B
    UINT64_C(3234234368),	// MOVA_2ZMXI_V_D
    UINT64_C(3225845760),	// MOVA_2ZMXI_V_H
    UINT64_C(3230040064),	// MOVA_2ZMXI_V_S
    UINT64_C(3221619712),	// MOVA_4ZMXI_H_B
    UINT64_C(3234202624),	// MOVA_4ZMXI_H_D
    UINT64_C(3225814016),	// MOVA_4ZMXI_H_H
    UINT64_C(3230008320),	// MOVA_4ZMXI_H_S
    UINT64_C(3221652480),	// MOVA_4ZMXI_V_B
    UINT64_C(3234235392),	// MOVA_4ZMXI_V_D
    UINT64_C(3225846784),	// MOVA_4ZMXI_V_H
    UINT64_C(3230041088),	// MOVA_4ZMXI_V_S
    UINT64_C(3221487616),	// MOVA_MXI2Z_H_B
    UINT64_C(3234070528),	// MOVA_MXI2Z_H_D
    UINT64_C(3225681920),	// MOVA_MXI2Z_H_H
    UINT64_C(3229876224),	// MOVA_MXI2Z_H_S
    UINT64_C(3221520384),	// MOVA_MXI2Z_V_B
    UINT64_C(3234103296),	// MOVA_MXI2Z_V_D
    UINT64_C(3225714688),	// MOVA_MXI2Z_V_H
    UINT64_C(3229908992),	// MOVA_MXI2Z_V_S
    UINT64_C(3221488640),	// MOVA_MXI4Z_H_B
    UINT64_C(3234071552),	// MOVA_MXI4Z_H_D
    UINT64_C(3225682944),	// MOVA_MXI4Z_H_H
    UINT64_C(3229877248),	// MOVA_MXI4Z_H_S
    UINT64_C(3221521408),	// MOVA_MXI4Z_V_B
    UINT64_C(3234104320),	// MOVA_MXI4Z_V_D
    UINT64_C(3225715712),	// MOVA_MXI4Z_V_H
    UINT64_C(3229910016),	// MOVA_MXI4Z_V_S
    UINT64_C(3221620736),	// MOVA_VG2_2ZMXI
    UINT64_C(3221489664),	// MOVA_VG2_MXI2Z
    UINT64_C(3221621760),	// MOVA_VG4_4ZMXI
    UINT64_C(3221490688),	// MOVA_VG4_MXI4Z
    UINT64_C(788587520),	// MOVID
    UINT64_C(1325458432),	// MOVIv16b_ns
    UINT64_C(1862329344),	// MOVIv2d_ns
    UINT64_C(251659264),	// MOVIv2i32
    UINT64_C(251708416),	// MOVIv2s_msl
    UINT64_C(251692032),	// MOVIv4i16
    UINT64_C(1325401088),	// MOVIv4i32
    UINT64_C(1325450240),	// MOVIv4s_msl
    UINT64_C(251716608),	// MOVIv8b_ns
    UINT64_C(1325433856),	// MOVIv8i16
    UINT64_C(1920991232),	// MOVKWi
    UINT64_C(4068474880),	// MOVKXi
    UINT64_C(310378496),	// MOVNWi
    UINT64_C(2457862144),	// MOVNXi
    UINT64_C(68231168),	// MOVPRFX_ZPmZ_B
    UINT64_C(80814080),	// MOVPRFX_ZPmZ_D
    UINT64_C(72425472),	// MOVPRFX_ZPmZ_H
    UINT64_C(76619776),	// MOVPRFX_ZPmZ_S
    UINT64_C(68165632),	// MOVPRFX_ZPzZ_B
    UINT64_C(80748544),	// MOVPRFX_ZPzZ_D
    UINT64_C(72359936),	// MOVPRFX_ZPzZ_H
    UINT64_C(76554240),	// MOVPRFX_ZPzZ_S
    UINT64_C(69254144),	// MOVPRFX_ZZ
    UINT64_C(3226338272),	// MOVT_TIX
    UINT64_C(3226403808),	// MOVT_TIZ
    UINT64_C(3226207200),	// MOVT_XTI
    UINT64_C(1384120320),	// MOVZWi
    UINT64_C(3531603968),	// MOVZXi
    UINT64_C(3579838464),	// MRRS
    UINT64_C(3575644160),	// MRS
    UINT64_C(67166208),	// MSB_ZPmZZ_B
    UINT64_C(79749120),	// MSB_ZPmZZ_D
    UINT64_C(71360512),	// MSB_ZPmZZ_H
    UINT64_C(75554816),	// MSB_ZPmZZ_S
    UINT64_C(3573547008),	// MSR
    UINT64_C(3577741312),	// MSRR
    UINT64_C(3573563423),	// MSRpstateImm1
    UINT64_C(3573563423),	// MSRpstateImm4
    UINT64_C(3573760127),	// MSRpstatesvcrImm1
    UINT64_C(2606792704),	// MSUBPT
    UINT64_C(453017600),	// MSUBWrrr
    UINT64_C(2600501248),	// MSUBXrrr
    UINT64_C(623951872),	// MUL_ZI_B
    UINT64_C(636534784),	// MUL_ZI_D
    UINT64_C(628146176),	// MUL_ZI_H
    UINT64_C(632340480),	// MUL_ZI_S
    UINT64_C(68157440),	// MUL_ZPmZ_B
    UINT64_C(80740352),	// MUL_ZPmZ_D
    UINT64_C(72351744),	// MUL_ZPmZ_H
    UINT64_C(76546048),	// MUL_ZPmZ_S
    UINT64_C(1155594240),	// MUL_ZZZI_D
    UINT64_C(1143011328),	// MUL_ZZZI_H
    UINT64_C(1151399936),	// MUL_ZZZI_S
    UINT64_C(69230592),	// MUL_ZZZ_B
    UINT64_C(81813504),	// MUL_ZZZ_D
    UINT64_C(73424896),	// MUL_ZZZ_H
    UINT64_C(77619200),	// MUL_ZZZ_S
    UINT64_C(1310759936),	// MULv16i8
    UINT64_C(245406720),	// MULv2i32
    UINT64_C(260079616),	// MULv2i32_indexed
    UINT64_C(241212416),	// MULv4i16
    UINT64_C(255885312),	// MULv4i16_indexed
    UINT64_C(1319148544),	// MULv4i32
    UINT64_C(1333821440),	// MULv4i32_indexed
    UINT64_C(1314954240),	// MULv8i16
    UINT64_C(1329627136),	// MULv8i16_indexed
    UINT64_C(237018112),	// MULv8i8
    UINT64_C(788530176),	// MVNIv2i32
    UINT64_C(788579328),	// MVNIv2s_msl
    UINT64_C(788562944),	// MVNIv4i16
    UINT64_C(1862272000),	// MVNIv4i32
    UINT64_C(1862321152),	// MVNIv4s_msl
    UINT64_C(1862304768),	// MVNIv8i16
    UINT64_C(633356816),	// NANDS_PPzPP
    UINT64_C(629162512),	// NAND_PPzPP
    UINT64_C(81804288),	// NBSL_ZZZZ
    UINT64_C(68657152),	// NEG_ZPmZ_B
    UINT64_C(81240064),	// NEG_ZPmZ_D
    UINT64_C(72851456),	// NEG_ZPmZ_H
    UINT64_C(77045760),	// NEG_ZPmZ_S
    UINT64_C(67608576),	// NEG_ZPzZ_B
    UINT64_C(80191488),	// NEG_ZPzZ_D
    UINT64_C(71802880),	// NEG_ZPzZ_H
    UINT64_C(75997184),	// NEG_ZPzZ_S
    UINT64_C(1847638016),	// NEGv16i8
    UINT64_C(2128656384),	// NEGv1i64
    UINT64_C(782284800),	// NEGv2i32
    UINT64_C(1860220928),	// NEGv2i64
    UINT64_C(778090496),	// NEGv4i16
    UINT64_C(1856026624),	// NEGv4i32
    UINT64_C(1851832320),	// NEGv8i16
    UINT64_C(773896192),	// NEGv8i8
    UINT64_C(1159757840),	// NMATCH_PPzZZ_B
    UINT64_C(1163952144),	// NMATCH_PPzZZ_H
    UINT64_C(3573751839),	// NOP
    UINT64_C(633356800),	// NORS_PPzPP
    UINT64_C(629162496),	// NOR_PPzPP
    UINT64_C(69115904),	// NOT_ZPmZ_B
    UINT64_C(81698816),	// NOT_ZPmZ_D
    UINT64_C(73310208),	// NOT_ZPmZ_H
    UINT64_C(77504512),	// NOT_ZPmZ_S
    UINT64_C(68067328),	// NOT_ZPzZ_B
    UINT64_C(80650240),	// NOT_ZPzZ_D
    UINT64_C(72261632),	// NOT_ZPzZ_H
    UINT64_C(76455936),	// NOT_ZPzZ_S
    UINT64_C(1847613440),	// NOTv16i8
    UINT64_C(773871616),	// NOTv8i8
    UINT64_C(633356304),	// ORNS_PPzPP
    UINT64_C(706740224),	// ORNWrs
    UINT64_C(2854223872),	// ORNXrs
    UINT64_C(629162000),	// ORN_PPzPP
    UINT64_C(1323310080),	// ORNv16i8
    UINT64_C(249568256),	// ORNv8i8
    UINT64_C(68952064),	// ORQV_VPZ_B
    UINT64_C(81534976),	// ORQV_VPZ_D
    UINT64_C(73146368),	// ORQV_VPZ_H
    UINT64_C(77340672),	// ORQV_VPZ_S
    UINT64_C(633356288),	// ORRS_PPzPP
    UINT64_C(838860800),	// ORRWri
    UINT64_C(704643072),	// ORRWrs
    UINT64_C(2986344448),	// ORRXri
    UINT64_C(2852126720),	// ORRXrs
    UINT64_C(629161984),	// ORR_PPzPP
    UINT64_C(83886080),	// ORR_ZI
    UINT64_C(68681728),	// ORR_ZPmZ_B
    UINT64_C(81264640),	// ORR_ZPmZ_D
    UINT64_C(72876032),	// ORR_ZPmZ_H
    UINT64_C(77070336),	// ORR_ZPmZ_S
    UINT64_C(73412608),	// ORR_ZZZ
    UINT64_C(1319115776),	// ORRv16i8
    UINT64_C(251663360),	// ORRv2i32
    UINT64_C(251696128),	// ORRv4i16
    UINT64_C(1325405184),	// ORRv4i32
    UINT64_C(1325437952),	// ORRv8i16
    UINT64_C(245373952),	// ORRv8i8
    UINT64_C(68689920),	// ORV_VPZ_B
    UINT64_C(81272832),	// ORV_VPZ_D
    UINT64_C(72884224),	// ORV_VPZ_H
    UINT64_C(77078528),	// ORV_VPZ_S
    UINT64_C(3670083584),	// PACDA
    UINT64_C(3670084608),	// PACDB
    UINT64_C(3670092768),	// PACDZA
    UINT64_C(3670093792),	// PACDZB
    UINT64_C(2596286464),	// PACGA
    UINT64_C(3670081536),	// PACIA
    UINT64_C(3573752095),	// PACIA1716
    UINT64_C(3670117374),	// PACIA171615
    UINT64_C(3573752639),	// PACIASP
    UINT64_C(3670123518),	// PACIASPPC
    UINT64_C(3573752607),	// PACIAZ
    UINT64_C(3670082560),	// PACIB
    UINT64_C(3573752159),	// PACIB1716
    UINT64_C(3670118398),	// PACIB171615
    UINT64_C(3573752703),	// PACIBSP
    UINT64_C(3670124542),	// PACIBSPPC
    UINT64_C(3573752671),	// PACIBZ
    UINT64_C(3670090720),	// PACIZA
    UINT64_C(3670091744),	// PACIZB
    UINT64_C(3573753087),	// PACM
    UINT64_C(3670115326),	// PACNBIASPPC
    UINT64_C(3670116350),	// PACNBIBSPPC
    UINT64_C(622883856),	// PEXT_2PCI_B
    UINT64_C(635466768),	// PEXT_2PCI_D
    UINT64_C(627078160),	// PEXT_2PCI_H
    UINT64_C(631272464),	// PEXT_2PCI_S
    UINT64_C(622882832),	// PEXT_PCI_B
    UINT64_C(635465744),	// PEXT_PCI_D
    UINT64_C(627077136),	// PEXT_PCI_H
    UINT64_C(631271440),	// PEXT_PCI_S
    UINT64_C(622388224),	// PFALSE
    UINT64_C(626573312),	// PFIRST_B
    UINT64_C(1159789568),	// PMLAL_2ZZZ_Q
    UINT64_C(86652928),	// PMOV_PZI_B
    UINT64_C(94910464),	// PMOV_PZI_D
    UINT64_C(86784000),	// PMOV_PZI_H
    UINT64_C(90716160),	// PMOV_PZI_S
    UINT64_C(86718464),	// PMOV_ZIP_B
    UINT64_C(94976000),	// PMOV_ZIP_D
    UINT64_C(86849536),	// PMOV_ZIP_H
    UINT64_C(90781696),	// PMOV_ZIP_S
    UINT64_C(1170237440),	// PMULLB_ZZZ_D
    UINT64_C(1161848832),	// PMULLB_ZZZ_H
    UINT64_C(1157654528),	// PMULLB_ZZZ_Q
    UINT64_C(1170238464),	// PMULLT_ZZZ_D
    UINT64_C(1161849856),	// PMULLT_ZZZ_H
    UINT64_C(1157655552),	// PMULLT_ZZZ_Q
    UINT64_C(1159788544),	// PMULL_2ZZZ_Q
    UINT64_C(1310777344),	// PMULLv16i8
    UINT64_C(249618432),	// PMULLv1i64
    UINT64_C(1323360256),	// PMULLv2i64
    UINT64_C(237035520),	// PMULLv8i8
    UINT64_C(69231616),	// PMUL_ZZZ_B
    UINT64_C(1847630848),	// PMULv16i8
    UINT64_C(773889024),	// PMULv8i8
    UINT64_C(622445568),	// PNEXT_B
    UINT64_C(635028480),	// PNEXT_D
    UINT64_C(626639872),	// PNEXT_H
    UINT64_C(630834176),	// PNEXT_S
    UINT64_C(3288391680),	// PRFB_D_PZI
    UINT64_C(3294658560),	// PRFB_D_SCALED
    UINT64_C(3294625792),	// PRFB_D_SXTW_SCALED
    UINT64_C(3290431488),	// PRFB_D_UXTW_SCALED
    UINT64_C(2243952640),	// PRFB_PRI
    UINT64_C(2214641664),	// PRFB_PRR
    UINT64_C(2214649856),	// PRFB_S_PZI
    UINT64_C(2220883968),	// PRFB_S_SXTW_SCALED
    UINT64_C(2216689664),	// PRFB_S_UXTW_SCALED
    UINT64_C(3313557504),	// PRFD_D_PZI
    UINT64_C(3294683136),	// PRFD_D_SCALED
    UINT64_C(3294650368),	// PRFD_D_SXTW_SCALED
    UINT64_C(3290456064),	// PRFD_D_UXTW_SCALED
    UINT64_C(2243977216),	// PRFD_PRI
    UINT64_C(2239807488),	// PRFD_PRR
    UINT64_C(2239815680),	// PRFD_S_PZI
    UINT64_C(2220908544),	// PRFD_S_SXTW_SCALED
    UINT64_C(2216714240),	// PRFD_S_UXTW_SCALED
    UINT64_C(3296780288),	// PRFH_D_PZI
    UINT64_C(3294666752),	// PRFH_D_SCALED
    UINT64_C(3294633984),	// PRFH_D_SXTW_SCALED
    UINT64_C(3290439680),	// PRFH_D_UXTW_SCALED
    UINT64_C(2243960832),	// PRFH_PRI
    UINT64_C(2223030272),	// PRFH_PRR
    UINT64_C(2223038464),	// PRFH_S_PZI
    UINT64_C(2220892160),	// PRFH_S_SXTW_SCALED
    UINT64_C(2216697856),	// PRFH_S_UXTW_SCALED
    UINT64_C(3623878656),	// PRFMl
    UINT64_C(4171253760),	// PRFMroW
    UINT64_C(4171261952),	// PRFMroX
    UINT64_C(4185915392),	// PRFMui
    UINT64_C(4169138176),	// PRFUMi
    UINT64_C(3305168896),	// PRFW_D_PZI
    UINT64_C(3294674944),	// PRFW_D_SCALED
    UINT64_C(3294642176),	// PRFW_D_SXTW_SCALED
    UINT64_C(3290447872),	// PRFW_D_UXTW_SCALED
    UINT64_C(2243969024),	// PRFW_PRI
    UINT64_C(2231418880),	// PRFW_PRR
    UINT64_C(2231427072),	// PRFW_S_PZI
    UINT64_C(2220900352),	// PRFW_S_SXTW_SCALED
    UINT64_C(2216706048),	// PRFW_S_UXTW_SCALED
    UINT64_C(623132672),	// PSEL_PPPRI_B
    UINT64_C(627064832),	// PSEL_PPPRI_D
    UINT64_C(623394816),	// PSEL_PPPRI_H
    UINT64_C(623919104),	// PSEL_PPPRI_S
    UINT64_C(626049024),	// PTEST_PP
    UINT64_C(622452736),	// PTRUES_B
    UINT64_C(635035648),	// PTRUES_D
    UINT64_C(626647040),	// PTRUES_H
    UINT64_C(630841344),	// PTRUES_S
    UINT64_C(622387200),	// PTRUE_B
    UINT64_C(622884880),	// PTRUE_C_B
    UINT64_C(635467792),	// PTRUE_C_D
    UINT64_C(627079184),	// PTRUE_C_H
    UINT64_C(631273488),	// PTRUE_C_S
    UINT64_C(634970112),	// PTRUE_D
    UINT64_C(626581504),	// PTRUE_H
    UINT64_C(630775808),	// PTRUE_S
    UINT64_C(87113728),	// PUNPKHI_PP
    UINT64_C(87048192),	// PUNPKLO_PP
    UINT64_C(1163945984),	// RADDHNB_ZZZ_B
    UINT64_C(1168140288),	// RADDHNB_ZZZ_H
    UINT64_C(1172334592),	// RADDHNB_ZZZ_S
    UINT64_C(1163947008),	// RADDHNT_ZZZ_B
    UINT64_C(1168141312),	// RADDHNT_ZZZ_H
    UINT64_C(1172335616),	// RADDHNT_ZZZ_S
    UINT64_C(782254080),	// RADDHNv2i64_v2i32
    UINT64_C(1855995904),	// RADDHNv2i64_v4i32
    UINT64_C(778059776),	// RADDHNv4i32_v4i16
    UINT64_C(1851801600),	// RADDHNv4i32_v8i16
    UINT64_C(1847607296),	// RADDHNv8i16_v16i8
    UINT64_C(773865472),	// RADDHNv8i16_v8i8
    UINT64_C(3462433792),	// RAX1
    UINT64_C(1159787520),	// RAX1_ZZZ_D
    UINT64_C(1522532352),	// RBITWr
    UINT64_C(3670016000),	// RBITXr
    UINT64_C(86474752),	// RBIT_ZPmZ_B
    UINT64_C(99057664),	// RBIT_ZPmZ_D
    UINT64_C(90669056),	// RBIT_ZPmZ_H
    UINT64_C(94863360),	// RBIT_ZPmZ_S
    UINT64_C(86482944),	// RBIT_ZPzZ_B
    UINT64_C(99065856),	// RBIT_ZPzZ_D
    UINT64_C(90677248),	// RBIT_ZPzZ_H
    UINT64_C(94871552),	// RBIT_ZPzZ_S
    UINT64_C(1851807744),	// RBITv16i8
    UINT64_C(778065920),	// RBITv8i8
    UINT64_C(421529600),	// RCWCAS
    UINT64_C(429918208),	// RCWCASA
    UINT64_C(434112512),	// RCWCASAL
    UINT64_C(425723904),	// RCWCASL
    UINT64_C(421530624),	// RCWCASP
    UINT64_C(429919232),	// RCWCASPA
    UINT64_C(434113536),	// RCWCASPAL
    UINT64_C(425724928),	// RCWCASPL
    UINT64_C(941658112),	// RCWCLR
    UINT64_C(950046720),	// RCWCLRA
    UINT64_C(954241024),	// RCWCLRAL
    UINT64_C(945852416),	// RCWCLRL
    UINT64_C(421564416),	// RCWCLRP
    UINT64_C(429953024),	// RCWCLRPA
    UINT64_C(434147328),	// RCWCLRPAL
    UINT64_C(425758720),	// RCWCLRPL
    UINT64_C(2015399936),	// RCWCLRS
    UINT64_C(2023788544),	// RCWCLRSA
    UINT64_C(2027982848),	// RCWCLRSAL
    UINT64_C(2019594240),	// RCWCLRSL
    UINT64_C(1495306240),	// RCWCLRSP
    UINT64_C(1503694848),	// RCWCLRSPA
    UINT64_C(1507889152),	// RCWCLRSPAL
    UINT64_C(1499500544),	// RCWCLRSPL
    UINT64_C(1495271424),	// RCWSCAS
    UINT64_C(1503660032),	// RCWSCASA
    UINT64_C(1507854336),	// RCWSCASAL
    UINT64_C(1499465728),	// RCWSCASL
    UINT64_C(1495272448),	// RCWSCASP
    UINT64_C(1503661056),	// RCWSCASPA
    UINT64_C(1507855360),	// RCWSCASPAL
    UINT64_C(1499466752),	// RCWSCASPL
    UINT64_C(941666304),	// RCWSET
    UINT64_C(950054912),	// RCWSETA
    UINT64_C(954249216),	// RCWSETAL
    UINT64_C(945860608),	// RCWSETL
    UINT64_C(421572608),	// RCWSETP
    UINT64_C(429961216),	// RCWSETPA
    UINT64_C(434155520),	// RCWSETPAL
    UINT64_C(425766912),	// RCWSETPL
    UINT64_C(2015408128),	// RCWSETS
    UINT64_C(2023796736),	// RCWSETSA
    UINT64_C(2027991040),	// RCWSETSAL
    UINT64_C(2019602432),	// RCWSETSL
    UINT64_C(1495314432),	// RCWSETSP
    UINT64_C(1503703040),	// RCWSETSPA
    UINT64_C(1507897344),	// RCWSETSPAL
    UINT64_C(1499508736),	// RCWSETSPL
    UINT64_C(941662208),	// RCWSWP
    UINT64_C(950050816),	// RCWSWPA
    UINT64_C(954245120),	// RCWSWPAL
    UINT64_C(945856512),	// RCWSWPL
    UINT64_C(421568512),	// RCWSWPP
    UINT64_C(429957120),	// RCWSWPPA
    UINT64_C(434151424),	// RCWSWPPAL
    UINT64_C(425762816),	// RCWSWPPL
    UINT64_C(2015404032),	// RCWSWPS
    UINT64_C(2023792640),	// RCWSWPSA
    UINT64_C(2027986944),	// RCWSWPSAL
    UINT64_C(2019598336),	// RCWSWPSL
    UINT64_C(1495310336),	// RCWSWPSP
    UINT64_C(1503698944),	// RCWSWPSPA
    UINT64_C(1507893248),	// RCWSWPSPAL
    UINT64_C(1499504640),	// RCWSWPSPL
    UINT64_C(626585600),	// RDFFRS_PPz
    UINT64_C(622456832),	// RDFFR_P
    UINT64_C(622391296),	// RDFFR_PPz
    UINT64_C(79648768),	// RDSVLI_XI
    UINT64_C(79646720),	// RDVLI_XI
    UINT64_C(3596550144),	// RET
    UINT64_C(3596553215),	// RETAA
    UINT64_C(1426063391),	// RETAASPPCi
    UINT64_C(3596553184),	// RETAASPPCr
    UINT64_C(3596554239),	// RETAB
    UINT64_C(1428160543),	// RETABSPPCi
    UINT64_C(3596554208),	// RETABSPPCr
    UINT64_C(1522533376),	// REV16Wr
    UINT64_C(3670017024),	// REV16Xr
    UINT64_C(1310726144),	// REV16v16i8
    UINT64_C(236984320),	// REV16v8i8
    UINT64_C(3670018048),	// REV32Xr
    UINT64_C(1847592960),	// REV32v16i8
    UINT64_C(778045440),	// REV32v4i16
    UINT64_C(1851787264),	// REV32v8i16
    UINT64_C(773851136),	// REV32v8i8
    UINT64_C(1310722048),	// REV64v16i8
    UINT64_C(245368832),	// REV64v2i32
    UINT64_C(241174528),	// REV64v4i16
    UINT64_C(1319110656),	// REV64v4i32
    UINT64_C(1314916352),	// REV64v8i16
    UINT64_C(236980224),	// REV64v8i8
    UINT64_C(98861056),	// REVB_ZPmZ_D
    UINT64_C(90472448),	// REVB_ZPmZ_H
    UINT64_C(94666752),	// REVB_ZPmZ_S
    UINT64_C(98869248),	// REVB_ZPzZ_D
    UINT64_C(90480640),	// REVB_ZPzZ_H
    UINT64_C(94674944),	// REVB_ZPzZ_S
    UINT64_C(86933504),	// REVD_ZPmZ
    UINT64_C(86941696),	// REVD_ZPzZ
    UINT64_C(98926592),	// REVH_ZPmZ_D
    UINT64_C(94732288),	// REVH_ZPmZ_S
    UINT64_C(98934784),	// REVH_ZPzZ_D
    UINT64_C(94740480),	// REVH_ZPzZ_S
    UINT64_C(98992128),	// REVW_ZPmZ_D
    UINT64_C(99000320),	// REVW_ZPzZ_D
    UINT64_C(1522534400),	// REVWr
    UINT64_C(3670019072),	// REVXr
    UINT64_C(87310336),	// REV_PP_B
    UINT64_C(99893248),	// REV_PP_D
    UINT64_C(91504640),	// REV_PP_H
    UINT64_C(95698944),	// REV_PP_S
    UINT64_C(87570432),	// REV_ZZ_B
    UINT64_C(100153344),	// REV_ZZ_D
    UINT64_C(91764736),	// REV_ZZ_H
    UINT64_C(95959040),	// REV_ZZ_S
    UINT64_C(3120563200),	// RMIF
    UINT64_C(448801792),	// RORVWr
    UINT64_C(2596285440),	// RORVXr
    UINT64_C(4171253784),	// RPRFM
    UINT64_C(1160255488),	// RSHRNB_ZZI_B
    UINT64_C(1160779776),	// RSHRNB_ZZI_H
    UINT64_C(1163925504),	// RSHRNB_ZZI_S
    UINT64_C(1160256512),	// RSHRNT_ZZI_B
    UINT64_C(1160780800),	// RSHRNT_ZZI_H
    UINT64_C(1163926528),	// RSHRNT_ZZI_S
    UINT64_C(1325960192),	// RSHRNv16i8_shift
    UINT64_C(253791232),	// RSHRNv2i32_shift
    UINT64_C(252742656),	// RSHRNv4i16_shift
    UINT64_C(1327533056),	// RSHRNv4i32_shift
    UINT64_C(1326484480),	// RSHRNv8i16_shift
    UINT64_C(252218368),	// RSHRNv8i8_shift
    UINT64_C(1163950080),	// RSUBHNB_ZZZ_B
    UINT64_C(1168144384),	// RSUBHNB_ZZZ_H
    UINT64_C(1172338688),	// RSUBHNB_ZZZ_S
    UINT64_C(1163951104),	// RSUBHNT_ZZZ_B
    UINT64_C(1168145408),	// RSUBHNT_ZZZ_H
    UINT64_C(1172339712),	// RSUBHNT_ZZZ_S
    UINT64_C(782262272),	// RSUBHNv2i64_v2i32
    UINT64_C(1856004096),	// RSUBHNv2i64_v4i32
    UINT64_C(778067968),	// RSUBHNv4i32_v4i16
    UINT64_C(1851809792),	// RSUBHNv4i32_v8i16
    UINT64_C(1847615488),	// RSUBHNv8i16_v16i8
    UINT64_C(773873664),	// RSUBHNv8i16_v8i8
    UINT64_C(1170259968),	// SABALB_ZZZ_D
    UINT64_C(1161871360),	// SABALB_ZZZ_H
    UINT64_C(1166065664),	// SABALB_ZZZ_S
    UINT64_C(1170260992),	// SABALT_ZZZ_D
    UINT64_C(1161872384),	// SABALT_ZZZ_H
    UINT64_C(1166066688),	// SABALT_ZZZ_S
    UINT64_C(1145099264),	// SABAL_ZZZ_BtoH
    UINT64_C(1149293568),	// SABAL_ZZZ_HtoS
    UINT64_C(1153487872),	// SABAL_ZZZ_StoD
    UINT64_C(1310740480),	// SABALv16i8_v8i16
    UINT64_C(245387264),	// SABALv2i32_v2i64
    UINT64_C(241192960),	// SABALv4i16_v4i32
    UINT64_C(1319129088),	// SABALv4i32_v2i64
    UINT64_C(1314934784),	// SABALv8i16_v4i32
    UINT64_C(236998656),	// SABALv8i8_v8i16
    UINT64_C(1157691392),	// SABA_ZZZ_B
    UINT64_C(1170274304),	// SABA_ZZZ_D
    UINT64_C(1161885696),	// SABA_ZZZ_H
    UINT64_C(1166080000),	// SABA_ZZZ_S
    UINT64_C(1310751744),	// SABAv16i8
    UINT64_C(245398528),	// SABAv2i32
    UINT64_C(241204224),	// SABAv4i16
    UINT64_C(1319140352),	// SABAv4i32
    UINT64_C(1314946048),	// SABAv8i16
    UINT64_C(237009920),	// SABAv8i8
    UINT64_C(1170223104),	// SABDLB_ZZZ_D
    UINT64_C(1161834496),	// SABDLB_ZZZ_H
    UINT64_C(1166028800),	// SABDLB_ZZZ_S
    UINT64_C(1170224128),	// SABDLT_ZZZ_D
    UINT64_C(1161835520),	// SABDLT_ZZZ_H
    UINT64_C(1166029824),	// SABDLT_ZZZ_S
    UINT64_C(1310748672),	// SABDLv16i8_v8i16
    UINT64_C(245395456),	// SABDLv2i32_v2i64
    UINT64_C(241201152),	// SABDLv4i16_v4i32
    UINT64_C(1319137280),	// SABDLv4i32_v2i64
    UINT64_C(1314942976),	// SABDLv8i16_v4i32
    UINT64_C(237006848),	// SABDLv8i8_v8i16
    UINT64_C(67895296),	// SABD_ZPmZ_B
    UINT64_C(80478208),	// SABD_ZPmZ_D
    UINT64_C(72089600),	// SABD_ZPmZ_H
    UINT64_C(76283904),	// SABD_ZPmZ_S
    UINT64_C(1310749696),	// SABDv16i8
    UINT64_C(245396480),	// SABDv2i32
    UINT64_C(241202176),	// SABDv4i16
    UINT64_C(1319138304),	// SABDv4i32
    UINT64_C(1314944000),	// SABDv8i16
    UINT64_C(237007872),	// SABDv8i8
    UINT64_C(1153736704),	// SADALP_ZPmZ_D
    UINT64_C(1145348096),	// SADALP_ZPmZ_H
    UINT64_C(1149542400),	// SADALP_ZPmZ_S
    UINT64_C(1310746624),	// SADALPv16i8_v8i16
    UINT64_C(245393408),	// SADALPv2i32_v1i64
    UINT64_C(241199104),	// SADALPv4i16_v2i32
    UINT64_C(1319135232),	// SADALPv4i32_v2i64
    UINT64_C(1314940928),	// SADALPv8i16_v4i32
    UINT64_C(237004800),	// SADALPv8i8_v4i16
    UINT64_C(1170243584),	// SADDLBT_ZZZ_D
    UINT64_C(1161854976),	// SADDLBT_ZZZ_H
    UINT64_C(1166049280),	// SADDLBT_ZZZ_S
    UINT64_C(1170210816),	// SADDLB_ZZZ_D
    UINT64_C(1161822208),	// SADDLB_ZZZ_H
    UINT64_C(1166016512),	// SADDLB_ZZZ_S
    UINT64_C(1310730240),	// SADDLPv16i8_v8i16
    UINT64_C(245377024),	// SADDLPv2i32_v1i64
    UINT64_C(241182720),	// SADDLPv4i16_v2i32
    UINT64_C(1319118848),	// SADDLPv4i32_v2i64
    UINT64_C(1314924544),	// SADDLPv8i16_v4i32
    UINT64_C(236988416),	// SADDLPv8i8_v4i16
    UINT64_C(1170211840),	// SADDLT_ZZZ_D
    UINT64_C(1161823232),	// SADDLT_ZZZ_H
    UINT64_C(1166017536),	// SADDLT_ZZZ_S
    UINT64_C(1311782912),	// SADDLVv16i8v
    UINT64_C(242235392),	// SADDLVv4i16v
    UINT64_C(1320171520),	// SADDLVv4i32v
    UINT64_C(1315977216),	// SADDLVv8i16v
    UINT64_C(238041088),	// SADDLVv8i8v
    UINT64_C(1310720000),	// SADDLv16i8_v8i16
    UINT64_C(245366784),	// SADDLv2i32_v2i64
    UINT64_C(241172480),	// SADDLv4i16_v4i32
    UINT64_C(1319108608),	// SADDLv4i32_v2i64
    UINT64_C(1314914304),	// SADDLv8i16_v4i32
    UINT64_C(236978176),	// SADDLv8i8_v8i16
    UINT64_C(67117056),	// SADDV_VPZ_B
    UINT64_C(71311360),	// SADDV_VPZ_H
    UINT64_C(75505664),	// SADDV_VPZ_S
    UINT64_C(1170227200),	// SADDWB_ZZZ_D
    UINT64_C(1161838592),	// SADDWB_ZZZ_H
    UINT64_C(1166032896),	// SADDWB_ZZZ_S
    UINT64_C(1170228224),	// SADDWT_ZZZ_D
    UINT64_C(1161839616),	// SADDWT_ZZZ_H
    UINT64_C(1166033920),	// SADDWT_ZZZ_S
    UINT64_C(1310724096),	// SADDWv16i8_v8i16
    UINT64_C(245370880),	// SADDWv2i32_v2i64
    UINT64_C(241176576),	// SADDWv4i16_v4i32
    UINT64_C(1319112704),	// SADDWv4i32_v2i64
    UINT64_C(1314918400),	// SADDWv8i16_v4i32
    UINT64_C(236982272),	// SADDWv8i8_v8i16
    UINT64_C(3573756159),	// SB
    UINT64_C(1170264064),	// SBCLB_ZZZ_D
    UINT64_C(1166069760),	// SBCLB_ZZZ_S
    UINT64_C(1170265088),	// SBCLT_ZZZ_D
    UINT64_C(1166070784),	// SBCLT_ZZZ_S
    UINT64_C(2046820352),	// SBCSWr
    UINT64_C(4194304000),	// SBCSXr
    UINT64_C(1509949440),	// SBCWr
    UINT64_C(3657433088),	// SBCXr
    UINT64_C(318767104),	// SBFMWri
    UINT64_C(2470445056),	// SBFMXri
    UINT64_C(3240150016),	// SCLAMP_VG2_2Z2Z_B
    UINT64_C(3252732928),	// SCLAMP_VG2_2Z2Z_D
    UINT64_C(3244344320),	// SCLAMP_VG2_2Z2Z_H
    UINT64_C(3248538624),	// SCLAMP_VG2_2Z2Z_S
    UINT64_C(3240152064),	// SCLAMP_VG4_4Z4Z_B
    UINT64_C(3252734976),	// SCLAMP_VG4_4Z4Z_D
    UINT64_C(3244346368),	// SCLAMP_VG4_4Z4Z_H
    UINT64_C(3248540672),	// SCLAMP_VG4_4Z4Z_S
    UINT64_C(1140899840),	// SCLAMP_ZZZ_B
    UINT64_C(1153482752),	// SCLAMP_ZZZ_D
    UINT64_C(1145094144),	// SCLAMP_ZZZ_H
    UINT64_C(1149288448),	// SCLAMP_ZZZ_S
    UINT64_C(511442944),	// SCVTFDSr
    UINT64_C(2667315200),	// SCVTFHDr
    UINT64_C(519831552),	// SCVTFHSr
    UINT64_C(1699493888),	// SCVTFLT_ZZ_BtoH
    UINT64_C(1703688192),	// SCVTFLT_ZZ_HtoS
    UINT64_C(1707882496),	// SCVTFLT_ZZ_StoD
    UINT64_C(2654732288),	// SCVTFSDr
    UINT64_C(507674624),	// SCVTFSWDri
    UINT64_C(516063232),	// SCVTFSWHri
    UINT64_C(503480320),	// SCVTFSWSri
    UINT64_C(2655125504),	// SCVTFSXDri
    UINT64_C(2663514112),	// SCVTFSXHri
    UINT64_C(2650931200),	// SCVTFSXSri
    UINT64_C(509739008),	// SCVTFUWDri
    UINT64_C(518127616),	// SCVTFUWHri
    UINT64_C(505544704),	// SCVTFUWSri
    UINT64_C(2657222656),	// SCVTFUXDri
    UINT64_C(2665611264),	// SCVTFUXHri
    UINT64_C(2653028352),	// SCVTFUXSri
    UINT64_C(3240288256),	// SCVTF_2Z2Z_StoS
    UINT64_C(3241336832),	// SCVTF_4Z4Z_StoS
    UINT64_C(1708564480),	// SCVTF_ZPmZ_DtoD
    UINT64_C(1700175872),	// SCVTF_ZPmZ_DtoH
    UINT64_C(1708433408),	// SCVTF_ZPmZ_DtoS
    UINT64_C(1699913728),	// SCVTF_ZPmZ_HtoH
    UINT64_C(1708171264),	// SCVTF_ZPmZ_StoD
    UINT64_C(1700044800),	// SCVTF_ZPmZ_StoH
    UINT64_C(1704239104),	// SCVTF_ZPmZ_StoS
    UINT64_C(1692254208),	// SCVTF_ZPzZ_DtoD
    UINT64_C(1683865600),	// SCVTF_ZPzZ_DtoH
    UINT64_C(1692237824),	// SCVTF_ZPzZ_DtoS
    UINT64_C(1683800064),	// SCVTF_ZPzZ_HtoH
    UINT64_C(1692172288),	// SCVTF_ZPzZ_StoD
    UINT64_C(1683849216),	// SCVTF_ZPzZ_StoH
    UINT64_C(1688043520),	// SCVTF_ZPzZ_StoS
    UINT64_C(1699491840),	// SCVTF_ZZ_BtoH
    UINT64_C(1703686144),	// SCVTF_ZZ_HtoS
    UINT64_C(1707880448),	// SCVTF_ZZ_StoD
    UINT64_C(1598088192),	// SCVTFd
    UINT64_C(1594942464),	// SCVTFh
    UINT64_C(1595991040),	// SCVTFs
    UINT64_C(1585043456),	// SCVTFv1i16
    UINT64_C(1579276288),	// SCVTFv1i32
    UINT64_C(1583470592),	// SCVTFv1i64
    UINT64_C(237099008),	// SCVTFv2f32
    UINT64_C(1315035136),	// SCVTFv2f64
    UINT64_C(253813760),	// SCVTFv2i32_shift
    UINT64_C(1329652736),	// SCVTFv2i64_shift
    UINT64_C(242866176),	// SCVTFv4f16
    UINT64_C(1310840832),	// SCVTFv4f32
    UINT64_C(252765184),	// SCVTFv4i16_shift
    UINT64_C(1327555584),	// SCVTFv4i32_shift
    UINT64_C(1316608000),	// SCVTFv8f16
    UINT64_C(1326507008),	// SCVTFv8i16_shift
    UINT64_C(81133568),	// SDIVR_ZPmZ_D
    UINT64_C(76939264),	// SDIVR_ZPmZ_S
    UINT64_C(448793600),	// SDIVWr
    UINT64_C(2596277248),	// SDIVXr
    UINT64_C(81002496),	// SDIV_ZPmZ_D
    UINT64_C(76808192),	// SDIV_ZPmZ_S
    UINT64_C(3248493568),	// SDOT_VG2_M2Z2Z_BtoS
    UINT64_C(3252687872),	// SDOT_VG2_M2Z2Z_HtoD
    UINT64_C(3252687880),	// SDOT_VG2_M2Z2Z_HtoS
    UINT64_C(3243249696),	// SDOT_VG2_M2ZZI_BToS
    UINT64_C(3243249664),	// SDOT_VG2_M2ZZI_HToS
    UINT64_C(3251634184),	// SDOT_VG2_M2ZZI_HtoD
    UINT64_C(3240104960),	// SDOT_VG2_M2ZZ_BtoS
    UINT64_C(3244299264),	// SDOT_VG2_M2ZZ_HtoD
    UINT64_C(3244299272),	// SDOT_VG2_M2ZZ_HtoS
    UINT64_C(3248559104),	// SDOT_VG4_M4Z4Z_BtoS
    UINT64_C(3252753408),	// SDOT_VG4_M4Z4Z_HtoD
    UINT64_C(3252753416),	// SDOT_VG4_M4Z4Z_HtoS
    UINT64_C(3243282464),	// SDOT_VG4_M4ZZI_BToS
    UINT64_C(3243282432),	// SDOT_VG4_M4ZZI_HToS
    UINT64_C(3251666952),	// SDOT_VG4_M4ZZI_HtoD
    UINT64_C(3241153536),	// SDOT_VG4_M4ZZ_BtoS
    UINT64_C(3245347840),	// SDOT_VG4_M4ZZ_HtoD
    UINT64_C(3245347848),	// SDOT_VG4_M4ZZ_HtoS
    UINT64_C(1142947840),	// SDOT_ZZZI_BtoH
    UINT64_C(1151336448),	// SDOT_ZZZI_BtoS
    UINT64_C(1155530752),	// SDOT_ZZZI_HtoD
    UINT64_C(1149290496),	// SDOT_ZZZI_HtoS
    UINT64_C(1145044992),	// SDOT_ZZZ_BtoH
    UINT64_C(1149239296),	// SDOT_ZZZ_BtoS
    UINT64_C(1153433600),	// SDOT_ZZZ_HtoD
    UINT64_C(1140901888),	// SDOT_ZZZ_HtoS
    UINT64_C(1333846016),	// SDOTlanev16i8
    UINT64_C(260104192),	// SDOTlanev8i8
    UINT64_C(1317049344),	// SDOTv16i8
    UINT64_C(243307520),	// SDOTv8i8
    UINT64_C(620773904),	// SEL_PPPP
    UINT64_C(3240132608),	// SEL_VG2_2ZC2Z2Z_B
    UINT64_C(3252715520),	// SEL_VG2_2ZC2Z2Z_D
    UINT64_C(3244326912),	// SEL_VG2_2ZC2Z2Z_H
    UINT64_C(3248521216),	// SEL_VG2_2ZC2Z2Z_S
    UINT64_C(3240198144),	// SEL_VG4_4ZC4Z4Z_B
    UINT64_C(3252781056),	// SEL_VG4_4ZC4Z4Z_D
    UINT64_C(3244392448),	// SEL_VG4_4ZC4Z4Z_H
    UINT64_C(3248586752),	// SEL_VG4_4ZC4Z4Z_S
    UINT64_C(86032384),	// SEL_ZPZZ_B
    UINT64_C(98615296),	// SEL_ZPZZ_D
    UINT64_C(90226688),	// SEL_ZPZZ_H
    UINT64_C(94420992),	// SEL_ZPZZ_S
    UINT64_C(432047104),	// SETE
    UINT64_C(432055296),	// SETEN
    UINT64_C(432051200),	// SETET
    UINT64_C(432059392),	// SETETN
    UINT64_C(973096973),	// SETF16
    UINT64_C(973080589),	// SETF8
    UINT64_C(623677440),	// SETFFR
    UINT64_C(499139584),	// SETGM
    UINT64_C(499147776),	// SETGMN
    UINT64_C(499143680),	// SETGMT
    UINT64_C(499151872),	// SETGMTN
    UINT64_C(501186560),	// SETGOE
    UINT64_C(501194752),	// SETGOEN
    UINT64_C(501190656),	// SETGOET
    UINT64_C(501198848),	// SETGOETN
    UINT64_C(501170176),	// SETGOM
    UINT64_C(501178368),	// SETGOMN
    UINT64_C(501174272),	// SETGOMT
    UINT64_C(501182464),	// SETGOMTN
    UINT64_C(501153792),	// SETGOP
    UINT64_C(501161984),	// SETGOPN
    UINT64_C(501157888),	// SETGOPT
    UINT64_C(501166080),	// SETGOPTN
    UINT64_C(499123200),	// SETGP
    UINT64_C(499131392),	// SETGPN
    UINT64_C(499127296),	// SETGPT
    UINT64_C(499135488),	// SETGPTN
    UINT64_C(432030720),	// SETM
    UINT64_C(432038912),	// SETMN
    UINT64_C(432034816),	// SETMT
    UINT64_C(432043008),	// SETMTN
    UINT64_C(432014336),	// SETP
    UINT64_C(432022528),	// SETPN
    UINT64_C(432018432),	// SETPT
    UINT64_C(432026624),	// SETPTN
    UINT64_C(1577058304),	// SHA1Crrr
    UINT64_C(1579681792),	// SHA1Hrr
    UINT64_C(1577066496),	// SHA1Mrrr
    UINT64_C(1577062400),	// SHA1Prrr
    UINT64_C(1577070592),	// SHA1SU0rrr
    UINT64_C(1579685888),	// SHA1SU1rr
    UINT64_C(1577078784),	// SHA256H2rrr
    UINT64_C(1577074688),	// SHA256Hrrr
    UINT64_C(1579689984),	// SHA256SU0rr
    UINT64_C(1577082880),	// SHA256SU1rrr
    UINT64_C(3462430720),	// SHA512H
    UINT64_C(3462431744),	// SHA512H2
    UINT64_C(3468722176),	// SHA512SU0
    UINT64_C(3462432768),	// SHA512SU1
    UINT64_C(1141932032),	// SHADD_ZPmZ_B
    UINT64_C(1154514944),	// SHADD_ZPmZ_D
    UINT64_C(1146126336),	// SHADD_ZPmZ_H
    UINT64_C(1150320640),	// SHADD_ZPmZ_S
    UINT64_C(1310721024),	// SHADDv16i8
    UINT64_C(245367808),	// SHADDv2i32
    UINT64_C(241173504),	// SHADDv4i16
    UINT64_C(1319109632),	// SHADDv4i32
    UINT64_C(1314915328),	// SHADDv8i16
    UINT64_C(236979200),	// SHADDv8i8
    UINT64_C(1847670784),	// SHLLv16i8
    UINT64_C(782317568),	// SHLLv2i32
    UINT64_C(778123264),	// SHLLv4i16
    UINT64_C(1856059392),	// SHLLv4i32
    UINT64_C(1851865088),	// SHLLv8i16
    UINT64_C(773928960),	// SHLLv8i8
    UINT64_C(1598051328),	// SHLd
    UINT64_C(1325945856),	// SHLv16i8_shift
    UINT64_C(253776896),	// SHLv2i32_shift
    UINT64_C(1329615872),	// SHLv2i64_shift
    UINT64_C(252728320),	// SHLv4i16_shift
    UINT64_C(1327518720),	// SHLv4i32_shift
    UINT64_C(1326470144),	// SHLv8i16_shift
    UINT64_C(252204032),	// SHLv8i8_shift
    UINT64_C(1160253440),	// SHRNB_ZZI_B
    UINT64_C(1160777728),	// SHRNB_ZZI_H
    UINT64_C(1163923456),	// SHRNB_ZZI_S
    UINT64_C(1160254464),	// SHRNT_ZZI_B
    UINT64_C(1160778752),	// SHRNT_ZZI_H
    UINT64_C(1163924480),	// SHRNT_ZZI_S
    UINT64_C(1325958144),	// SHRNv16i8_shift
    UINT64_C(253789184),	// SHRNv2i32_shift
    UINT64_C(252740608),	// SHRNv4i16_shift
    UINT64_C(1327531008),	// SHRNv4i32_shift
    UINT64_C(1326482432),	// SHRNv8i16_shift
    UINT64_C(252216320),	// SHRNv8i8_shift
    UINT64_C(1142325248),	// SHSUBR_ZPmZ_B
    UINT64_C(1154908160),	// SHSUBR_ZPmZ_D
    UINT64_C(1146519552),	// SHSUBR_ZPmZ_H
    UINT64_C(1150713856),	// SHSUBR_ZPmZ_S
    UINT64_C(1142063104),	// SHSUB_ZPmZ_B
    UINT64_C(1154646016),	// SHSUB_ZPmZ_D
    UINT64_C(1146257408),	// SHSUB_ZPmZ_H
    UINT64_C(1150451712),	// SHSUB_ZPmZ_S
    UINT64_C(1310729216),	// SHSUBv16i8
    UINT64_C(245376000),	// SHSUBv2i32
    UINT64_C(241181696),	// SHSUBv4i16
    UINT64_C(1319117824),	// SHSUBv4i32
    UINT64_C(1314923520),	// SHSUBv8i16
    UINT64_C(236987392),	// SHSUBv8i8
    UINT64_C(3573753439),	// SHUH
    UINT64_C(1158214656),	// SLI_ZZI_B
    UINT64_C(1166078976),	// SLI_ZZI_D
    UINT64_C(1158738944),	// SLI_ZZI_H
    UINT64_C(1161884672),	// SLI_ZZI_S
    UINT64_C(2134922240),	// SLId
    UINT64_C(1862816768),	// SLIv16i8_shift
    UINT64_C(790647808),	// SLIv2i32_shift
    UINT64_C(1866486784),	// SLIv2i64_shift
    UINT64_C(789599232),	// SLIv4i16_shift
    UINT64_C(1864389632),	// SLIv4i32_shift
    UINT64_C(1863341056),	// SLIv8i16_shift
    UINT64_C(789074944),	// SLIv8i8_shift
    UINT64_C(3462447104),	// SM3PARTW1
    UINT64_C(3462448128),	// SM3PARTW2
    UINT64_C(3460300800),	// SM3SS1
    UINT64_C(3460333568),	// SM3TT1A
    UINT64_C(3460334592),	// SM3TT1B
    UINT64_C(3460335616),	// SM3TT2A
    UINT64_C(3460336640),	// SM3TT2B
    UINT64_C(3468723200),	// SM4E
    UINT64_C(1159786496),	// SM4EKEY_ZZZ_S
    UINT64_C(3462449152),	// SM4ENCKEY
    UINT64_C(1159979008),	// SM4E_ZZZ_S
    UINT64_C(2602565632),	// SMADDLrrr
    UINT64_C(1142202368),	// SMAXP_ZPmZ_B
    UINT64_C(1154785280),	// SMAXP_ZPmZ_D
    UINT64_C(1146396672),	// SMAXP_ZPmZ_H
    UINT64_C(1150590976),	// SMAXP_ZPmZ_S
    UINT64_C(1310761984),	// SMAXPv16i8
    UINT64_C(245408768),	// SMAXPv2i32
    UINT64_C(241214464),	// SMAXPv4i16
    UINT64_C(1319150592),	// SMAXPv4i32
    UINT64_C(1314956288),	// SMAXPv8i16
    UINT64_C(237020160),	// SMAXPv8i8
    UINT64_C(67903488),	// SMAXQV_VPZ_B
    UINT64_C(80486400),	// SMAXQV_VPZ_D
    UINT64_C(72097792),	// SMAXQV_VPZ_H
    UINT64_C(76292096),	// SMAXQV_VPZ_S
    UINT64_C(67641344),	// SMAXV_VPZ_B
    UINT64_C(80224256),	// SMAXV_VPZ_D
    UINT64_C(71835648),	// SMAXV_VPZ_H
    UINT64_C(76029952),	// SMAXV_VPZ_S
    UINT64_C(1311811584),	// SMAXVv16i8v
    UINT64_C(242264064),	// SMAXVv4i16v
    UINT64_C(1320200192),	// SMAXVv4i32v
    UINT64_C(1316005888),	// SMAXVv8i16v
    UINT64_C(238069760),	// SMAXVv8i8v
    UINT64_C(297795584),	// SMAXWri
    UINT64_C(448815104),	// SMAXWrr
    UINT64_C(2445279232),	// SMAXXri
    UINT64_C(2596298752),	// SMAXXrr
    UINT64_C(3240144896),	// SMAX_VG2_2Z2Z_B
    UINT64_C(3252727808),	// SMAX_VG2_2Z2Z_D
    UINT64_C(3244339200),	// SMAX_VG2_2Z2Z_H
    UINT64_C(3248533504),	// SMAX_VG2_2Z2Z_S
    UINT64_C(3240140800),	// SMAX_VG2_2ZZ_B
    UINT64_C(3252723712),	// SMAX_VG2_2ZZ_D
    UINT64_C(3244335104),	// SMAX_VG2_2ZZ_H
    UINT64_C(3248529408),	// SMAX_VG2_2ZZ_S
    UINT64_C(3240146944),	// SMAX_VG4_4Z4Z_B
    UINT64_C(3252729856),	// SMAX_VG4_4Z4Z_D
    UINT64_C(3244341248),	// SMAX_VG4_4Z4Z_H
    UINT64_C(3248535552),	// SMAX_VG4_4Z4Z_S
    UINT64_C(3240142848),	// SMAX_VG4_4ZZ_B
    UINT64_C(3252725760),	// SMAX_VG4_4ZZ_D
    UINT64_C(3244337152),	// SMAX_VG4_4ZZ_H
    UINT64_C(3248531456),	// SMAX_VG4_4ZZ_S
    UINT64_C(623427584),	// SMAX_ZI_B
    UINT64_C(636010496),	// SMAX_ZI_D
    UINT64_C(627621888),	// SMAX_ZI_H
    UINT64_C(631816192),	// SMAX_ZI_S
    UINT64_C(67633152),	// SMAX_ZPmZ_B
    UINT64_C(80216064),	// SMAX_ZPmZ_D
    UINT64_C(71827456),	// SMAX_ZPmZ_H
    UINT64_C(76021760),	// SMAX_ZPmZ_S
    UINT64_C(1310745600),	// SMAXv16i8
    UINT64_C(245392384),	// SMAXv2i32
    UINT64_C(241198080),	// SMAXv4i16
    UINT64_C(1319134208),	// SMAXv4i32
    UINT64_C(1314939904),	// SMAXv8i16
    UINT64_C(237003776),	// SMAXv8i8
    UINT64_C(3556769795),	// SMC
    UINT64_C(1142333440),	// SMINP_ZPmZ_B
    UINT64_C(1154916352),	// SMINP_ZPmZ_D
    UINT64_C(1146527744),	// SMINP_ZPmZ_H
    UINT64_C(1150722048),	// SMINP_ZPmZ_S
    UINT64_C(1310764032),	// SMINPv16i8
    UINT64_C(245410816),	// SMINPv2i32
    UINT64_C(241216512),	// SMINPv4i16
    UINT64_C(1319152640),	// SMINPv4i32
    UINT64_C(1314958336),	// SMINPv8i16
    UINT64_C(237022208),	// SMINPv8i8
    UINT64_C(68034560),	// SMINQV_VPZ_B
    UINT64_C(80617472),	// SMINQV_VPZ_D
    UINT64_C(72228864),	// SMINQV_VPZ_H
    UINT64_C(76423168),	// SMINQV_VPZ_S
    UINT64_C(67772416),	// SMINV_VPZ_B
    UINT64_C(80355328),	// SMINV_VPZ_D
    UINT64_C(71966720),	// SMINV_VPZ_H
    UINT64_C(76161024),	// SMINV_VPZ_S
    UINT64_C(1311877120),	// SMINVv16i8v
    UINT64_C(242329600),	// SMINVv4i16v
    UINT64_C(1320265728),	// SMINVv4i32v
    UINT64_C(1316071424),	// SMINVv8i16v
    UINT64_C(238135296),	// SMINVv8i8v
    UINT64_C(298319872),	// SMINWri
    UINT64_C(448817152),	// SMINWrr
    UINT64_C(2445803520),	// SMINXri
    UINT64_C(2596300800),	// SMINXrr
    UINT64_C(3240144928),	// SMIN_VG2_2Z2Z_B
    UINT64_C(3252727840),	// SMIN_VG2_2Z2Z_D
    UINT64_C(3244339232),	// SMIN_VG2_2Z2Z_H
    UINT64_C(3248533536),	// SMIN_VG2_2Z2Z_S
    UINT64_C(3240140832),	// SMIN_VG2_2ZZ_B
    UINT64_C(3252723744),	// SMIN_VG2_2ZZ_D
    UINT64_C(3244335136),	// SMIN_VG2_2ZZ_H
    UINT64_C(3248529440),	// SMIN_VG2_2ZZ_S
    UINT64_C(3240146976),	// SMIN_VG4_4Z4Z_B
    UINT64_C(3252729888),	// SMIN_VG4_4Z4Z_D
    UINT64_C(3244341280),	// SMIN_VG4_4Z4Z_H
    UINT64_C(3248535584),	// SMIN_VG4_4Z4Z_S
    UINT64_C(3240142880),	// SMIN_VG4_4ZZ_B
    UINT64_C(3252725792),	// SMIN_VG4_4ZZ_D
    UINT64_C(3244337184),	// SMIN_VG4_4ZZ_H
    UINT64_C(3248531488),	// SMIN_VG4_4ZZ_S
    UINT64_C(623558656),	// SMIN_ZI_B
    UINT64_C(636141568),	// SMIN_ZI_D
    UINT64_C(627752960),	// SMIN_ZI_H
    UINT64_C(631947264),	// SMIN_ZI_S
    UINT64_C(67764224),	// SMIN_ZPmZ_B
    UINT64_C(80347136),	// SMIN_ZPmZ_D
    UINT64_C(71958528),	// SMIN_ZPmZ_H
    UINT64_C(76152832),	// SMIN_ZPmZ_S
    UINT64_C(1310747648),	// SMINv16i8
    UINT64_C(245394432),	// SMINv2i32
    UINT64_C(241200128),	// SMINv4i16
    UINT64_C(1319136256),	// SMINv4i32
    UINT64_C(1314941952),	// SMINv8i16
    UINT64_C(237005824),	// SMINv8i8
    UINT64_C(1155563520),	// SMLALB_ZZZI_D
    UINT64_C(1151369216),	// SMLALB_ZZZI_S
    UINT64_C(1153449984),	// SMLALB_ZZZ_D
    UINT64_C(1145061376),	// SMLALB_ZZZ_H
    UINT64_C(1149255680),	// SMLALB_ZZZ_S
    UINT64_C(3238002688),	// SMLALL_MZZI_BtoS
    UINT64_C(3246391296),	// SMLALL_MZZI_HtoD
    UINT64_C(3240100864),	// SMLALL_MZZ_BtoS
    UINT64_C(3244295168),	// SMLALL_MZZ_HtoD
    UINT64_C(3248488448),	// SMLALL_VG2_M2Z2Z_BtoS
    UINT64_C(3252682752),	// SMLALL_VG2_M2Z2Z_HtoD
    UINT64_C(3239051264),	// SMLALL_VG2_M2ZZI_BtoS
    UINT64_C(3247439872),	// SMLALL_VG2_M2ZZI_HtoD
    UINT64_C(3240099840),	// SMLALL_VG2_M2ZZ_BtoS
    UINT64_C(3244294144),	// SMLALL_VG2_M2ZZ_HtoD
    UINT64_C(3248553984),	// SMLALL_VG4_M4Z4Z_BtoS
    UINT64_C(3252748288),	// SMLALL_VG4_M4Z4Z_HtoD
    UINT64_C(3239084032),	// SMLALL_VG4_M4ZZI_BtoS
    UINT64_C(3247472640),	// SMLALL_VG4_M4ZZI_HtoD
    UINT64_C(3241148416),	// SMLALL_VG4_M4ZZ_BtoS
    UINT64_C(3245342720),	// SMLALL_VG4_M4ZZ_HtoD
    UINT64_C(1155564544),	// SMLALT_ZZZI_D
    UINT64_C(1151370240),	// SMLALT_ZZZI_S
    UINT64_C(1153451008),	// SMLALT_ZZZ_D
    UINT64_C(1145062400),	// SMLALT_ZZZ_H
    UINT64_C(1149256704),	// SMLALT_ZZZ_S
    UINT64_C(3250589696),	// SMLAL_MZZI_HtoS
    UINT64_C(3244297216),	// SMLAL_MZZ_HtoS
    UINT64_C(3252684800),	// SMLAL_VG2_M2Z2Z_HtoS
    UINT64_C(3251638272),	// SMLAL_VG2_M2ZZI_S
    UINT64_C(3244296192),	// SMLAL_VG2_M2ZZ_HtoS
    UINT64_C(3252750336),	// SMLAL_VG4_M4Z4Z_HtoS
    UINT64_C(3251671040),	// SMLAL_VG4_M4ZZI_HtoS
    UINT64_C(3245344768),	// SMLAL_VG4_M4ZZ_HtoS
    UINT64_C(1310752768),	// SMLALv16i8_v8i16
    UINT64_C(260055040),	// SMLALv2i32_indexed
    UINT64_C(245399552),	// SMLALv2i32_v2i64
    UINT64_C(255860736),	// SMLALv4i16_indexed
    UINT64_C(241205248),	// SMLALv4i16_v4i32
    UINT64_C(1333796864),	// SMLALv4i32_indexed
    UINT64_C(1319141376),	// SMLALv4i32_v2i64
    UINT64_C(1329602560),	// SMLALv8i16_indexed
    UINT64_C(1314947072),	// SMLALv8i16_v4i32
    UINT64_C(237010944),	// SMLALv8i8_v8i16
    UINT64_C(1155571712),	// SMLSLB_ZZZI_D
    UINT64_C(1151377408),	// SMLSLB_ZZZI_S
    UINT64_C(1153454080),	// SMLSLB_ZZZ_D
    UINT64_C(1145065472),	// SMLSLB_ZZZ_H
    UINT64_C(1149259776),	// SMLSLB_ZZZ_S
    UINT64_C(3238002696),	// SMLSLL_MZZI_BtoS
    UINT64_C(3246391304),	// SMLSLL_MZZI_HtoD
    UINT64_C(3240100872),	// SMLSLL_MZZ_BtoS
    UINT64_C(3244295176),	// SMLSLL_MZZ_HtoD
    UINT64_C(3248488456),	// SMLSLL_VG2_M2Z2Z_BtoS
    UINT64_C(3252682760),	// SMLSLL_VG2_M2Z2Z_HtoD
    UINT64_C(3239051272),	// SMLSLL_VG2_M2ZZI_BtoS
    UINT64_C(3247439880),	// SMLSLL_VG2_M2ZZI_HtoD
    UINT64_C(3240099848),	// SMLSLL_VG2_M2ZZ_BtoS
    UINT64_C(3244294152),	// SMLSLL_VG2_M2ZZ_HtoD
    UINT64_C(3248553992),	// SMLSLL_VG4_M4Z4Z_BtoS
    UINT64_C(3252748296),	// SMLSLL_VG4_M4Z4Z_HtoD
    UINT64_C(3239084040),	// SMLSLL_VG4_M4ZZI_BtoS
    UINT64_C(3247472648),	// SMLSLL_VG4_M4ZZI_HtoD
    UINT64_C(3241148424),	// SMLSLL_VG4_M4ZZ_BtoS
    UINT64_C(3245342728),	// SMLSLL_VG4_M4ZZ_HtoD
    UINT64_C(1155572736),	// SMLSLT_ZZZI_D
    UINT64_C(1151378432),	// SMLSLT_ZZZI_S
    UINT64_C(1153455104),	// SMLSLT_ZZZ_D
    UINT64_C(1145066496),	// SMLSLT_ZZZ_H
    UINT64_C(1149260800),	// SMLSLT_ZZZ_S
    UINT64_C(3250589704),	// SMLSL_MZZI_HtoS
    UINT64_C(3244297224),	// SMLSL_MZZ_HtoS
    UINT64_C(3252684808),	// SMLSL_VG2_M2Z2Z_HtoS
    UINT64_C(3251638280),	// SMLSL_VG2_M2ZZI_S
    UINT64_C(3244296200),	// SMLSL_VG2_M2ZZ_HtoS
    UINT64_C(3252750344),	// SMLSL_VG4_M4Z4Z_HtoS
    UINT64_C(3251671048),	// SMLSL_VG4_M4ZZI_HtoS
    UINT64_C(3245344776),	// SMLSL_VG4_M4ZZ_HtoS
    UINT64_C(1310760960),	// SMLSLv16i8_v8i16
    UINT64_C(260071424),	// SMLSLv2i32_indexed
    UINT64_C(245407744),	// SMLSLv2i32_v2i64
    UINT64_C(255877120),	// SMLSLv4i16_indexed
    UINT64_C(241213440),	// SMLSLv4i16_v4i32
    UINT64_C(1333813248),	// SMLSLv4i32_indexed
    UINT64_C(1319149568),	// SMLSLv4i32_v2i64
    UINT64_C(1329618944),	// SMLSLv8i16_indexed
    UINT64_C(1314955264),	// SMLSLv8i16_v4i32
    UINT64_C(237019136),	// SMLSLv8i8_v8i16
    UINT64_C(1317053440),	// SMMLA
    UINT64_C(1157666816),	// SMMLA_ZZZ
    UINT64_C(2148565504),	// SMOP4A_M2Z2Z_BToS
    UINT64_C(2148565512),	// SMOP4A_M2Z2Z_HToS
    UINT64_C(2697986568),	// SMOP4A_M2Z2Z_HtoD
    UINT64_C(2147516928),	// SMOP4A_M2ZZ_BToS
    UINT64_C(2147516936),	// SMOP4A_M2ZZ_HToS
    UINT64_C(2696937992),	// SMOP4A_M2ZZ_HtoD
    UINT64_C(2148564992),	// SMOP4A_MZ2Z_BToS
    UINT64_C(2148565000),	// SMOP4A_MZ2Z_HToS
    UINT64_C(2697986056),	// SMOP4A_MZ2Z_HtoD
    UINT64_C(2147516416),	// SMOP4A_MZZ_BToS
    UINT64_C(2147516424),	// SMOP4A_MZZ_HToS
    UINT64_C(2696937480),	// SMOP4A_MZZ_HtoD
    UINT64_C(2148565520),	// SMOP4S_M2Z2Z_BToS
    UINT64_C(2148565528),	// SMOP4S_M2Z2Z_HToS
    UINT64_C(2697986584),	// SMOP4S_M2Z2Z_HtoD
    UINT64_C(2147516944),	// SMOP4S_M2ZZ_BToS
    UINT64_C(2147516952),	// SMOP4S_M2ZZ_HToS
    UINT64_C(2696938008),	// SMOP4S_M2ZZ_HtoD
    UINT64_C(2148565008),	// SMOP4S_MZ2Z_BToS
    UINT64_C(2148565016),	// SMOP4S_MZ2Z_HToS
    UINT64_C(2697986072),	// SMOP4S_MZ2Z_HtoD
    UINT64_C(2147516432),	// SMOP4S_MZZ_BToS
    UINT64_C(2147516440),	// SMOP4S_MZZ_HToS
    UINT64_C(2696937496),	// SMOP4S_MZZ_HtoD
    UINT64_C(2696937472),	// SMOPA_MPPZZ_D
    UINT64_C(2692743176),	// SMOPA_MPPZZ_HtoS
    UINT64_C(2692743168),	// SMOPA_MPPZZ_S
    UINT64_C(2696937488),	// SMOPS_MPPZZ_D
    UINT64_C(2692743192),	// SMOPS_MPPZZ_HtoS
    UINT64_C(2692743184),	// SMOPS_MPPZZ_S
    UINT64_C(235023360),	// SMOVvi16to32
    UINT64_C(235023360),	// SMOVvi16to32_idx0
    UINT64_C(1308765184),	// SMOVvi16to64
    UINT64_C(1308765184),	// SMOVvi16to64_idx0
    UINT64_C(1308896256),	// SMOVvi32to64
    UINT64_C(1308896256),	// SMOVvi32to64_idx0
    UINT64_C(234957824),	// SMOVvi8to32
    UINT64_C(234957824),	// SMOVvi8to32_idx0
    UINT64_C(1308699648),	// SMOVvi8to64
    UINT64_C(1308699648),	// SMOVvi8to64_idx0
    UINT64_C(2602598400),	// SMSUBLrrr
    UINT64_C(68288512),	// SMULH_ZPmZ_B
    UINT64_C(80871424),	// SMULH_ZPmZ_D
    UINT64_C(72482816),	// SMULH_ZPmZ_H
    UINT64_C(76677120),	// SMULH_ZPmZ_S
    UINT64_C(69232640),	// SMULH_ZZZ_B
    UINT64_C(81815552),	// SMULH_ZZZ_D
    UINT64_C(73426944),	// SMULH_ZZZ_H
    UINT64_C(77621248),	// SMULH_ZZZ_S
    UINT64_C(2604694528),	// SMULHrr
    UINT64_C(1155579904),	// SMULLB_ZZZI_D
    UINT64_C(1151385600),	// SMULLB_ZZZI_S
    UINT64_C(1170239488),	// SMULLB_ZZZ_D
    UINT64_C(1161850880),	// SMULLB_ZZZ_H
    UINT64_C(1166045184),	// SMULLB_ZZZ_S
    UINT64_C(1155580928),	// SMULLT_ZZZI_D
    UINT64_C(1151386624),	// SMULLT_ZZZI_S
    UINT64_C(1170240512),	// SMULLT_ZZZ_D
    UINT64_C(1161851904),	// SMULLT_ZZZ_H
    UINT64_C(1166046208),	// SMULLT_ZZZ_S
    UINT64_C(1310769152),	// SMULLv16i8_v8i16
    UINT64_C(260087808),	// SMULLv2i32_indexed
    UINT64_C(245415936),	// SMULLv2i32_v2i64
    UINT64_C(255893504),	// SMULLv4i16_indexed
    UINT64_C(241221632),	// SMULLv4i16_v4i32
    UINT64_C(1333829632),	// SMULLv4i32_indexed
    UINT64_C(1319157760),	// SMULLv4i32_v2i64
    UINT64_C(1329635328),	// SMULLv8i16_indexed
    UINT64_C(1314963456),	// SMULLv8i16_v4i32
    UINT64_C(237027328),	// SMULLv8i8_v8i16
    UINT64_C(86867968),	// SPLICE_ZPZZ_B
    UINT64_C(99450880),	// SPLICE_ZPZZ_D
    UINT64_C(91062272),	// SPLICE_ZPZZ_H
    UINT64_C(95256576),	// SPLICE_ZPZZ_S
    UINT64_C(86802432),	// SPLICE_ZPZ_B
    UINT64_C(99385344),	// SPLICE_ZPZ_D
    UINT64_C(90996736),	// SPLICE_ZPZ_H
    UINT64_C(95191040),	// SPLICE_ZPZ_S
    UINT64_C(1141415936),	// SQABS_ZPmZ_B
    UINT64_C(1153998848),	// SQABS_ZPmZ_D
    UINT64_C(1145610240),	// SQABS_ZPmZ_H
    UINT64_C(1149804544),	// SQABS_ZPmZ_S
    UINT64_C(1141547008),	// SQABS_ZPzZ_B
    UINT64_C(1154129920),	// SQABS_ZPzZ_D
    UINT64_C(1145741312),	// SQABS_ZPzZ_H
    UINT64_C(1149935616),	// SQABS_ZPzZ_S
    UINT64_C(1310750720),	// SQABSv16i8
    UINT64_C(1583380480),	// SQABSv1i16
    UINT64_C(1587574784),	// SQABSv1i32
    UINT64_C(1591769088),	// SQABSv1i64
    UINT64_C(1579186176),	// SQABSv1i8
    UINT64_C(245397504),	// SQABSv2i32
    UINT64_C(1323333632),	// SQABSv2i64
    UINT64_C(241203200),	// SQABSv4i16
    UINT64_C(1319139328),	// SQABSv4i32
    UINT64_C(1314945024),	// SQABSv8i16
    UINT64_C(237008896),	// SQABSv8i8
    UINT64_C(623165440),	// SQADD_ZI_B
    UINT64_C(635748352),	// SQADD_ZI_D
    UINT64_C(627359744),	// SQADD_ZI_H
    UINT64_C(631554048),	// SQADD_ZI_S
    UINT64_C(1142456320),	// SQADD_ZPmZ_B
    UINT64_C(1155039232),	// SQADD_ZPmZ_D
    UINT64_C(1146650624),	// SQADD_ZPmZ_H
    UINT64_C(1150844928),	// SQADD_ZPmZ_S
    UINT64_C(69210112),	// SQADD_ZZZ_B
    UINT64_C(81793024),	// SQADD_ZZZ_D
    UINT64_C(73404416),	// SQADD_ZZZ_H
    UINT64_C(77598720),	// SQADD_ZZZ_S
    UINT64_C(1310723072),	// SQADDv16i8
    UINT64_C(1583352832),	// SQADDv1i16
    UINT64_C(1587547136),	// SQADDv1i32
    UINT64_C(1591741440),	// SQADDv1i64
    UINT64_C(1579158528),	// SQADDv1i8
    UINT64_C(245369856),	// SQADDv2i32
    UINT64_C(1323305984),	// SQADDv2i64
    UINT64_C(241175552),	// SQADDv4i16
    UINT64_C(1319111680),	// SQADDv4i32
    UINT64_C(1314917376),	// SQADDv8i16
    UINT64_C(236981248),	// SQADDv8i8
    UINT64_C(1157748736),	// SQCADD_ZZI_B
    UINT64_C(1170331648),	// SQCADD_ZZI_D
    UINT64_C(1161943040),	// SQCADD_ZZI_H
    UINT64_C(1166137344),	// SQCADD_ZZI_S
    UINT64_C(1160855552),	// SQCVTN_Z2Z_StoH
    UINT64_C(3249791040),	// SQCVTN_Z4Z_DtoH
    UINT64_C(3241402432),	// SQCVTN_Z4Z_StoB
    UINT64_C(1160859648),	// SQCVTUN_Z2Z_StoH
    UINT64_C(3253985344),	// SQCVTUN_Z4Z_DtoH
    UINT64_C(3245596736),	// SQCVTUN_Z4Z_StoB
    UINT64_C(3244548096),	// SQCVTU_Z2Z_StoH
    UINT64_C(3253985280),	// SQCVTU_Z4Z_DtoH
    UINT64_C(3245596672),	// SQCVTU_Z4Z_StoB
    UINT64_C(3240353792),	// SQCVT_Z2Z_StoH
    UINT64_C(3249790976),	// SQCVT_Z4Z_DtoH
    UINT64_C(3241402368),	// SQCVT_Z4Z_StoB
    UINT64_C(70318080),	// SQDECB_XPiI
    UINT64_C(69269504),	// SQDECB_XPiWdI
    UINT64_C(82900992),	// SQDECD_XPiI
    UINT64_C(81852416),	// SQDECD_XPiWdI
    UINT64_C(81840128),	// SQDECD_ZPiI
    UINT64_C(74512384),	// SQDECH_XPiI
    UINT64_C(73463808),	// SQDECH_XPiWdI
    UINT64_C(73451520),	// SQDECH_ZPiI
    UINT64_C(623544320),	// SQDECP_XPWd_B
    UINT64_C(636127232),	// SQDECP_XPWd_D
    UINT64_C(627738624),	// SQDECP_XPWd_H
    UINT64_C(631932928),	// SQDECP_XPWd_S
    UINT64_C(623545344),	// SQDECP_XP_B
    UINT64_C(636128256),	// SQDECP_XP_D
    UINT64_C(627739648),	// SQDECP_XP_H
    UINT64_C(631933952),	// SQDECP_XP_S
    UINT64_C(636125184),	// SQDECP_ZP_D
    UINT64_C(627736576),	// SQDECP_ZP_H
    UINT64_C(631930880),	// SQDECP_ZP_S
    UINT64_C(78706688),	// SQDECW_XPiI
    UINT64_C(77658112),	// SQDECW_XPiWdI
    UINT64_C(77645824),	// SQDECW_ZPiI
    UINT64_C(1153435648),	// SQDMLALBT_ZZZ_D
    UINT64_C(1145047040),	// SQDMLALBT_ZZZ_H
    UINT64_C(1149241344),	// SQDMLALBT_ZZZ_S
    UINT64_C(1155538944),	// SQDMLALB_ZZZI_D
    UINT64_C(1151344640),	// SQDMLALB_ZZZI_S
    UINT64_C(1153458176),	// SQDMLALB_ZZZ_D
    UINT64_C(1145069568),	// SQDMLALB_ZZZ_H
    UINT64_C(1149263872),	// SQDMLALB_ZZZ_S
    UINT64_C(1155539968),	// SQDMLALT_ZZZI_D
    UINT64_C(1151345664),	// SQDMLALT_ZZZI_S
    UINT64_C(1153459200),	// SQDMLALT_ZZZ_D
    UINT64_C(1145070592),	// SQDMLALT_ZZZ_H
    UINT64_C(1149264896),	// SQDMLALT_ZZZ_S
    UINT64_C(1583386624),	// SQDMLALi16
    UINT64_C(1587580928),	// SQDMLALi32
    UINT64_C(1598042112),	// SQDMLALv1i32_indexed
    UINT64_C(1602236416),	// SQDMLALv1i64_indexed
    UINT64_C(260059136),	// SQDMLALv2i32_indexed
    UINT64_C(245403648),	// SQDMLALv2i32_v2i64
    UINT64_C(255864832),	// SQDMLALv4i16_indexed
    UINT64_C(241209344),	// SQDMLALv4i16_v4i32
    UINT64_C(1333800960),	// SQDMLALv4i32_indexed
    UINT64_C(1319145472),	// SQDMLALv4i32_v2i64
    UINT64_C(1329606656),	// SQDMLALv8i16_indexed
    UINT64_C(1314951168),	// SQDMLALv8i16_v4i32
    UINT64_C(1153436672),	// SQDMLSLBT_ZZZ_D
    UINT64_C(1145048064),	// SQDMLSLBT_ZZZ_H
    UINT64_C(1149242368),	// SQDMLSLBT_ZZZ_S
    UINT64_C(1155543040),	// SQDMLSLB_ZZZI_D
    UINT64_C(1151348736),	// SQDMLSLB_ZZZI_S
    UINT64_C(1153460224),	// SQDMLSLB_ZZZ_D
    UINT64_C(1145071616),	// SQDMLSLB_ZZZ_H
    UINT64_C(1149265920),	// SQDMLSLB_ZZZ_S
    UINT64_C(1155544064),	// SQDMLSLT_ZZZI_D
    UINT64_C(1151349760),	// SQDMLSLT_ZZZI_S
    UINT64_C(1153461248),	// SQDMLSLT_ZZZ_D
    UINT64_C(1145072640),	// SQDMLSLT_ZZZ_H
    UINT64_C(1149266944),	// SQDMLSLT_ZZZ_S
    UINT64_C(1583394816),	// SQDMLSLi16
    UINT64_C(1587589120),	// SQDMLSLi32
    UINT64_C(1598058496),	// SQDMLSLv1i32_indexed
    UINT64_C(1602252800),	// SQDMLSLv1i64_indexed
    UINT64_C(260075520),	// SQDMLSLv2i32_indexed
    UINT64_C(245411840),	// SQDMLSLv2i32_v2i64
    UINT64_C(255881216),	// SQDMLSLv4i16_indexed
    UINT64_C(241217536),	// SQDMLSLv4i16_v4i32
    UINT64_C(1333817344),	// SQDMLSLv4i32_indexed
    UINT64_C(1319153664),	// SQDMLSLv4i32_v2i64
    UINT64_C(1329623040),	// SQDMLSLv8i16_indexed
    UINT64_C(1314959360),	// SQDMLSLv8i16_v4i32
    UINT64_C(3240145920),	// SQDMULH_VG2_2Z2Z_B
    UINT64_C(3252728832),	// SQDMULH_VG2_2Z2Z_D
    UINT64_C(3244340224),	// SQDMULH_VG2_2Z2Z_H
    UINT64_C(3248534528),	// SQDMULH_VG2_2Z2Z_S
    UINT64_C(3240141824),	// SQDMULH_VG2_2ZZ_B
    UINT64_C(3252724736),	// SQDMULH_VG2_2ZZ_D
    UINT64_C(3244336128),	// SQDMULH_VG2_2ZZ_H
    UINT64_C(3248530432),	// SQDMULH_VG2_2ZZ_S
    UINT64_C(3240147968),	// SQDMULH_VG4_4Z4Z_B
    UINT64_C(3252730880),	// SQDMULH_VG4_4Z4Z_D
    UINT64_C(3244342272),	// SQDMULH_VG4_4Z4Z_H
    UINT64_C(3248536576),	// SQDMULH_VG4_4Z4Z_S
    UINT64_C(3240143872),	// SQDMULH_VG4_4ZZ_B
    UINT64_C(3252726784),	// SQDMULH_VG4_4ZZ_D
    UINT64_C(3244338176),	// SQDMULH_VG4_4ZZ_H
    UINT64_C(3248532480),	// SQDMULH_VG4_4ZZ_S
    UINT64_C(1155592192),	// SQDMULH_ZZZI_D
    UINT64_C(1143009280),	// SQDMULH_ZZZI_H
    UINT64_C(1151397888),	// SQDMULH_ZZZI_S
    UINT64_C(69234688),	// SQDMULH_ZZZ_B
    UINT64_C(81817600),	// SQDMULH_ZZZ_D
    UINT64_C(73428992),	// SQDMULH_ZZZ_H
    UINT64_C(77623296),	// SQDMULH_ZZZ_S
    UINT64_C(1583395840),	// SQDMULHv1i16
    UINT64_C(1598078976),	// SQDMULHv1i16_indexed
    UINT64_C(1587590144),	// SQDMULHv1i32
    UINT64_C(1602273280),	// SQDMULHv1i32_indexed
    UINT64_C(245412864),	// SQDMULHv2i32
    UINT64_C(260096000),	// SQDMULHv2i32_indexed
    UINT64_C(241218560),	// SQDMULHv4i16
    UINT64_C(255901696),	// SQDMULHv4i16_indexed
    UINT64_C(1319154688),	// SQDMULHv4i32
    UINT64_C(1333837824),	// SQDMULHv4i32_indexed
    UINT64_C(1314960384),	// SQDMULHv8i16
    UINT64_C(1329643520),	// SQDMULHv8i16_indexed
    UINT64_C(1155588096),	// SQDMULLB_ZZZI_D
    UINT64_C(1151393792),	// SQDMULLB_ZZZI_S
    UINT64_C(1170235392),	// SQDMULLB_ZZZ_D
    UINT64_C(1161846784),	// SQDMULLB_ZZZ_H
    UINT64_C(1166041088),	// SQDMULLB_ZZZ_S
    UINT64_C(1155589120),	// SQDMULLT_ZZZI_D
    UINT64_C(1151394816),	// SQDMULLT_ZZZI_S
    UINT64_C(1170236416),	// SQDMULLT_ZZZ_D
    UINT64_C(1161847808),	// SQDMULLT_ZZZ_H
    UINT64_C(1166042112),	// SQDMULLT_ZZZ_S
    UINT64_C(1583403008),	// SQDMULLi16
    UINT64_C(1587597312),	// SQDMULLi32
    UINT64_C(1598074880),	// SQDMULLv1i32_indexed
    UINT64_C(1602269184),	// SQDMULLv1i64_indexed
    UINT64_C(260091904),	// SQDMULLv2i32_indexed
    UINT64_C(245420032),	// SQDMULLv2i32_v2i64
    UINT64_C(255897600),	// SQDMULLv4i16_indexed
    UINT64_C(241225728),	// SQDMULLv4i16_v4i32
    UINT64_C(1333833728),	// SQDMULLv4i32_indexed
    UINT64_C(1319161856),	// SQDMULLv4i32_v2i64
    UINT64_C(1329639424),	// SQDMULLv8i16_indexed
    UINT64_C(1314967552),	// SQDMULLv8i16_v4i32
    UINT64_C(70316032),	// SQINCB_XPiI
    UINT64_C(69267456),	// SQINCB_XPiWdI
    UINT64_C(82898944),	// SQINCD_XPiI
    UINT64_C(81850368),	// SQINCD_XPiWdI
    UINT64_C(81838080),	// SQINCD_ZPiI
    UINT64_C(74510336),	// SQINCH_XPiI
    UINT64_C(73461760),	// SQINCH_XPiWdI
    UINT64_C(73449472),	// SQINCH_ZPiI
    UINT64_C(623413248),	// SQINCP_XPWd_B
    UINT64_C(635996160),	// SQINCP_XPWd_D
    UINT64_C(627607552),	// SQINCP_XPWd_H
    UINT64_C(631801856),	// SQINCP_XPWd_S
    UINT64_C(623414272),	// SQINCP_XP_B
    UINT64_C(635997184),	// SQINCP_XP_D
    UINT64_C(627608576),	// SQINCP_XP_H
    UINT64_C(631802880),	// SQINCP_XP_S
    UINT64_C(635994112),	// SQINCP_ZP_D
    UINT64_C(627605504),	// SQINCP_ZP_H
    UINT64_C(631799808),	// SQINCP_ZP_S
    UINT64_C(78704640),	// SQINCW_XPiI
    UINT64_C(77656064),	// SQINCW_XPiWdI
    UINT64_C(77643776),	// SQINCW_ZPiI
    UINT64_C(1141481472),	// SQNEG_ZPmZ_B
    UINT64_C(1154064384),	// SQNEG_ZPmZ_D
    UINT64_C(1145675776),	// SQNEG_ZPmZ_H
    UINT64_C(1149870080),	// SQNEG_ZPmZ_S
    UINT64_C(1141612544),	// SQNEG_ZPzZ_B
    UINT64_C(1154195456),	// SQNEG_ZPzZ_D
    UINT64_C(1145806848),	// SQNEG_ZPzZ_H
    UINT64_C(1150001152),	// SQNEG_ZPzZ_S
    UINT64_C(1847621632),	// SQNEGv16i8
    UINT64_C(2120251392),	// SQNEGv1i16
    UINT64_C(2124445696),	// SQNEGv1i32
    UINT64_C(2128640000),	// SQNEGv1i64
    UINT64_C(2116057088),	// SQNEGv1i8
    UINT64_C(782268416),	// SQNEGv2i32
    UINT64_C(1860204544),	// SQNEGv2i64
    UINT64_C(778074112),	// SQNEGv4i16
    UINT64_C(1856010240),	// SQNEGv4i32
    UINT64_C(1851815936),	// SQNEGv8i16
    UINT64_C(773879808),	// SQNEGv8i8
    UINT64_C(1151365120),	// SQRDCMLAH_ZZZI_H
    UINT64_C(1155559424),	// SQRDCMLAH_ZZZI_S
    UINT64_C(1140862976),	// SQRDCMLAH_ZZZ_B
    UINT64_C(1153445888),	// SQRDCMLAH_ZZZ_D
    UINT64_C(1145057280),	// SQRDCMLAH_ZZZ_H
    UINT64_C(1149251584),	// SQRDCMLAH_ZZZ_S
    UINT64_C(1155534848),	// SQRDMLAH_ZZZI_D
    UINT64_C(1142951936),	// SQRDMLAH_ZZZI_H
    UINT64_C(1151340544),	// SQRDMLAH_ZZZI_S
    UINT64_C(1140879360),	// SQRDMLAH_ZZZ_B
    UINT64_C(1153462272),	// SQRDMLAH_ZZZ_D
    UINT64_C(1145073664),	// SQRDMLAH_ZZZ_H
    UINT64_C(1149267968),	// SQRDMLAH_ZZZ_S
    UINT64_C(2118157312),	// SQRDMLAHv1i16
    UINT64_C(2134953984),	// SQRDMLAHv1i16_indexed
    UINT64_C(2122351616),	// SQRDMLAHv1i32
    UINT64_C(2139148288),	// SQRDMLAHv1i32_indexed
    UINT64_C(780174336),	// SQRDMLAHv2i32
    UINT64_C(796971008),	// SQRDMLAHv2i32_indexed
    UINT64_C(775980032),	// SQRDMLAHv4i16
    UINT64_C(792776704),	// SQRDMLAHv4i16_indexed
    UINT64_C(1853916160),	// SQRDMLAHv4i32
    UINT64_C(1870712832),	// SQRDMLAHv4i32_indexed
    UINT64_C(1849721856),	// SQRDMLAHv8i16
    UINT64_C(1866518528),	// SQRDMLAHv8i16_indexed
    UINT64_C(1155535872),	// SQRDMLSH_ZZZI_D
    UINT64_C(1142952960),	// SQRDMLSH_ZZZI_H
    UINT64_C(1151341568),	// SQRDMLSH_ZZZI_S
    UINT64_C(1140880384),	// SQRDMLSH_ZZZ_B
    UINT64_C(1153463296),	// SQRDMLSH_ZZZ_D
    UINT64_C(1145074688),	// SQRDMLSH_ZZZ_H
    UINT64_C(1149268992),	// SQRDMLSH_ZZZ_S
    UINT64_C(2118159360),	// SQRDMLSHv1i16
    UINT64_C(2134962176),	// SQRDMLSHv1i16_indexed
    UINT64_C(2122353664),	// SQRDMLSHv1i32
    UINT64_C(2139156480),	// SQRDMLSHv1i32_indexed
    UINT64_C(780176384),	// SQRDMLSHv2i32
    UINT64_C(796979200),	// SQRDMLSHv2i32_indexed
    UINT64_C(775982080),	// SQRDMLSHv4i16
    UINT64_C(792784896),	// SQRDMLSHv4i16_indexed
    UINT64_C(1853918208),	// SQRDMLSHv4i32
    UINT64_C(1870721024),	// SQRDMLSHv4i32_indexed
    UINT64_C(1849723904),	// SQRDMLSHv8i16
    UINT64_C(1866526720),	// SQRDMLSHv8i16_indexed
    UINT64_C(1155593216),	// SQRDMULH_ZZZI_D
    UINT64_C(1143010304),	// SQRDMULH_ZZZI_H
    UINT64_C(1151398912),	// SQRDMULH_ZZZI_S
    UINT64_C(69235712),	// SQRDMULH_ZZZ_B
    UINT64_C(81818624),	// SQRDMULH_ZZZ_D
    UINT64_C(73430016),	// SQRDMULH_ZZZ_H
    UINT64_C(77624320),	// SQRDMULH_ZZZ_S
    UINT64_C(2120266752),	// SQRDMULHv1i16
    UINT64_C(1598083072),	// SQRDMULHv1i16_indexed
    UINT64_C(2124461056),	// SQRDMULHv1i32
    UINT64_C(1602277376),	// SQRDMULHv1i32_indexed
    UINT64_C(782283776),	// SQRDMULHv2i32
    UINT64_C(260100096),	// SQRDMULHv2i32_indexed
    UINT64_C(778089472),	// SQRDMULHv4i16
    UINT64_C(255905792),	// SQRDMULHv4i16_indexed
    UINT64_C(1856025600),	// SQRDMULHv4i32
    UINT64_C(1333841920),	// SQRDMULHv4i32_indexed
    UINT64_C(1851831296),	// SQRDMULHv8i16
    UINT64_C(1329647616),	// SQRDMULHv8i16_indexed
    UINT64_C(1141800960),	// SQRSHLR_ZPmZ_B
    UINT64_C(1154383872),	// SQRSHLR_ZPmZ_D
    UINT64_C(1145995264),	// SQRSHLR_ZPmZ_H
    UINT64_C(1150189568),	// SQRSHLR_ZPmZ_S
    UINT64_C(1141538816),	// SQRSHL_ZPmZ_B
    UINT64_C(1154121728),	// SQRSHL_ZPmZ_D
    UINT64_C(1145733120),	// SQRSHL_ZPmZ_H
    UINT64_C(1149927424),	// SQRSHL_ZPmZ_S
    UINT64_C(1310743552),	// SQRSHLv16i8
    UINT64_C(1583373312),	// SQRSHLv1i16
    UINT64_C(1587567616),	// SQRSHLv1i32
    UINT64_C(1591761920),	// SQRSHLv1i64
    UINT64_C(1579179008),	// SQRSHLv1i8
    UINT64_C(245390336),	// SQRSHLv2i32
    UINT64_C(1323326464),	// SQRSHLv2i64
    UINT64_C(241196032),	// SQRSHLv4i16
    UINT64_C(1319132160),	// SQRSHLv4i32
    UINT64_C(1314937856),	// SQRSHLv8i16
    UINT64_C(237001728),	// SQRSHLv8i8
    UINT64_C(1160259584),	// SQRSHRNB_ZZI_B
    UINT64_C(1160783872),	// SQRSHRNB_ZZI_H
    UINT64_C(1163929600),	// SQRSHRNB_ZZI_S
    UINT64_C(1160260608),	// SQRSHRNT_ZZI_B
    UINT64_C(1160784896),	// SQRSHRNT_ZZI_H
    UINT64_C(1163930624),	// SQRSHRNT_ZZI_S
    UINT64_C(3244350464),	// SQRSHRN_VG4_Z4ZI_B
    UINT64_C(3248544768),	// SQRSHRN_VG4_Z4ZI_H
    UINT64_C(1168648192),	// SQRSHRN_Z2ZI_HtoB
    UINT64_C(1169172480),	// SQRSHRN_Z2ZI_StoH
    UINT64_C(1594399744),	// SQRSHRNb
    UINT64_C(1594924032),	// SQRSHRNh
    UINT64_C(1595972608),	// SQRSHRNs
    UINT64_C(1325964288),	// SQRSHRNv16i8_shift
    UINT64_C(253795328),	// SQRSHRNv2i32_shift
    UINT64_C(252746752),	// SQRSHRNv4i16_shift
    UINT64_C(1327537152),	// SQRSHRNv4i32_shift
    UINT64_C(1326488576),	// SQRSHRNv8i16_shift
    UINT64_C(252222464),	// SQRSHRNv8i8_shift
    UINT64_C(1160251392),	// SQRSHRUNB_ZZI_B
    UINT64_C(1160775680),	// SQRSHRUNB_ZZI_H
    UINT64_C(1163921408),	// SQRSHRUNB_ZZI_S
    UINT64_C(1160252416),	// SQRSHRUNT_ZZI_B
    UINT64_C(1160776704),	// SQRSHRUNT_ZZI_H
    UINT64_C(1163922432),	// SQRSHRUNT_ZZI_S
    UINT64_C(3244350528),	// SQRSHRUN_VG4_Z4ZI_B
    UINT64_C(3248544832),	// SQRSHRUN_VG4_Z4ZI_H
    UINT64_C(1168640000),	// SQRSHRUN_Z2ZI_HtoB
    UINT64_C(1169164288),	// SQRSHRUN_Z2ZI_StoH
    UINT64_C(2131266560),	// SQRSHRUNb
    UINT64_C(2131790848),	// SQRSHRUNh
    UINT64_C(2132839424),	// SQRSHRUNs
    UINT64_C(1862831104),	// SQRSHRUNv16i8_shift
    UINT64_C(790662144),	// SQRSHRUNv2i32_shift
    UINT64_C(789613568),	// SQRSHRUNv4i16_shift
    UINT64_C(1864403968),	// SQRSHRUNv4i32_shift
    UINT64_C(1863355392),	// SQRSHRUNv8i16_shift
    UINT64_C(789089280),	// SQRSHRUNv8i8_shift
    UINT64_C(3253785600),	// SQRSHRU_VG2_Z2ZI_H
    UINT64_C(3244349504),	// SQRSHRU_VG4_Z4ZI_B
    UINT64_C(3248543808),	// SQRSHRU_VG4_Z4ZI_H
    UINT64_C(3252737024),	// SQRSHR_VG2_Z2ZI_H
    UINT64_C(3244349440),	// SQRSHR_VG4_Z4ZI_B
    UINT64_C(3248543744),	// SQRSHR_VG4_Z4ZI_H
    UINT64_C(1141669888),	// SQSHLR_ZPmZ_B
    UINT64_C(1154252800),	// SQSHLR_ZPmZ_D
    UINT64_C(1145864192),	// SQSHLR_ZPmZ_H
    UINT64_C(1150058496),	// SQSHLR_ZPmZ_S
    UINT64_C(68124928),	// SQSHLU_ZPmI_B
    UINT64_C(76513280),	// SQSHLU_ZPmI_D
    UINT64_C(68125184),	// SQSHLU_ZPmI_H
    UINT64_C(72318976),	// SQSHLU_ZPmI_S
    UINT64_C(2131256320),	// SQSHLUb
    UINT64_C(2134926336),	// SQSHLUd
    UINT64_C(2131780608),	// SQSHLUh
    UINT64_C(2132829184),	// SQSHLUs
    UINT64_C(1862820864),	// SQSHLUv16i8_shift
    UINT64_C(790651904),	// SQSHLUv2i32_shift
    UINT64_C(1866490880),	// SQSHLUv2i64_shift
    UINT64_C(789603328),	// SQSHLUv4i16_shift
    UINT64_C(1864393728),	// SQSHLUv4i32_shift
    UINT64_C(1863345152),	// SQSHLUv8i16_shift
    UINT64_C(789079040),	// SQSHLUv8i8_shift
    UINT64_C(67535104),	// SQSHL_ZPmI_B
    UINT64_C(75923456),	// SQSHL_ZPmI_D
    UINT64_C(67535360),	// SQSHL_ZPmI_H
    UINT64_C(71729152),	// SQSHL_ZPmI_S
    UINT64_C(1141407744),	// SQSHL_ZPmZ_B
    UINT64_C(1153990656),	// SQSHL_ZPmZ_D
    UINT64_C(1145602048),	// SQSHL_ZPmZ_H
    UINT64_C(1149796352),	// SQSHL_ZPmZ_S
    UINT64_C(1594389504),	// SQSHLb
    UINT64_C(1598059520),	// SQSHLd
    UINT64_C(1594913792),	// SQSHLh
    UINT64_C(1595962368),	// SQSHLs
    UINT64_C(1310739456),	// SQSHLv16i8
    UINT64_C(1325954048),	// SQSHLv16i8_shift
    UINT64_C(1583369216),	// SQSHLv1i16
    UINT64_C(1587563520),	// SQSHLv1i32
    UINT64_C(1591757824),	// SQSHLv1i64
    UINT64_C(1579174912),	// SQSHLv1i8
    UINT64_C(245386240),	// SQSHLv2i32
    UINT64_C(253785088),	// SQSHLv2i32_shift
    UINT64_C(1323322368),	// SQSHLv2i64
    UINT64_C(1329624064),	// SQSHLv2i64_shift
    UINT64_C(241191936),	// SQSHLv4i16
    UINT64_C(252736512),	// SQSHLv4i16_shift
    UINT64_C(1319128064),	// SQSHLv4i32
    UINT64_C(1327526912),	// SQSHLv4i32_shift
    UINT64_C(1314933760),	// SQSHLv8i16
    UINT64_C(1326478336),	// SQSHLv8i16_shift
    UINT64_C(236997632),	// SQSHLv8i8
    UINT64_C(252212224),	// SQSHLv8i8_shift
    UINT64_C(1160257536),	// SQSHRNB_ZZI_B
    UINT64_C(1160781824),	// SQSHRNB_ZZI_H
    UINT64_C(1163927552),	// SQSHRNB_ZZI_S
    UINT64_C(1160258560),	// SQSHRNT_ZZI_B
    UINT64_C(1160782848),	// SQSHRNT_ZZI_H
    UINT64_C(1163928576),	// SQSHRNT_ZZI_S
    UINT64_C(1168637952),	// SQSHRN_Z2ZI_HtoB
    UINT64_C(1169162240),	// SQSHRN_Z2ZI_StoH
    UINT64_C(1594397696),	// SQSHRNb
    UINT64_C(1594921984),	// SQSHRNh
    UINT64_C(1595970560),	// SQSHRNs
    UINT64_C(1325962240),	// SQSHRNv16i8_shift
    UINT64_C(253793280),	// SQSHRNv2i32_shift
    UINT64_C(252744704),	// SQSHRNv4i16_shift
    UINT64_C(1327535104),	// SQSHRNv4i32_shift
    UINT64_C(1326486528),	// SQSHRNv8i16_shift
    UINT64_C(252220416),	// SQSHRNv8i8_shift
    UINT64_C(1160249344),	// SQSHRUNB_ZZI_B
    UINT64_C(1160773632),	// SQSHRUNB_ZZI_H
    UINT64_C(1163919360),	// SQSHRUNB_ZZI_S
    UINT64_C(1160250368),	// SQSHRUNT_ZZI_B
    UINT64_C(1160774656),	// SQSHRUNT_ZZI_H
    UINT64_C(1163920384),	// SQSHRUNT_ZZI_S
    UINT64_C(1168646144),	// SQSHRUN_Z2ZI_HtoB
    UINT64_C(1169170432),	// SQSHRUN_Z2ZI_StoH
    UINT64_C(2131264512),	// SQSHRUNb
    UINT64_C(2131788800),	// SQSHRUNh
    UINT64_C(2132837376),	// SQSHRUNs
    UINT64_C(1862829056),	// SQSHRUNv16i8_shift
    UINT64_C(790660096),	// SQSHRUNv2i32_shift
    UINT64_C(789611520),	// SQSHRUNv4i16_shift
    UINT64_C(1864401920),	// SQSHRUNv4i32_shift
    UINT64_C(1863353344),	// SQSHRUNv8i16_shift
    UINT64_C(789087232),	// SQSHRUNv8i8_shift
    UINT64_C(1142849536),	// SQSUBR_ZPmZ_B
    UINT64_C(1155432448),	// SQSUBR_ZPmZ_D
    UINT64_C(1147043840),	// SQSUBR_ZPmZ_H
    UINT64_C(1151238144),	// SQSUBR_ZPmZ_S
    UINT64_C(623296512),	// SQSUB_ZI_B
    UINT64_C(635879424),	// SQSUB_ZI_D
    UINT64_C(627490816),	// SQSUB_ZI_H
    UINT64_C(631685120),	// SQSUB_ZI_S
    UINT64_C(1142587392),	// SQSUB_ZPmZ_B
    UINT64_C(1155170304),	// SQSUB_ZPmZ_D
    UINT64_C(1146781696),	// SQSUB_ZPmZ_H
    UINT64_C(1150976000),	// SQSUB_ZPmZ_S
    UINT64_C(69212160),	// SQSUB_ZZZ_B
    UINT64_C(81795072),	// SQSUB_ZZZ_D
    UINT64_C(73406464),	// SQSUB_ZZZ_H
    UINT64_C(77600768),	// SQSUB_ZZZ_S
    UINT64_C(1310731264),	// SQSUBv16i8
    UINT64_C(1583361024),	// SQSUBv1i16
    UINT64_C(1587555328),	// SQSUBv1i32
    UINT64_C(1591749632),	// SQSUBv1i64
    UINT64_C(1579166720),	// SQSUBv1i8
    UINT64_C(245378048),	// SQSUBv2i32
    UINT64_C(1323314176),	// SQSUBv2i64
    UINT64_C(241183744),	// SQSUBv4i16
    UINT64_C(1319119872),	// SQSUBv4i32
    UINT64_C(1314925568),	// SQSUBv8i16
    UINT64_C(236989440),	// SQSUBv8i8
    UINT64_C(1160265728),	// SQXTNB_ZZ_B
    UINT64_C(1160790016),	// SQXTNB_ZZ_H
    UINT64_C(1163935744),	// SQXTNB_ZZ_S
    UINT64_C(1160266752),	// SQXTNT_ZZ_B
    UINT64_C(1160791040),	// SQXTNT_ZZ_H
    UINT64_C(1163936768),	// SQXTNT_ZZ_S
    UINT64_C(1310803968),	// SQXTNv16i8
    UINT64_C(1583433728),	// SQXTNv1i16
    UINT64_C(1587628032),	// SQXTNv1i32
    UINT64_C(1579239424),	// SQXTNv1i8
    UINT64_C(245450752),	// SQXTNv2i32
    UINT64_C(241256448),	// SQXTNv4i16
    UINT64_C(1319192576),	// SQXTNv4i32
    UINT64_C(1314998272),	// SQXTNv8i16
    UINT64_C(237062144),	// SQXTNv8i8
    UINT64_C(1160269824),	// SQXTUNB_ZZ_B
    UINT64_C(1160794112),	// SQXTUNB_ZZ_H
    UINT64_C(1163939840),	// SQXTUNB_ZZ_S
    UINT64_C(1160270848),	// SQXTUNT_ZZ_B
    UINT64_C(1160795136),	// SQXTUNT_ZZ_H
    UINT64_C(1163940864),	// SQXTUNT_ZZ_S
    UINT64_C(1847666688),	// SQXTUNv16i8
    UINT64_C(2120296448),	// SQXTUNv1i16
    UINT64_C(2124490752),	// SQXTUNv1i32
    UINT64_C(2116102144),	// SQXTUNv1i8
    UINT64_C(782313472),	// SQXTUNv2i32
    UINT64_C(778119168),	// SQXTUNv4i16
    UINT64_C(1856055296),	// SQXTUNv4i32
    UINT64_C(1851860992),	// SQXTUNv8i16
    UINT64_C(773924864),	// SQXTUNv8i8
    UINT64_C(1142194176),	// SRHADD_ZPmZ_B
    UINT64_C(1154777088),	// SRHADD_ZPmZ_D
    UINT64_C(1146388480),	// SRHADD_ZPmZ_H
    UINT64_C(1150582784),	// SRHADD_ZPmZ_S
    UINT64_C(1310725120),	// SRHADDv16i8
    UINT64_C(245371904),	// SRHADDv2i32
    UINT64_C(241177600),	// SRHADDv4i16
    UINT64_C(1319113728),	// SRHADDv4i32
    UINT64_C(1314919424),	// SRHADDv8i16
    UINT64_C(236983296),	// SRHADDv8i8
    UINT64_C(1158213632),	// SRI_ZZI_B
    UINT64_C(1166077952),	// SRI_ZZI_D
    UINT64_C(1158737920),	// SRI_ZZI_H
    UINT64_C(1161883648),	// SRI_ZZI_S
    UINT64_C(2134918144),	// SRId
    UINT64_C(1862812672),	// SRIv16i8_shift
    UINT64_C(790643712),	// SRIv2i32_shift
    UINT64_C(1866482688),	// SRIv2i64_shift
    UINT64_C(789595136),	// SRIv4i16_shift
    UINT64_C(1864385536),	// SRIv4i32_shift
    UINT64_C(1863336960),	// SRIv8i16_shift
    UINT64_C(789070848),	// SRIv8i8_shift
    UINT64_C(1141276672),	// SRSHLR_ZPmZ_B
    UINT64_C(1153859584),	// SRSHLR_ZPmZ_D
    UINT64_C(1145470976),	// SRSHLR_ZPmZ_H
    UINT64_C(1149665280),	// SRSHLR_ZPmZ_S
    UINT64_C(3240145440),	// SRSHL_VG2_2Z2Z_B
    UINT64_C(3252728352),	// SRSHL_VG2_2Z2Z_D
    UINT64_C(3244339744),	// SRSHL_VG2_2Z2Z_H
    UINT64_C(3248534048),	// SRSHL_VG2_2Z2Z_S
    UINT64_C(3240141344),	// SRSHL_VG2_2ZZ_B
    UINT64_C(3252724256),	// SRSHL_VG2_2ZZ_D
    UINT64_C(3244335648),	// SRSHL_VG2_2ZZ_H
    UINT64_C(3248529952),	// SRSHL_VG2_2ZZ_S
    UINT64_C(3240147488),	// SRSHL_VG4_4Z4Z_B
    UINT64_C(3252730400),	// SRSHL_VG4_4Z4Z_D
    UINT64_C(3244341792),	// SRSHL_VG4_4Z4Z_H
    UINT64_C(3248536096),	// SRSHL_VG4_4Z4Z_S
    UINT64_C(3240143392),	// SRSHL_VG4_4ZZ_B
    UINT64_C(3252726304),	// SRSHL_VG4_4ZZ_D
    UINT64_C(3244337696),	// SRSHL_VG4_4ZZ_H
    UINT64_C(3248532000),	// SRSHL_VG4_4ZZ_S
    UINT64_C(1141014528),	// SRSHL_ZPmZ_B
    UINT64_C(1153597440),	// SRSHL_ZPmZ_D
    UINT64_C(1145208832),	// SRSHL_ZPmZ_H
    UINT64_C(1149403136),	// SRSHL_ZPmZ_S
    UINT64_C(1310741504),	// SRSHLv16i8
    UINT64_C(1591759872),	// SRSHLv1i64
    UINT64_C(245388288),	// SRSHLv2i32
    UINT64_C(1323324416),	// SRSHLv2i64
    UINT64_C(241193984),	// SRSHLv4i16
    UINT64_C(1319130112),	// SRSHLv4i32
    UINT64_C(1314935808),	// SRSHLv8i16
    UINT64_C(236999680),	// SRSHLv8i8
    UINT64_C(67928320),	// SRSHR_ZPmI_B
    UINT64_C(76316672),	// SRSHR_ZPmI_D
    UINT64_C(67928576),	// SRSHR_ZPmI_H
    UINT64_C(72122368),	// SRSHR_ZPmI_S
    UINT64_C(1598039040),	// SRSHRd
    UINT64_C(1325933568),	// SRSHRv16i8_shift
    UINT64_C(253764608),	// SRSHRv2i32_shift
    UINT64_C(1329603584),	// SRSHRv2i64_shift
    UINT64_C(252716032),	// SRSHRv4i16_shift
    UINT64_C(1327506432),	// SRSHRv4i32_shift
    UINT64_C(1326457856),	// SRSHRv8i16_shift
    UINT64_C(252191744),	// SRSHRv8i8_shift
    UINT64_C(1158211584),	// SRSRA_ZZI_B
    UINT64_C(1166075904),	// SRSRA_ZZI_D
    UINT64_C(1158735872),	// SRSRA_ZZI_H
    UINT64_C(1161881600),	// SRSRA_ZZI_S
    UINT64_C(1598043136),	// SRSRAd
    UINT64_C(1325937664),	// SRSRAv16i8_shift
    UINT64_C(253768704),	// SRSRAv2i32_shift
    UINT64_C(1329607680),	// SRSRAv2i64_shift
    UINT64_C(252720128),	// SRSRAv4i16_shift
    UINT64_C(1327510528),	// SRSRAv4i32_shift
    UINT64_C(1326461952),	// SRSRAv8i16_shift
    UINT64_C(252195840),	// SRSRAv8i8_shift
    UINT64_C(1161863168),	// SSHLLB_ZZI_D
    UINT64_C(1158193152),	// SSHLLB_ZZI_H
    UINT64_C(1158717440),	// SSHLLB_ZZI_S
    UINT64_C(1161864192),	// SSHLLT_ZZI_D
    UINT64_C(1158194176),	// SSHLLT_ZZI_H
    UINT64_C(1158718464),	// SSHLLT_ZZI_S
    UINT64_C(1325966336),	// SSHLLv16i8_shift
    UINT64_C(253797376),	// SSHLLv2i32_shift
    UINT64_C(252748800),	// SSHLLv4i16_shift
    UINT64_C(1327539200),	// SSHLLv4i32_shift
    UINT64_C(1326490624),	// SSHLLv8i16_shift
    UINT64_C(252224512),	// SSHLLv8i8_shift
    UINT64_C(1310737408),	// SSHLv16i8
    UINT64_C(1591755776),	// SSHLv1i64
    UINT64_C(245384192),	// SSHLv2i32
    UINT64_C(1323320320),	// SSHLv2i64
    UINT64_C(241189888),	// SSHLv4i16
    UINT64_C(1319126016),	// SSHLv4i32
    UINT64_C(1314931712),	// SSHLv8i16
    UINT64_C(236995584),	// SSHLv8i8
    UINT64_C(1598030848),	// SSHRd
    UINT64_C(1325925376),	// SSHRv16i8_shift
    UINT64_C(253756416),	// SSHRv2i32_shift
    UINT64_C(1329595392),	// SSHRv2i64_shift
    UINT64_C(252707840),	// SSHRv4i16_shift
    UINT64_C(1327498240),	// SSHRv4i32_shift
    UINT64_C(1326449664),	// SSHRv8i16_shift
    UINT64_C(252183552),	// SSHRv8i8_shift
    UINT64_C(1158209536),	// SSRA_ZZI_B
    UINT64_C(1166073856),	// SSRA_ZZI_D
    UINT64_C(1158733824),	// SSRA_ZZI_H
    UINT64_C(1161879552),	// SSRA_ZZI_S
    UINT64_C(1598034944),	// SSRAd
    UINT64_C(1325929472),	// SSRAv16i8_shift
    UINT64_C(253760512),	// SSRAv2i32_shift
    UINT64_C(1329599488),	// SSRAv2i64_shift
    UINT64_C(252711936),	// SSRAv4i16_shift
    UINT64_C(1327502336),	// SSRAv4i32_shift
    UINT64_C(1326453760),	// SSRAv8i16_shift
    UINT64_C(252187648),	// SSRAv8i8_shift
    UINT64_C(3825246208),	// SST1B_D
    UINT64_C(3829440512),	// SST1B_D_IMM
    UINT64_C(3825254400),	// SST1B_D_SXTW
    UINT64_C(3825238016),	// SST1B_D_UXTW
    UINT64_C(3831537664),	// SST1B_S_IMM
    UINT64_C(3829448704),	// SST1B_S_SXTW
    UINT64_C(3829432320),	// SST1B_S_UXTW
    UINT64_C(3850412032),	// SST1D
    UINT64_C(3854606336),	// SST1D_IMM
    UINT64_C(3852509184),	// SST1D_SCALED
    UINT64_C(3850420224),	// SST1D_SXTW
    UINT64_C(3852517376),	// SST1D_SXTW_SCALED
    UINT64_C(3850403840),	// SST1D_UXTW
    UINT64_C(3852500992),	// SST1D_UXTW_SCALED
    UINT64_C(3833634816),	// SST1H_D
    UINT64_C(3837829120),	// SST1H_D_IMM
    UINT64_C(3835731968),	// SST1H_D_SCALED
    UINT64_C(3833643008),	// SST1H_D_SXTW
    UINT64_C(3835740160),	// SST1H_D_SXTW_SCALED
    UINT64_C(3833626624),	// SST1H_D_UXTW
    UINT64_C(3835723776),	// SST1H_D_UXTW_SCALED
    UINT64_C(3839926272),	// SST1H_S_IMM
    UINT64_C(3837837312),	// SST1H_S_SXTW
    UINT64_C(3839934464),	// SST1H_S_SXTW_SCALED
    UINT64_C(3837820928),	// SST1H_S_UXTW
    UINT64_C(3839918080),	// SST1H_S_UXTW_SCALED
    UINT64_C(3827310592),	// SST1Q
    UINT64_C(3842023424),	// SST1W_D
    UINT64_C(3846217728),	// SST1W_D_IMM
    UINT64_C(3844120576),	// SST1W_D_SCALED
    UINT64_C(3842031616),	// SST1W_D_SXTW
    UINT64_C(3844128768),	// SST1W_D_SXTW_SCALED
    UINT64_C(3842015232),	// SST1W_D_UXTW
    UINT64_C(3844112384),	// SST1W_D_UXTW_SCALED
    UINT64_C(3848314880),	// SST1W_IMM
    UINT64_C(3846225920),	// SST1W_SXTW
    UINT64_C(3848323072),	// SST1W_SXTW_SCALED
    UINT64_C(3846209536),	// SST1W_UXTW
    UINT64_C(3848306688),	// SST1W_UXTW_SCALED
    UINT64_C(1170245632),	// SSUBLBT_ZZZ_D
    UINT64_C(1161857024),	// SSUBLBT_ZZZ_H
    UINT64_C(1166051328),	// SSUBLBT_ZZZ_S
    UINT64_C(1170214912),	// SSUBLB_ZZZ_D
    UINT64_C(1161826304),	// SSUBLB_ZZZ_H
    UINT64_C(1166020608),	// SSUBLB_ZZZ_S
    UINT64_C(1170246656),	// SSUBLTB_ZZZ_D
    UINT64_C(1161858048),	// SSUBLTB_ZZZ_H
    UINT64_C(1166052352),	// SSUBLTB_ZZZ_S
    UINT64_C(1170215936),	// SSUBLT_ZZZ_D
    UINT64_C(1161827328),	// SSUBLT_ZZZ_H
    UINT64_C(1166021632),	// SSUBLT_ZZZ_S
    UINT64_C(1310728192),	// SSUBLv16i8_v8i16
    UINT64_C(245374976),	// SSUBLv2i32_v2i64
    UINT64_C(241180672),	// SSUBLv4i16_v4i32
    UINT64_C(1319116800),	// SSUBLv4i32_v2i64
    UINT64_C(1314922496),	// SSUBLv8i16_v4i32
    UINT64_C(236986368),	// SSUBLv8i8_v8i16
    UINT64_C(1170231296),	// SSUBWB_ZZZ_D
    UINT64_C(1161842688),	// SSUBWB_ZZZ_H
    UINT64_C(1166036992),	// SSUBWB_ZZZ_S
    UINT64_C(1170232320),	// SSUBWT_ZZZ_D
    UINT64_C(1161843712),	// SSUBWT_ZZZ_H
    UINT64_C(1166038016),	// SSUBWT_ZZZ_S
    UINT64_C(1310732288),	// SSUBWv16i8_v8i16
    UINT64_C(245379072),	// SSUBWv2i32_v2i64
    UINT64_C(241184768),	// SSUBWv4i16_v4i32
    UINT64_C(1319120896),	// SSUBWv4i32_v2i64
    UINT64_C(1314926592),	// SSUBWv8i16_v4i32
    UINT64_C(236990464),	// SSUBWv8i8_v8i16
    UINT64_C(3825221632),	// ST1B
    UINT64_C(2686451712),	// ST1B_2Z
    UINT64_C(2690646016),	// ST1B_2Z_IMM
    UINT64_C(2703228928),	// ST1B_2Z_STRIDED
    UINT64_C(2707423232),	// ST1B_2Z_STRIDED_IMM
    UINT64_C(2686484480),	// ST1B_4Z
    UINT64_C(2690678784),	// ST1B_4Z_IMM
    UINT64_C(2703261696),	// ST1B_4Z_STRIDED
    UINT64_C(2707456000),	// ST1B_4Z_STRIDED_IMM
    UINT64_C(3831513088),	// ST1B_D
    UINT64_C(3831554048),	// ST1B_D_IMM
    UINT64_C(3827318784),	// ST1B_H
    UINT64_C(3827359744),	// ST1B_H_IMM
    UINT64_C(3825262592),	// ST1B_IMM
    UINT64_C(3829415936),	// ST1B_S
    UINT64_C(3829456896),	// ST1B_S_IMM
    UINT64_C(3856678912),	// ST1D
    UINT64_C(2686476288),	// ST1D_2Z
    UINT64_C(2690670592),	// ST1D_2Z_IMM
    UINT64_C(2703253504),	// ST1D_2Z_STRIDED
    UINT64_C(2707447808),	// ST1D_2Z_STRIDED_IMM
    UINT64_C(2686509056),	// ST1D_4Z
    UINT64_C(2690703360),	// ST1D_4Z_IMM
    UINT64_C(2703286272),	// ST1D_4Z_STRIDED
    UINT64_C(2707480576),	// ST1D_4Z_STRIDED_IMM
    UINT64_C(3856719872),	// ST1D_IMM
    UINT64_C(3854581760),	// ST1D_Q
    UINT64_C(3854622720),	// ST1D_Q_IMM
    UINT64_C(1275076608),	// ST1Fourv16b
    UINT64_C(1283465216),	// ST1Fourv16b_POST
    UINT64_C(201337856),	// ST1Fourv1d
    UINT64_C(209726464),	// ST1Fourv1d_POST
    UINT64_C(1275079680),	// ST1Fourv2d
    UINT64_C(1283468288),	// ST1Fourv2d_POST
    UINT64_C(201336832),	// ST1Fourv2s
    UINT64_C(209725440),	// ST1Fourv2s_POST
    UINT64_C(201335808),	// ST1Fourv4h
    UINT64_C(209724416),	// ST1Fourv4h_POST
    UINT64_C(1275078656),	// ST1Fourv4s
    UINT64_C(1283467264),	// ST1Fourv4s_POST
    UINT64_C(201334784),	// ST1Fourv8b
    UINT64_C(209723392),	// ST1Fourv8b_POST
    UINT64_C(1275077632),	// ST1Fourv8h
    UINT64_C(1283466240),	// ST1Fourv8h_POST
    UINT64_C(3835707392),	// ST1H
    UINT64_C(2686459904),	// ST1H_2Z
    UINT64_C(2690654208),	// ST1H_2Z_IMM
    UINT64_C(2703237120),	// ST1H_2Z_STRIDED
    UINT64_C(2707431424),	// ST1H_2Z_STRIDED_IMM
    UINT64_C(2686492672),	// ST1H_4Z
    UINT64_C(2690686976),	// ST1H_4Z_IMM
    UINT64_C(2703269888),	// ST1H_4Z_STRIDED
    UINT64_C(2707464192),	// ST1H_4Z_STRIDED_IMM
    UINT64_C(3839901696),	// ST1H_D
    UINT64_C(3839942656),	// ST1H_D_IMM
    UINT64_C(3835748352),	// ST1H_IMM
    UINT64_C(3837804544),	// ST1H_S
    UINT64_C(3837845504),	// ST1H_S_IMM
    UINT64_C(1275097088),	// ST1Onev16b
    UINT64_C(1283485696),	// ST1Onev16b_POST
    UINT64_C(201358336),	// ST1Onev1d
    UINT64_C(209746944),	// ST1Onev1d_POST
    UINT64_C(1275100160),	// ST1Onev2d
    UINT64_C(1283488768),	// ST1Onev2d_POST
    UINT64_C(201357312),	// ST1Onev2s
    UINT64_C(209745920),	// ST1Onev2s_POST
    UINT64_C(201356288),	// ST1Onev4h
    UINT64_C(209744896),	// ST1Onev4h_POST
    UINT64_C(1275099136),	// ST1Onev4s
    UINT64_C(1283487744),	// ST1Onev4s_POST
    UINT64_C(201355264),	// ST1Onev8b
    UINT64_C(209743872),	// ST1Onev8b_POST
    UINT64_C(1275098112),	// ST1Onev8h
    UINT64_C(1283486720),	// ST1Onev8h_POST
    UINT64_C(1275092992),	// ST1Threev16b
    UINT64_C(1283481600),	// ST1Threev16b_POST
    UINT64_C(201354240),	// ST1Threev1d
    UINT64_C(209742848),	// ST1Threev1d_POST
    UINT64_C(1275096064),	// ST1Threev2d
    UINT64_C(1283484672),	// ST1Threev2d_POST
    UINT64_C(201353216),	// ST1Threev2s
    UINT64_C(209741824),	// ST1Threev2s_POST
    UINT64_C(201352192),	// ST1Threev4h
    UINT64_C(209740800),	// ST1Threev4h_POST
    UINT64_C(1275095040),	// ST1Threev4s
    UINT64_C(1283483648),	// ST1Threev4s_POST
    UINT64_C(201351168),	// ST1Threev8b
    UINT64_C(209739776),	// ST1Threev8b_POST
    UINT64_C(1275094016),	// ST1Threev8h
    UINT64_C(1283482624),	// ST1Threev8h_POST
    UINT64_C(1275109376),	// ST1Twov16b
    UINT64_C(1283497984),	// ST1Twov16b_POST
    UINT64_C(201370624),	// ST1Twov1d
    UINT64_C(209759232),	// ST1Twov1d_POST
    UINT64_C(1275112448),	// ST1Twov2d
    UINT64_C(1283501056),	// ST1Twov2d_POST
    UINT64_C(201369600),	// ST1Twov2s
    UINT64_C(209758208),	// ST1Twov2s_POST
    UINT64_C(201368576),	// ST1Twov4h
    UINT64_C(209757184),	// ST1Twov4h_POST
    UINT64_C(1275111424),	// ST1Twov4s
    UINT64_C(1283500032),	// ST1Twov4s_POST
    UINT64_C(201367552),	// ST1Twov8b
    UINT64_C(209756160),	// ST1Twov8b_POST
    UINT64_C(1275110400),	// ST1Twov8h
    UINT64_C(1283499008),	// ST1Twov8h_POST
    UINT64_C(3846193152),	// ST1W
    UINT64_C(2686468096),	// ST1W_2Z
    UINT64_C(2690662400),	// ST1W_2Z_IMM
    UINT64_C(2703245312),	// ST1W_2Z_STRIDED
    UINT64_C(2707439616),	// ST1W_2Z_STRIDED_IMM
    UINT64_C(2686500864),	// ST1W_4Z
    UINT64_C(2690695168),	// ST1W_4Z_IMM
    UINT64_C(2703278080),	// ST1W_4Z_STRIDED
    UINT64_C(2707472384),	// ST1W_4Z_STRIDED_IMM
    UINT64_C(3848290304),	// ST1W_D
    UINT64_C(3848331264),	// ST1W_D_IMM
    UINT64_C(3846234112),	// ST1W_IMM
    UINT64_C(3841998848),	// ST1W_Q
    UINT64_C(3842039808),	// ST1W_Q_IMM
    UINT64_C(3760193536),	// ST1_MXIPXX_H_B
    UINT64_C(3772776448),	// ST1_MXIPXX_H_D
    UINT64_C(3764387840),	// ST1_MXIPXX_H_H
    UINT64_C(3789553664),	// ST1_MXIPXX_H_Q
    UINT64_C(3768582144),	// ST1_MXIPXX_H_S
    UINT64_C(3760226304),	// ST1_MXIPXX_V_B
    UINT64_C(3772809216),	// ST1_MXIPXX_V_D
    UINT64_C(3764420608),	// ST1_MXIPXX_V_H
    UINT64_C(3789586432),	// ST1_MXIPXX_V_Q
    UINT64_C(3768614912),	// ST1_MXIPXX_V_S
    UINT64_C(218120192),	// ST1i16
    UINT64_C(226508800),	// ST1i16_POST
    UINT64_C(218136576),	// ST1i32
    UINT64_C(226525184),	// ST1i32_POST
    UINT64_C(218137600),	// ST1i64
    UINT64_C(226526208),	// ST1i64_POST
    UINT64_C(218103808),	// ST1i8
    UINT64_C(226492416),	// ST1i8_POST
    UINT64_C(3827326976),	// ST2B
    UINT64_C(3828408320),	// ST2B_IMM
    UINT64_C(3852492800),	// ST2D
    UINT64_C(3853574144),	// ST2D_IMM
    UINT64_C(3651142656),	// ST2GPostIndex
    UINT64_C(3651144704),	// ST2GPreIndex
    UINT64_C(3651143680),	// ST2Gi
    UINT64_C(3835715584),	// ST2H
    UINT64_C(3836796928),	// ST2H_IMM
    UINT64_C(3831496704),	// ST2Q
    UINT64_C(3829399552),	// ST2Q_IMM
    UINT64_C(1275101184),	// ST2Twov16b
    UINT64_C(1283489792),	// ST2Twov16b_POST
    UINT64_C(1275104256),	// ST2Twov2d
    UINT64_C(1283492864),	// ST2Twov2d_POST
    UINT64_C(201361408),	// ST2Twov2s
    UINT64_C(209750016),	// ST2Twov2s_POST
    UINT64_C(201360384),	// ST2Twov4h
    UINT64_C(209748992),	// ST2Twov4h_POST
    UINT64_C(1275103232),	// ST2Twov4s
    UINT64_C(1283491840),	// ST2Twov4s_POST
    UINT64_C(201359360),	// ST2Twov8b
    UINT64_C(209747968),	// ST2Twov8b_POST
    UINT64_C(1275102208),	// ST2Twov8h
    UINT64_C(1283490816),	// ST2Twov8h_POST
    UINT64_C(3844104192),	// ST2W
    UINT64_C(3845185536),	// ST2W_IMM
    UINT64_C(220217344),	// ST2i16
    UINT64_C(228605952),	// ST2i16_POST
    UINT64_C(220233728),	// ST2i32
    UINT64_C(228622336),	// ST2i32_POST
    UINT64_C(220234752),	// ST2i64
    UINT64_C(228623360),	// ST2i64_POST
    UINT64_C(220200960),	// ST2i8
    UINT64_C(228589568),	// ST2i8_POST
    UINT64_C(3829424128),	// ST3B
    UINT64_C(3830505472),	// ST3B_IMM
    UINT64_C(3854589952),	// ST3D
    UINT64_C(3855671296),	// ST3D_IMM
    UINT64_C(3837812736),	// ST3H
    UINT64_C(3838894080),	// ST3H_IMM
    UINT64_C(3835691008),	// ST3Q
    UINT64_C(3833593856),	// ST3Q_IMM
    UINT64_C(1275084800),	// ST3Threev16b
    UINT64_C(1283473408),	// ST3Threev16b_POST
    UINT64_C(1275087872),	// ST3Threev2d
    UINT64_C(1283476480),	// ST3Threev2d_POST
    UINT64_C(201345024),	// ST3Threev2s
    UINT64_C(209733632),	// ST3Threev2s_POST
    UINT64_C(201344000),	// ST3Threev4h
    UINT64_C(209732608),	// ST3Threev4h_POST
    UINT64_C(1275086848),	// ST3Threev4s
    UINT64_C(1283475456),	// ST3Threev4s_POST
    UINT64_C(201342976),	// ST3Threev8b
    UINT64_C(209731584),	// ST3Threev8b_POST
    UINT64_C(1275085824),	// ST3Threev8h
    UINT64_C(1283474432),	// ST3Threev8h_POST
    UINT64_C(3846201344),	// ST3W
    UINT64_C(3847282688),	// ST3W_IMM
    UINT64_C(218128384),	// ST3i16
    UINT64_C(226516992),	// ST3i16_POST
    UINT64_C(218144768),	// ST3i32
    UINT64_C(226533376),	// ST3i32_POST
    UINT64_C(218145792),	// ST3i64
    UINT64_C(226534400),	// ST3i64_POST
    UINT64_C(218112000),	// ST3i8
    UINT64_C(226500608),	// ST3i8_POST
    UINT64_C(3831521280),	// ST4B
    UINT64_C(3832602624),	// ST4B_IMM
    UINT64_C(3856687104),	// ST4D
    UINT64_C(3857768448),	// ST4D_IMM
    UINT64_C(1275068416),	// ST4Fourv16b
    UINT64_C(1283457024),	// ST4Fourv16b_POST
    UINT64_C(1275071488),	// ST4Fourv2d
    UINT64_C(1283460096),	// ST4Fourv2d_POST
    UINT64_C(201328640),	// ST4Fourv2s
    UINT64_C(209717248),	// ST4Fourv2s_POST
    UINT64_C(201327616),	// ST4Fourv4h
    UINT64_C(209716224),	// ST4Fourv4h_POST
    UINT64_C(1275070464),	// ST4Fourv4s
    UINT64_C(1283459072),	// ST4Fourv4s_POST
    UINT64_C(201326592),	// ST4Fourv8b
    UINT64_C(209715200),	// ST4Fourv8b_POST
    UINT64_C(1275069440),	// ST4Fourv8h
    UINT64_C(1283458048),	// ST4Fourv8h_POST
    UINT64_C(3839909888),	// ST4H
    UINT64_C(3840991232),	// ST4H_IMM
    UINT64_C(3839885312),	// ST4Q
    UINT64_C(3837788160),	// ST4Q_IMM
    UINT64_C(3848298496),	// ST4W
    UINT64_C(3849379840),	// ST4W_IMM
    UINT64_C(220225536),	// ST4i16
    UINT64_C(228614144),	// ST4i16_POST
    UINT64_C(220241920),	// ST4i32
    UINT64_C(228630528),	// ST4i32_POST
    UINT64_C(220242944),	// ST4i64
    UINT64_C(228631552),	// ST4i64_POST
    UINT64_C(220209152),	// ST4i8
    UINT64_C(228597760),	// ST4i8_POST
    UINT64_C(4164915200),	// ST64B
    UINT64_C(4162891776),	// ST64BV
    UINT64_C(4162887680),	// ST64BV0
    UINT64_C(1008762911),	// STBFADD
    UINT64_C(1012957215),	// STBFADDL
    UINT64_C(1008779295),	// STBFMAX
    UINT64_C(1012973599),	// STBFMAXL
    UINT64_C(1008787487),	// STBFMAXNM
    UINT64_C(1012981791),	// STBFMAXNML
    UINT64_C(1008783391),	// STBFMIN
    UINT64_C(1012977695),	// STBFMINL
    UINT64_C(1008791583),	// STBFMINNM
    UINT64_C(1012985887),	// STBFMINNML
    UINT64_C(3573753503),	// STCPH
    UINT64_C(4229988383),	// STFADDD
    UINT64_C(2082504735),	// STFADDH
    UINT64_C(4234182687),	// STFADDLD
    UINT64_C(2086699039),	// STFADDLH
    UINT64_C(3160440863),	// STFADDLS
    UINT64_C(3156246559),	// STFADDS
    UINT64_C(4230004767),	// STFMAXD
    UINT64_C(2082521119),	// STFMAXH
    UINT64_C(4234199071),	// STFMAXLD
    UINT64_C(2086715423),	// STFMAXLH
    UINT64_C(3160457247),	// STFMAXLS
    UINT64_C(4230012959),	// STFMAXNMD
    UINT64_C(2082529311),	// STFMAXNMH
    UINT64_C(4234207263),	// STFMAXNMLD
    UINT64_C(2086723615),	// STFMAXNMLH
    UINT64_C(3160465439),	// STFMAXNMLS
    UINT64_C(3156271135),	// STFMAXNMS
    UINT64_C(3156262943),	// STFMAXS
    UINT64_C(4230008863),	// STFMIND
    UINT64_C(2082525215),	// STFMINH
    UINT64_C(4234203167),	// STFMINLD
    UINT64_C(2086719519),	// STFMINLH
    UINT64_C(3160461343),	// STFMINLS
    UINT64_C(4230017055),	// STFMINNMD
    UINT64_C(2082533407),	// STFMINNMH
    UINT64_C(4234211359),	// STFMINNMLD
    UINT64_C(2086727711),	// STFMINNMLH
    UINT64_C(3160469535),	// STFMINNMLS
    UINT64_C(3156275231),	// STFMINNMS
    UINT64_C(3156267039),	// STFMINS
    UINT64_C(3651141632),	// STGM
    UINT64_C(1761607680),	// STGPi
    UINT64_C(3642754048),	// STGPostIndex
    UINT64_C(1753219072),	// STGPpost
    UINT64_C(1769996288),	// STGPpre
    UINT64_C(3642756096),	// STGPreIndex
    UINT64_C(3642755072),	// STGi
    UINT64_C(2566920192),	// STILPW
    UINT64_C(2566916096),	// STILPWpre
    UINT64_C(3640662016),	// STILPX
    UINT64_C(3640657920),	// STILPXpre
    UINT64_C(218203136),	// STL1
    UINT64_C(144669696),	// STLLRB
    UINT64_C(1218411520),	// STLLRH
    UINT64_C(2292153344),	// STLLRW
    UINT64_C(3365895168),	// STLLRX
    UINT64_C(3640678400),	// STLPi
    UINT64_C(144702464),	// STLRB
    UINT64_C(1218444288),	// STLRH
    UINT64_C(2292186112),	// STLRW
    UINT64_C(2575304704),	// STLRWpre
    UINT64_C(3365927936),	// STLRX
    UINT64_C(3649046528),	// STLRXpre
    UINT64_C(2298543104),	// STLTXRW
    UINT64_C(3372284928),	// STLTXRX
    UINT64_C(419430400),	// STLURBi
    UINT64_C(1493172224),	// STLURHi
    UINT64_C(2566914048),	// STLURWi
    UINT64_C(3640655872),	// STLURXi
    UINT64_C(486541312),	// STLURbi
    UINT64_C(3707766784),	// STLURdi
    UINT64_C(1560283136),	// STLURhi
    UINT64_C(494929920),	// STLURqi
    UINT64_C(2634024960),	// STLURsi
    UINT64_C(2283831296),	// STLXPW
    UINT64_C(3357573120),	// STLXPX
    UINT64_C(134250496),	// STLXRB
    UINT64_C(1207992320),	// STLXRH
    UINT64_C(2281734144),	// STLXRW
    UINT64_C(3355475968),	// STLXRX
    UINT64_C(2151710720),	// STMOPA_M2ZZZI_BtoS
    UINT64_C(2151710728),	// STMOPA_M2ZZZI_HtoS
    UINT64_C(1811939328),	// STNPDi
    UINT64_C(2885681152),	// STNPQi
    UINT64_C(738197504),	// STNPSi
    UINT64_C(671088640),	// STNPWi
    UINT64_C(2818572288),	// STNPXi
    UINT64_C(2686451713),	// STNT1B_2Z
    UINT64_C(2690646017),	// STNT1B_2Z_IMM
    UINT64_C(2703228936),	// STNT1B_2Z_STRIDED
    UINT64_C(2707423240),	// STNT1B_2Z_STRIDED_IMM
    UINT64_C(2686484481),	// STNT1B_4Z
    UINT64_C(2690678785),	// STNT1B_4Z_IMM
    UINT64_C(2703261704),	// STNT1B_4Z_STRIDED
    UINT64_C(2707456008),	// STNT1B_4Z_STRIDED_IMM
    UINT64_C(3826311168),	// STNT1B_ZRI
    UINT64_C(3825229824),	// STNT1B_ZRR
    UINT64_C(3825213440),	// STNT1B_ZZR_D
    UINT64_C(3829407744),	// STNT1B_ZZR_S
    UINT64_C(2686476289),	// STNT1D_2Z
    UINT64_C(2690670593),	// STNT1D_2Z_IMM
    UINT64_C(2703253512),	// STNT1D_2Z_STRIDED
    UINT64_C(2707447816),	// STNT1D_2Z_STRIDED_IMM
    UINT64_C(2686509057),	// STNT1D_4Z
    UINT64_C(2690703361),	// STNT1D_4Z_IMM
    UINT64_C(2703286280),	// STNT1D_4Z_STRIDED
    UINT64_C(2707480584),	// STNT1D_4Z_STRIDED_IMM
    UINT64_C(3851476992),	// STNT1D_ZRI
    UINT64_C(3850395648),	// STNT1D_ZRR
    UINT64_C(3850379264),	// STNT1D_ZZR_D
    UINT64_C(2686459905),	// STNT1H_2Z
    UINT64_C(2690654209),	// STNT1H_2Z_IMM
    UINT64_C(2703237128),	// STNT1H_2Z_STRIDED
    UINT64_C(2707431432),	// STNT1H_2Z_STRIDED_IMM
    UINT64_C(2686492673),	// STNT1H_4Z
    UINT64_C(2690686977),	// STNT1H_4Z_IMM
    UINT64_C(2703269896),	// STNT1H_4Z_STRIDED
    UINT64_C(2707464200),	// STNT1H_4Z_STRIDED_IMM
    UINT64_C(3834699776),	// STNT1H_ZRI
    UINT64_C(3833618432),	// STNT1H_ZRR
    UINT64_C(3833602048),	// STNT1H_ZZR_D
    UINT64_C(3837796352),	// STNT1H_ZZR_S
    UINT64_C(2686468097),	// STNT1W_2Z
    UINT64_C(2690662401),	// STNT1W_2Z_IMM
    UINT64_C(2703245320),	// STNT1W_2Z_STRIDED
    UINT64_C(2707439624),	// STNT1W_2Z_STRIDED_IMM
    UINT64_C(2686500865),	// STNT1W_4Z
    UINT64_C(2690695169),	// STNT1W_4Z_IMM
    UINT64_C(2703278088),	// STNT1W_4Z_STRIDED
    UINT64_C(2707472392),	// STNT1W_4Z_STRIDED_IMM
    UINT64_C(3843088384),	// STNT1W_ZRI
    UINT64_C(3842007040),	// STNT1W_ZRR
    UINT64_C(3841990656),	// STNT1W_ZZR_D
    UINT64_C(3846184960),	// STNT1W_ZZR_S
    UINT64_C(1828716544),	// STPDi
    UINT64_C(1820327936),	// STPDpost
    UINT64_C(1837105152),	// STPDpre
    UINT64_C(2902458368),	// STPQi
    UINT64_C(2894069760),	// STPQpost
    UINT64_C(2910846976),	// STPQpre
    UINT64_C(754974720),	// STPSi
    UINT64_C(746586112),	// STPSpost
    UINT64_C(763363328),	// STPSpre
    UINT64_C(687865856),	// STPWi
    UINT64_C(679477248),	// STPWpost
    UINT64_C(696254464),	// STPWpre
    UINT64_C(2835349504),	// STPXi
    UINT64_C(2826960896),	// STPXpost
    UINT64_C(2843738112),	// STPXpre
    UINT64_C(939525120),	// STRBBpost
    UINT64_C(939527168),	// STRBBpre
    UINT64_C(941639680),	// STRBBroW
    UINT64_C(941647872),	// STRBBroX
    UINT64_C(956301312),	// STRBBui
    UINT64_C(1006633984),	// STRBpost
    UINT64_C(1006636032),	// STRBpre
    UINT64_C(1008748544),	// STRBroW
    UINT64_C(1008756736),	// STRBroX
    UINT64_C(1023410176),	// STRBui
    UINT64_C(4227859456),	// STRDpost
    UINT64_C(4227861504),	// STRDpre
    UINT64_C(4229974016),	// STRDroW
    UINT64_C(4229982208),	// STRDroX
    UINT64_C(4244635648),	// STRDui
    UINT64_C(2013266944),	// STRHHpost
    UINT64_C(2013268992),	// STRHHpre
    UINT64_C(2015381504),	// STRHHroW
    UINT64_C(2015389696),	// STRHHroX
    UINT64_C(2030043136),	// STRHHui
    UINT64_C(2080375808),	// STRHpost
    UINT64_C(2080377856),	// STRHpre
    UINT64_C(2082490368),	// STRHroW
    UINT64_C(2082498560),	// STRHroX
    UINT64_C(2097152000),	// STRHui
    UINT64_C(1015022592),	// STRQpost
    UINT64_C(1015024640),	// STRQpre
    UINT64_C(1017137152),	// STRQroW
    UINT64_C(1017145344),	// STRQroX
    UINT64_C(1031798784),	// STRQui
    UINT64_C(3154117632),	// STRSpost
    UINT64_C(3154119680),	// STRSpre
    UINT64_C(3156232192),	// STRSroW
    UINT64_C(3156240384),	// STRSroX
    UINT64_C(3170893824),	// STRSui
    UINT64_C(3087008768),	// STRWpost
    UINT64_C(3087010816),	// STRWpre
    UINT64_C(3089123328),	// STRWroW
    UINT64_C(3089131520),	// STRWroX
    UINT64_C(3103784960),	// STRWui
    UINT64_C(4160750592),	// STRXpost
    UINT64_C(4160752640),	// STRXpre
    UINT64_C(4162865152),	// STRXroW
    UINT64_C(4162873344),	// STRXroX
    UINT64_C(4177526784),	// STRXui
    UINT64_C(3850371072),	// STR_PXI
    UINT64_C(3779035136),	// STR_TX
    UINT64_C(3776970752),	// STR_ZA
    UINT64_C(3850387456),	// STR_ZXI
    UINT64_C(3573753375),	// STSHH
    UINT64_C(3959422976),	// STTNPQi
    UINT64_C(3892314112),	// STTNPXi
    UINT64_C(3976200192),	// STTPQi
    UINT64_C(3967811584),	// STTPQpost
    UINT64_C(3984588800),	// STTPQpre
    UINT64_C(3909091328),	// STTPi
    UINT64_C(3900702720),	// STTPpost
    UINT64_C(3917479936),	// STTPpre
    UINT64_C(939526144),	// STTRBi
    UINT64_C(2013267968),	// STTRHi
    UINT64_C(3087009792),	// STTRWi
    UINT64_C(4160751616),	// STTRXi
    UINT64_C(2298510336),	// STTXRWr
    UINT64_C(3372252160),	// STTXRXr
    UINT64_C(939524096),	// STURBBi
    UINT64_C(1006632960),	// STURBi
    UINT64_C(4227858432),	// STURDi
    UINT64_C(2013265920),	// STURHHi
    UINT64_C(2080374784),	// STURHi
    UINT64_C(1015021568),	// STURQi
    UINT64_C(3154116608),	// STURSi
    UINT64_C(3087007744),	// STURWi
    UINT64_C(4160749568),	// STURXi
    UINT64_C(2283798528),	// STXPW
    UINT64_C(3357540352),	// STXPX
    UINT64_C(134217728),	// STXRB
    UINT64_C(1207959552),	// STXRH
    UINT64_C(2281701376),	// STXRW
    UINT64_C(3355443200),	// STXRX
    UINT64_C(3655336960),	// STZ2GPostIndex
    UINT64_C(3655339008),	// STZ2GPreIndex
    UINT64_C(3655337984),	// STZ2Gi
    UINT64_C(3642753024),	// STZGM
    UINT64_C(3646948352),	// STZGPostIndex
    UINT64_C(3646950400),	// STZGPreIndex
    UINT64_C(3646949376),	// STZGi
    UINT64_C(3514826752),	// SUBG
    UINT64_C(1163948032),	// SUBHNB_ZZZ_B
    UINT64_C(1168142336),	// SUBHNB_ZZZ_H
    UINT64_C(1172336640),	// SUBHNB_ZZZ_S
    UINT64_C(1163949056),	// SUBHNT_ZZZ_B
    UINT64_C(1168143360),	// SUBHNT_ZZZ_H
    UINT64_C(1172337664),	// SUBHNT_ZZZ_S
    UINT64_C(245391360),	// SUBHNv2i64_v2i32
    UINT64_C(1319133184),	// SUBHNv2i64_v4i32
    UINT64_C(241197056),	// SUBHNv4i32_v4i16
    UINT64_C(1314938880),	// SUBHNv4i32_v8i16
    UINT64_C(1310744576),	// SUBHNv8i16_v16i8
    UINT64_C(237002752),	// SUBHNv8i16_v8i8
    UINT64_C(2596274176),	// SUBP
    UINT64_C(3133145088),	// SUBPS
    UINT64_C(3657441280),	// SUBPT_shift
    UINT64_C(1141940224),	// SUBP_ZPmZZ_B
    UINT64_C(1154523136),	// SUBP_ZPmZZ_D
    UINT64_C(1146134528),	// SUBP_ZPmZZ_H
    UINT64_C(1150328832),	// SUBP_ZPmZZ_S
    UINT64_C(623099904),	// SUBR_ZI_B
    UINT64_C(635682816),	// SUBR_ZI_D
    UINT64_C(627294208),	// SUBR_ZI_H
    UINT64_C(631488512),	// SUBR_ZI_S
    UINT64_C(67305472),	// SUBR_ZPmZ_B
    UINT64_C(79888384),	// SUBR_ZPmZ_D
    UINT64_C(71499776),	// SUBR_ZPmZ_H
    UINT64_C(75694080),	// SUBR_ZPmZ_S
    UINT64_C(1895825408),	// SUBSWri
    UINT64_C(1795162112),	// SUBSWrs
    UINT64_C(1797259264),	// SUBSWrx
    UINT64_C(4043309056),	// SUBSXri
    UINT64_C(3942645760),	// SUBSXrs
    UINT64_C(3944742912),	// SUBSXrx
    UINT64_C(3944767488),	// SUBSXrx64
    UINT64_C(1358954496),	// SUBWri
    UINT64_C(1258291200),	// SUBWrs
    UINT64_C(1260388352),	// SUBWrx
    UINT64_C(3506438144),	// SUBXri
    UINT64_C(3405774848),	// SUBXrs
    UINT64_C(3407872000),	// SUBXrx
    UINT64_C(3407896576),	// SUBXrx64
    UINT64_C(3252688920),	// SUB_VG2_M2Z2Z_D
    UINT64_C(3248494616),	// SUB_VG2_M2Z2Z_S
    UINT64_C(3244300312),	// SUB_VG2_M2ZZ_D
    UINT64_C(3240106008),	// SUB_VG2_M2ZZ_S
    UINT64_C(3252689944),	// SUB_VG2_M2Z_D
    UINT64_C(3248495640),	// SUB_VG2_M2Z_S
    UINT64_C(3252754456),	// SUB_VG4_M4Z4Z_D
    UINT64_C(3248560152),	// SUB_VG4_M4Z4Z_S
    UINT64_C(3245348888),	// SUB_VG4_M4ZZ_D
    UINT64_C(3241154584),	// SUB_VG4_M4ZZ_S
    UINT64_C(3252755480),	// SUB_VG4_M4Z_D
    UINT64_C(3248561176),	// SUB_VG4_M4Z_S
    UINT64_C(622968832),	// SUB_ZI_B
    UINT64_C(635551744),	// SUB_ZI_D
    UINT64_C(627163136),	// SUB_ZI_H
    UINT64_C(631357440),	// SUB_ZI_S
    UINT64_C(67174400),	// SUB_ZPmZ_B
    UINT64_C(80019456),	// SUB_ZPmZ_CPA
    UINT64_C(79757312),	// SUB_ZPmZ_D
    UINT64_C(71368704),	// SUB_ZPmZ_H
    UINT64_C(75563008),	// SUB_ZPmZ_S
    UINT64_C(69207040),	// SUB_ZZZ_B
    UINT64_C(81792000),	// SUB_ZZZ_CPA
    UINT64_C(81789952),	// SUB_ZZZ_D
    UINT64_C(73401344),	// SUB_ZZZ_H
    UINT64_C(77595648),	// SUB_ZZZ_S
    UINT64_C(1847624704),	// SUBv16i8
    UINT64_C(2128643072),	// SUBv1i64
    UINT64_C(782271488),	// SUBv2i32
    UINT64_C(1860207616),	// SUBv2i64
    UINT64_C(778077184),	// SUBv4i16
    UINT64_C(1856013312),	// SUBv4i32
    UINT64_C(1851819008),	// SUBv8i16
    UINT64_C(773882880),	// SUBv8i8
    UINT64_C(3243249720),	// SUDOT_VG2_M2ZZI_BToS
    UINT64_C(3240104984),	// SUDOT_VG2_M2ZZ_BToS
    UINT64_C(3243282488),	// SUDOT_VG4_M4ZZI_BToS
    UINT64_C(3241153560),	// SUDOT_VG4_M4ZZ_BToS
    UINT64_C(1151343616),	// SUDOT_ZZZI
    UINT64_C(1325461504),	// SUDOTlanev16i8
    UINT64_C(251719680),	// SUDOTlanev8i8
    UINT64_C(3238002708),	// SUMLALL_MZZI_BtoS
    UINT64_C(3239051312),	// SUMLALL_VG2_M2ZZI_BtoS
    UINT64_C(3240099860),	// SUMLALL_VG2_M2ZZ_BtoS
    UINT64_C(3239084080),	// SUMLALL_VG4_M4ZZI_BtoS
    UINT64_C(3241148436),	// SUMLALL_VG4_M4ZZ_BtoS
    UINT64_C(2150662656),	// SUMOP4A_M2Z2Z_BToS
    UINT64_C(2700083720),	// SUMOP4A_M2Z2Z_HtoD
    UINT64_C(2149614080),	// SUMOP4A_M2ZZ_BToS
    UINT64_C(2699035144),	// SUMOP4A_M2ZZ_HtoD
    UINT64_C(2150662144),	// SUMOP4A_MZ2Z_BToS
    UINT64_C(2700083208),	// SUMOP4A_MZ2Z_HtoD
    UINT64_C(2149613568),	// SUMOP4A_MZZ_BToS
    UINT64_C(2699034632),	// SUMOP4A_MZZ_HtoD
    UINT64_C(2150662672),	// SUMOP4S_M2Z2Z_BToS
    UINT64_C(2700083736),	// SUMOP4S_M2Z2Z_HtoD
    UINT64_C(2149614096),	// SUMOP4S_M2ZZ_BToS
    UINT64_C(2699035160),	// SUMOP4S_M2ZZ_HtoD
    UINT64_C(2150662160),	// SUMOP4S_MZ2Z_BToS
    UINT64_C(2700083224),	// SUMOP4S_MZ2Z_HtoD
    UINT64_C(2149613584),	// SUMOP4S_MZZ_BToS
    UINT64_C(2699034648),	// SUMOP4S_MZZ_HtoD
    UINT64_C(2699034624),	// SUMOPA_MPPZZ_D
    UINT64_C(2694840320),	// SUMOPA_MPPZZ_S
    UINT64_C(2699034640),	// SUMOPS_MPPZZ_D
    UINT64_C(2694840336),	// SUMOPS_MPPZZ_S
    UINT64_C(99694592),	// SUNPKHI_ZZ_D
    UINT64_C(91305984),	// SUNPKHI_ZZ_H
    UINT64_C(95500288),	// SUNPKHI_ZZ_S
    UINT64_C(99629056),	// SUNPKLO_ZZ_D
    UINT64_C(91240448),	// SUNPKLO_ZZ_H
    UINT64_C(95434752),	// SUNPKLO_ZZ_S
    UINT64_C(3253067776),	// SUNPK_VG2_2ZZ_D
    UINT64_C(3244679168),	// SUNPK_VG2_2ZZ_H
    UINT64_C(3248873472),	// SUNPK_VG2_2ZZ_S
    UINT64_C(3254116352),	// SUNPK_VG4_4Z2Z_D
    UINT64_C(3245727744),	// SUNPK_VG4_4Z2Z_H
    UINT64_C(3249922048),	// SUNPK_VG4_4Z2Z_S
    UINT64_C(1142718464),	// SUQADD_ZPmZ_B
    UINT64_C(1155301376),	// SUQADD_ZPmZ_D
    UINT64_C(1146912768),	// SUQADD_ZPmZ_H
    UINT64_C(1151107072),	// SUQADD_ZPmZ_S
    UINT64_C(1310734336),	// SUQADDv16i8
    UINT64_C(1583364096),	// SUQADDv1i16
    UINT64_C(1587558400),	// SUQADDv1i32
    UINT64_C(1591752704),	// SUQADDv1i64
    UINT64_C(1579169792),	// SUQADDv1i8
    UINT64_C(245381120),	// SUQADDv2i32
    UINT64_C(1323317248),	// SUQADDv2i64
    UINT64_C(241186816),	// SUQADDv4i16
    UINT64_C(1319122944),	// SUQADDv4i32
    UINT64_C(1314928640),	// SUQADDv8i16
    UINT64_C(236992512),	// SUQADDv8i8
    UINT64_C(2153807872),	// SUTMOPA_M2ZZZI_BtoS
    UINT64_C(3243278392),	// SUVDOT_VG4_M4ZZI_BToS
    UINT64_C(3556769793),	// SVC
    UINT64_C(3243245600),	// SVDOT_VG2_M2ZZI_HtoS
    UINT64_C(3243278368),	// SVDOT_VG4_M4ZZI_BtoS
    UINT64_C(3251669000),	// SVDOT_VG4_M4ZZI_HtoD
    UINT64_C(950042624),	// SWPAB
    UINT64_C(2023784448),	// SWPAH
    UINT64_C(954236928),	// SWPALB
    UINT64_C(2027978752),	// SWPALH
    UINT64_C(3101720576),	// SWPALW
    UINT64_C(4175462400),	// SWPALX
    UINT64_C(3097526272),	// SWPAW
    UINT64_C(4171268096),	// SWPAX
    UINT64_C(941654016),	// SWPB
    UINT64_C(2015395840),	// SWPH
    UINT64_C(945848320),	// SWPLB
    UINT64_C(2019590144),	// SWPLH
    UINT64_C(3093331968),	// SWPLW
    UINT64_C(4167073792),	// SWPLX
    UINT64_C(421560320),	// SWPP
    UINT64_C(429948928),	// SWPPA
    UINT64_C(434143232),	// SWPPAL
    UINT64_C(425754624),	// SWPPL
    UINT64_C(434144256),	// SWPTALW
    UINT64_C(1507886080),	// SWPTALX
    UINT64_C(429949952),	// SWPTAW
    UINT64_C(1503691776),	// SWPTAX
    UINT64_C(425755648),	// SWPTLW
    UINT64_C(1499497472),	// SWPTLX
    UINT64_C(421561344),	// SWPTW
    UINT64_C(1495303168),	// SWPTX
    UINT64_C(3089137664),	// SWPW
    UINT64_C(4162879488),	// SWPX
    UINT64_C(80781312),	// SXTB_ZPmZ_D
    UINT64_C(72392704),	// SXTB_ZPmZ_H
    UINT64_C(76587008),	// SXTB_ZPmZ_S
    UINT64_C(79732736),	// SXTB_ZPzZ_D
    UINT64_C(71344128),	// SXTB_ZPzZ_H
    UINT64_C(75538432),	// SXTB_ZPzZ_S
    UINT64_C(80912384),	// SXTH_ZPmZ_D
    UINT64_C(76718080),	// SXTH_ZPmZ_S
    UINT64_C(79863808),	// SXTH_ZPzZ_D
    UINT64_C(75669504),	// SXTH_ZPzZ_S
    UINT64_C(81043456),	// SXTW_ZPmZ_D
    UINT64_C(79994880),	// SXTW_ZPzZ_D
    UINT64_C(3576168448),	// SYSLxt
    UINT64_C(3578265600),	// SYSPxt
    UINT64_C(3578265631),	// SYSPxt_XZR
    UINT64_C(3574071296),	// SYSxt
    UINT64_C(1140914176),	// TBLQ_ZZZ_B
    UINT64_C(1153497088),	// TBLQ_ZZZ_D
    UINT64_C(1145108480),	// TBLQ_ZZZ_H
    UINT64_C(1149302784),	// TBLQ_ZZZ_S
    UINT64_C(85993472),	// TBL_ZZZZ_B
    UINT64_C(98576384),	// TBL_ZZZZ_D
    UINT64_C(90187776),	// TBL_ZZZZ_H
    UINT64_C(94382080),	// TBL_ZZZZ_S
    UINT64_C(85995520),	// TBL_ZZZ_B
    UINT64_C(98578432),	// TBL_ZZZ_D
    UINT64_C(90189824),	// TBL_ZZZ_H
    UINT64_C(94384128),	// TBL_ZZZ_S
    UINT64_C(1308647424),	// TBLv16i8Four
    UINT64_C(1308622848),	// TBLv16i8One
    UINT64_C(1308639232),	// TBLv16i8Three
    UINT64_C(1308631040),	// TBLv16i8Two
    UINT64_C(234905600),	// TBLv8i8Four
    UINT64_C(234881024),	// TBLv8i8One
    UINT64_C(234897408),	// TBLv8i8Three
    UINT64_C(234889216),	// TBLv8i8Two
    UINT64_C(922746880),	// TBNZW
    UINT64_C(3070230528),	// TBNZX
    UINT64_C(85996544),	// TBXQ_ZZZ_B
    UINT64_C(98579456),	// TBXQ_ZZZ_D
    UINT64_C(90190848),	// TBXQ_ZZZ_H
    UINT64_C(94385152),	// TBXQ_ZZZ_S
    UINT64_C(85994496),	// TBX_ZZZ_B
    UINT64_C(98577408),	// TBX_ZZZ_D
    UINT64_C(90188800),	// TBX_ZZZ_H
    UINT64_C(94383104),	// TBX_ZZZ_S
    UINT64_C(1308651520),	// TBXv16i8Four
    UINT64_C(1308626944),	// TBXv16i8One
    UINT64_C(1308643328),	// TBXv16i8Three
    UINT64_C(1308635136),	// TBXv16i8Two
    UINT64_C(234909696),	// TBXv8i8Four
    UINT64_C(234885120),	// TBXv8i8One
    UINT64_C(234901504),	// TBXv8i8Three
    UINT64_C(234893312),	// TBXv8i8Two
    UINT64_C(905969664),	// TBZW
    UINT64_C(3053453312),	// TBZX
    UINT64_C(3583246336),	// TCHANGEBri
    UINT64_C(3582197760),	// TCHANGEBrr
    UINT64_C(3582984192),	// TCHANGEFri
    UINT64_C(3581935616),	// TCHANGEFrr
    UINT64_C(3571449856),	// TENTER
    UINT64_C(3607036896),	// TEXIT
    UINT64_C(3574297312),	// TRCIT
    UINT64_C(86003712),	// TRN1_PPP_B
    UINT64_C(98586624),	// TRN1_PPP_D
    UINT64_C(90198016),	// TRN1_PPP_H
    UINT64_C(94392320),	// TRN1_PPP_S
    UINT64_C(86011904),	// TRN1_ZZZ_B
    UINT64_C(98594816),	// TRN1_ZZZ_D
    UINT64_C(90206208),	// TRN1_ZZZ_H
    UINT64_C(94377984),	// TRN1_ZZZ_Q
    UINT64_C(94400512),	// TRN1_ZZZ_S
    UINT64_C(1308633088),	// TRN1v16i8
    UINT64_C(243279872),	// TRN1v2i32
    UINT64_C(1321216000),	// TRN1v2i64
    UINT64_C(239085568),	// TRN1v4i16
    UINT64_C(1317021696),	// TRN1v4i32
    UINT64_C(1312827392),	// TRN1v8i16
    UINT64_C(234891264),	// TRN1v8i8
    UINT64_C(86004736),	// TRN2_PPP_B
    UINT64_C(98587648),	// TRN2_PPP_D
    UINT64_C(90199040),	// TRN2_PPP_H
    UINT64_C(94393344),	// TRN2_PPP_S
    UINT64_C(86012928),	// TRN2_ZZZ_B
    UINT64_C(98595840),	// TRN2_ZZZ_D
    UINT64_C(90207232),	// TRN2_ZZZ_H
    UINT64_C(94379008),	// TRN2_ZZZ_Q
    UINT64_C(94401536),	// TRN2_ZZZ_S
    UINT64_C(1308649472),	// TRN2v16i8
    UINT64_C(243296256),	// TRN2v2i32
    UINT64_C(1321232384),	// TRN2v2i64
    UINT64_C(239101952),	// TRN2v4i16
    UINT64_C(1317038080),	// TRN2v4i32
    UINT64_C(1312843776),	// TRN2v8i16
    UINT64_C(234907648),	// TRN2v8i8
    UINT64_C(3573752415),	// TSB
    UINT64_C(1170262016),	// UABALB_ZZZ_D
    UINT64_C(1161873408),	// UABALB_ZZZ_H
    UINT64_C(1166067712),	// UABALB_ZZZ_S
    UINT64_C(1170263040),	// UABALT_ZZZ_D
    UINT64_C(1161874432),	// UABALT_ZZZ_H
    UINT64_C(1166068736),	// UABALT_ZZZ_S
    UINT64_C(1145101312),	// UABAL_ZZZ_BtoH
    UINT64_C(1149295616),	// UABAL_ZZZ_HtoS
    UINT64_C(1153489920),	// UABAL_ZZZ_StoD
    UINT64_C(1847611392),	// UABALv16i8_v8i16
    UINT64_C(782258176),	// UABALv2i32_v2i64
    UINT64_C(778063872),	// UABALv4i16_v4i32
    UINT64_C(1856000000),	// UABALv4i32_v2i64
    UINT64_C(1851805696),	// UABALv8i16_v4i32
    UINT64_C(773869568),	// UABALv8i8_v8i16
    UINT64_C(1157692416),	// UABA_ZZZ_B
    UINT64_C(1170275328),	// UABA_ZZZ_D
    UINT64_C(1161886720),	// UABA_ZZZ_H
    UINT64_C(1166081024),	// UABA_ZZZ_S
    UINT64_C(1847622656),	// UABAv16i8
    UINT64_C(782269440),	// UABAv2i32
    UINT64_C(778075136),	// UABAv4i16
    UINT64_C(1856011264),	// UABAv4i32
    UINT64_C(1851816960),	// UABAv8i16
    UINT64_C(773880832),	// UABAv8i8
    UINT64_C(1170225152),	// UABDLB_ZZZ_D
    UINT64_C(1161836544),	// UABDLB_ZZZ_H
    UINT64_C(1166030848),	// UABDLB_ZZZ_S
    UINT64_C(1170226176),	// UABDLT_ZZZ_D
    UINT64_C(1161837568),	// UABDLT_ZZZ_H
    UINT64_C(1166031872),	// UABDLT_ZZZ_S
    UINT64_C(1847619584),	// UABDLv16i8_v8i16
    UINT64_C(782266368),	// UABDLv2i32_v2i64
    UINT64_C(778072064),	// UABDLv4i16_v4i32
    UINT64_C(1856008192),	// UABDLv4i32_v2i64
    UINT64_C(1851813888),	// UABDLv8i16_v4i32
    UINT64_C(773877760),	// UABDLv8i8_v8i16
    UINT64_C(67960832),	// UABD_ZPmZ_B
    UINT64_C(80543744),	// UABD_ZPmZ_D
    UINT64_C(72155136),	// UABD_ZPmZ_H
    UINT64_C(76349440),	// UABD_ZPmZ_S
    UINT64_C(1847620608),	// UABDv16i8
    UINT64_C(782267392),	// UABDv2i32
    UINT64_C(778073088),	// UABDv4i16
    UINT64_C(1856009216),	// UABDv4i32
    UINT64_C(1851814912),	// UABDv8i16
    UINT64_C(773878784),	// UABDv8i8
    UINT64_C(1153802240),	// UADALP_ZPmZ_D
    UINT64_C(1145413632),	// UADALP_ZPmZ_H
    UINT64_C(1149607936),	// UADALP_ZPmZ_S
    UINT64_C(1847617536),	// UADALPv16i8_v8i16
    UINT64_C(782264320),	// UADALPv2i32_v1i64
    UINT64_C(778070016),	// UADALPv4i16_v2i32
    UINT64_C(1856006144),	// UADALPv4i32_v2i64
    UINT64_C(1851811840),	// UADALPv8i16_v4i32
    UINT64_C(773875712),	// UADALPv8i8_v4i16
    UINT64_C(1170212864),	// UADDLB_ZZZ_D
    UINT64_C(1161824256),	// UADDLB_ZZZ_H
    UINT64_C(1166018560),	// UADDLB_ZZZ_S
    UINT64_C(1847601152),	// UADDLPv16i8_v8i16
    UINT64_C(782247936),	// UADDLPv2i32_v1i64
    UINT64_C(778053632),	// UADDLPv4i16_v2i32
    UINT64_C(1855989760),	// UADDLPv4i32_v2i64
    UINT64_C(1851795456),	// UADDLPv8i16_v4i32
    UINT64_C(773859328),	// UADDLPv8i8_v4i16
    UINT64_C(1170213888),	// UADDLT_ZZZ_D
    UINT64_C(1161825280),	// UADDLT_ZZZ_H
    UINT64_C(1166019584),	// UADDLT_ZZZ_S
    UINT64_C(1848653824),	// UADDLVv16i8v
    UINT64_C(779106304),	// UADDLVv4i16v
    UINT64_C(1857042432),	// UADDLVv4i32v
    UINT64_C(1852848128),	// UADDLVv8i16v
    UINT64_C(774912000),	// UADDLVv8i8v
    UINT64_C(1847590912),	// UADDLv16i8_v8i16
    UINT64_C(782237696),	// UADDLv2i32_v2i64
    UINT64_C(778043392),	// UADDLv4i16_v4i32
    UINT64_C(1855979520),	// UADDLv4i32_v2i64
    UINT64_C(1851785216),	// UADDLv8i16_v4i32
    UINT64_C(773849088),	// UADDLv8i8_v8i16
    UINT64_C(67182592),	// UADDV_VPZ_B
    UINT64_C(79765504),	// UADDV_VPZ_D
    UINT64_C(71376896),	// UADDV_VPZ_H
    UINT64_C(75571200),	// UADDV_VPZ_S
    UINT64_C(1170229248),	// UADDWB_ZZZ_D
    UINT64_C(1161840640),	// UADDWB_ZZZ_H
    UINT64_C(1166034944),	// UADDWB_ZZZ_S
    UINT64_C(1170230272),	// UADDWT_ZZZ_D
    UINT64_C(1161841664),	// UADDWT_ZZZ_H
    UINT64_C(1166035968),	// UADDWT_ZZZ_S
    UINT64_C(1847595008),	// UADDWv16i8_v8i16
    UINT64_C(782241792),	// UADDWv2i32_v2i64
    UINT64_C(778047488),	// UADDWv4i16_v4i32
    UINT64_C(1855983616),	// UADDWv4i32_v2i64
    UINT64_C(1851789312),	// UADDWv8i16_v4i32
    UINT64_C(773853184),	// UADDWv8i8_v8i16
    UINT64_C(1392508928),	// UBFMWri
    UINT64_C(3544186880),	// UBFMXri
    UINT64_C(3240150017),	// UCLAMP_VG2_2Z2Z_B
    UINT64_C(3252732929),	// UCLAMP_VG2_2Z2Z_D
    UINT64_C(3244344321),	// UCLAMP_VG2_2Z2Z_H
    UINT64_C(3248538625),	// UCLAMP_VG2_2Z2Z_S
    UINT64_C(3240152065),	// UCLAMP_VG4_4Z4Z_B
    UINT64_C(3252734977),	// UCLAMP_VG4_4Z4Z_D
    UINT64_C(3244346369),	// UCLAMP_VG4_4Z4Z_H
    UINT64_C(3248540673),	// UCLAMP_VG4_4Z4Z_S
    UINT64_C(1140900864),	// UCLAMP_ZZZ_B
    UINT64_C(1153483776),	// UCLAMP_ZZZ_D
    UINT64_C(1145095168),	// UCLAMP_ZZZ_H
    UINT64_C(1149289472),	// UCLAMP_ZZZ_S
    UINT64_C(511508480),	// UCVTFDSr
    UINT64_C(2667380736),	// UCVTFHDr
    UINT64_C(519897088),	// UCVTFHSr
    UINT64_C(1699494912),	// UCVTFLT_ZZ_BtoH
    UINT64_C(1703689216),	// UCVTFLT_ZZ_HtoS
    UINT64_C(1707883520),	// UCVTFLT_ZZ_StoD
    UINT64_C(2654797824),	// UCVTFSDr
    UINT64_C(507740160),	// UCVTFSWDri
    UINT64_C(516128768),	// UCVTFSWHri
    UINT64_C(503545856),	// UCVTFSWSri
    UINT64_C(2655191040),	// UCVTFSXDri
    UINT64_C(2663579648),	// UCVTFSXHri
    UINT64_C(2650996736),	// UCVTFSXSri
    UINT64_C(509804544),	// UCVTFUWDri
    UINT64_C(518193152),	// UCVTFUWHri
    UINT64_C(505610240),	// UCVTFUWSri
    UINT64_C(2657288192),	// UCVTFUXDri
    UINT64_C(2665676800),	// UCVTFUXHri
    UINT64_C(2653093888),	// UCVTFUXSri
    UINT64_C(3240288288),	// UCVTF_2Z2Z_StoS
    UINT64_C(3241336864),	// UCVTF_4Z4Z_StoS
    UINT64_C(1708630016),	// UCVTF_ZPmZ_DtoD
    UINT64_C(1700241408),	// UCVTF_ZPmZ_DtoH
    UINT64_C(1708498944),	// UCVTF_ZPmZ_DtoS
    UINT64_C(1699979264),	// UCVTF_ZPmZ_HtoH
    UINT64_C(1708236800),	// UCVTF_ZPmZ_StoD
    UINT64_C(1700110336),	// UCVTF_ZPmZ_StoH
    UINT64_C(1704304640),	// UCVTF_ZPmZ_StoS
    UINT64_C(1692262400),	// UCVTF_ZPzZ_DtoD
    UINT64_C(1683873792),	// UCVTF_ZPzZ_DtoH
    UINT64_C(1692246016),	// UCVTF_ZPzZ_DtoS
    UINT64_C(1683808256),	// UCVTF_ZPzZ_HtoH
    UINT64_C(1692180480),	// UCVTF_ZPzZ_StoD
    UINT64_C(1683857408),	// UCVTF_ZPzZ_StoH
    UINT64_C(1688051712),	// UCVTF_ZPzZ_StoS
    UINT64_C(1699492864),	// UCVTF_ZZ_BtoH
    UINT64_C(1703687168),	// UCVTF_ZZ_HtoS
    UINT64_C(1707881472),	// UCVTF_ZZ_StoD
    UINT64_C(2134959104),	// UCVTFd
    UINT64_C(2131813376),	// UCVTFh
    UINT64_C(2132861952),	// UCVTFs
    UINT64_C(2121914368),	// UCVTFv1i16
    UINT64_C(2116147200),	// UCVTFv1i32
    UINT64_C(2120341504),	// UCVTFv1i64
    UINT64_C(773969920),	// UCVTFv2f32
    UINT64_C(1851906048),	// UCVTFv2f64
    UINT64_C(790684672),	// UCVTFv2i32_shift
    UINT64_C(1866523648),	// UCVTFv2i64_shift
    UINT64_C(779737088),	// UCVTFv4f16
    UINT64_C(1847711744),	// UCVTFv4f32
    UINT64_C(789636096),	// UCVTFv4i16_shift
    UINT64_C(1864426496),	// UCVTFv4i32_shift
    UINT64_C(1853478912),	// UCVTFv8f16
    UINT64_C(1863377920),	// UCVTFv8i16_shift
    UINT64_C(0),	// UDF
    UINT64_C(81199104),	// UDIVR_ZPmZ_D
    UINT64_C(77004800),	// UDIVR_ZPmZ_S
    UINT64_C(448792576),	// UDIVWr
    UINT64_C(2596276224),	// UDIVXr
    UINT64_C(81068032),	// UDIV_ZPmZ_D
    UINT64_C(76873728),	// UDIV_ZPmZ_S
    UINT64_C(3248493584),	// UDOT_VG2_M2Z2Z_BtoS
    UINT64_C(3252687888),	// UDOT_VG2_M2Z2Z_HtoD
    UINT64_C(3252687896),	// UDOT_VG2_M2Z2Z_HtoS
    UINT64_C(3243249712),	// UDOT_VG2_M2ZZI_BToS
    UINT64_C(3243249680),	// UDOT_VG2_M2ZZI_HToS
    UINT64_C(3251634200),	// UDOT_VG2_M2ZZI_HtoD
    UINT64_C(3240104976),	// UDOT_VG2_M2ZZ_BtoS
    UINT64_C(3244299280),	// UDOT_VG2_M2ZZ_HtoD
    UINT64_C(3244299288),	// UDOT_VG2_M2ZZ_HtoS
    UINT64_C(3248559120),	// UDOT_VG4_M4Z4Z_BtoS
    UINT64_C(3252753424),	// UDOT_VG4_M4Z4Z_HtoD
    UINT64_C(3252753432),	// UDOT_VG4_M4Z4Z_HtoS
    UINT64_C(3243282480),	// UDOT_VG4_M4ZZI_BtoS
    UINT64_C(3243282448),	// UDOT_VG4_M4ZZI_HToS
    UINT64_C(3251666968),	// UDOT_VG4_M4ZZI_HtoD
    UINT64_C(3241153552),	// UDOT_VG4_M4ZZ_BtoS
    UINT64_C(3245347856),	// UDOT_VG4_M4ZZ_HtoD
    UINT64_C(3245347864),	// UDOT_VG4_M4ZZ_HtoS
    UINT64_C(1142948864),	// UDOT_ZZZI_BtoH
    UINT64_C(1151337472),	// UDOT_ZZZI_BtoS
    UINT64_C(1155531776),	// UDOT_ZZZI_HtoD
    UINT64_C(1149291520),	// UDOT_ZZZI_HtoS
    UINT64_C(1145046016),	// UDOT_ZZZ_BtoH
    UINT64_C(1149240320),	// UDOT_ZZZ_BtoS
    UINT64_C(1153434624),	// UDOT_ZZZ_HtoD
    UINT64_C(1140902912),	// UDOT_ZZZ_HtoS
    UINT64_C(1870716928),	// UDOTlanev16i8
    UINT64_C(796975104),	// UDOTlanev8i8
    UINT64_C(1853920256),	// UDOTv16i8
    UINT64_C(780178432),	// UDOTv8i8
    UINT64_C(1141997568),	// UHADD_ZPmZ_B
    UINT64_C(1154580480),	// UHADD_ZPmZ_D
    UINT64_C(1146191872),	// UHADD_ZPmZ_H
    UINT64_C(1150386176),	// UHADD_ZPmZ_S
    UINT64_C(1847591936),	// UHADDv16i8
    UINT64_C(782238720),	// UHADDv2i32
    UINT64_C(778044416),	// UHADDv4i16
    UINT64_C(1855980544),	// UHADDv4i32
    UINT64_C(1851786240),	// UHADDv8i16
    UINT64_C(773850112),	// UHADDv8i8
    UINT64_C(1142390784),	// UHSUBR_ZPmZ_B
    UINT64_C(1154973696),	// UHSUBR_ZPmZ_D
    UINT64_C(1146585088),	// UHSUBR_ZPmZ_H
    UINT64_C(1150779392),	// UHSUBR_ZPmZ_S
    UINT64_C(1142128640),	// UHSUB_ZPmZ_B
    UINT64_C(1154711552),	// UHSUB_ZPmZ_D
    UINT64_C(1146322944),	// UHSUB_ZPmZ_H
    UINT64_C(1150517248),	// UHSUB_ZPmZ_S
    UINT64_C(1847600128),	// UHSUBv16i8
    UINT64_C(782246912),	// UHSUBv2i32
    UINT64_C(778052608),	// UHSUBv4i16
    UINT64_C(1855988736),	// UHSUBv4i32
    UINT64_C(1851794432),	// UHSUBv8i16
    UINT64_C(773858304),	// UHSUBv8i8
    UINT64_C(2610954240),	// UMADDLrrr
    UINT64_C(1142267904),	// UMAXP_ZPmZ_B
    UINT64_C(1154850816),	// UMAXP_ZPmZ_D
    UINT64_C(1146462208),	// UMAXP_ZPmZ_H
    UINT64_C(1150656512),	// UMAXP_ZPmZ_S
    UINT64_C(1847632896),	// UMAXPv16i8
    UINT64_C(782279680),	// UMAXPv2i32
    UINT64_C(778085376),	// UMAXPv4i16
    UINT64_C(1856021504),	// UMAXPv4i32
    UINT64_C(1851827200),	// UMAXPv8i16
    UINT64_C(773891072),	// UMAXPv8i8
    UINT64_C(67969024),	// UMAXQV_VPZ_B
    UINT64_C(80551936),	// UMAXQV_VPZ_D
    UINT64_C(72163328),	// UMAXQV_VPZ_H
    UINT64_C(76357632),	// UMAXQV_VPZ_S
    UINT64_C(67706880),	// UMAXV_VPZ_B
    UINT64_C(80289792),	// UMAXV_VPZ_D
    UINT64_C(71901184),	// UMAXV_VPZ_H
    UINT64_C(76095488),	// UMAXV_VPZ_S
    UINT64_C(1848682496),	// UMAXVv16i8v
    UINT64_C(779134976),	// UMAXVv4i16v
    UINT64_C(1857071104),	// UMAXVv4i32v
    UINT64_C(1852876800),	// UMAXVv8i16v
    UINT64_C(774940672),	// UMAXVv8i8v
    UINT64_C(298057728),	// UMAXWri
    UINT64_C(448816128),	// UMAXWrr
    UINT64_C(2445541376),	// UMAXXri
    UINT64_C(2596299776),	// UMAXXrr
    UINT64_C(3240144897),	// UMAX_VG2_2Z2Z_B
    UINT64_C(3252727809),	// UMAX_VG2_2Z2Z_D
    UINT64_C(3244339201),	// UMAX_VG2_2Z2Z_H
    UINT64_C(3248533505),	// UMAX_VG2_2Z2Z_S
    UINT64_C(3240140801),	// UMAX_VG2_2ZZ_B
    UINT64_C(3252723713),	// UMAX_VG2_2ZZ_D
    UINT64_C(3244335105),	// UMAX_VG2_2ZZ_H
    UINT64_C(3248529409),	// UMAX_VG2_2ZZ_S
    UINT64_C(3240146945),	// UMAX_VG4_4Z4Z_B
    UINT64_C(3252729857),	// UMAX_VG4_4Z4Z_D
    UINT64_C(3244341249),	// UMAX_VG4_4Z4Z_H
    UINT64_C(3248535553),	// UMAX_VG4_4Z4Z_S
    UINT64_C(3240142849),	// UMAX_VG4_4ZZ_B
    UINT64_C(3252725761),	// UMAX_VG4_4ZZ_D
    UINT64_C(3244337153),	// UMAX_VG4_4ZZ_H
    UINT64_C(3248531457),	// UMAX_VG4_4ZZ_S
    UINT64_C(623493120),	// UMAX_ZI_B
    UINT64_C(636076032),	// UMAX_ZI_D
    UINT64_C(627687424),	// UMAX_ZI_H
    UINT64_C(631881728),	// UMAX_ZI_S
    UINT64_C(67698688),	// UMAX_ZPmZ_B
    UINT64_C(80281600),	// UMAX_ZPmZ_D
    UINT64_C(71892992),	// UMAX_ZPmZ_H
    UINT64_C(76087296),	// UMAX_ZPmZ_S
    UINT64_C(1847616512),	// UMAXv16i8
    UINT64_C(782263296),	// UMAXv2i32
    UINT64_C(778068992),	// UMAXv4i16
    UINT64_C(1856005120),	// UMAXv4i32
    UINT64_C(1851810816),	// UMAXv8i16
    UINT64_C(773874688),	// UMAXv8i8
    UINT64_C(1142398976),	// UMINP_ZPmZ_B
    UINT64_C(1154981888),	// UMINP_ZPmZ_D
    UINT64_C(1146593280),	// UMINP_ZPmZ_H
    UINT64_C(1150787584),	// UMINP_ZPmZ_S
    UINT64_C(1847634944),	// UMINPv16i8
    UINT64_C(782281728),	// UMINPv2i32
    UINT64_C(778087424),	// UMINPv4i16
    UINT64_C(1856023552),	// UMINPv4i32
    UINT64_C(1851829248),	// UMINPv8i16
    UINT64_C(773893120),	// UMINPv8i8
    UINT64_C(68100096),	// UMINQV_VPZ_B
    UINT64_C(80683008),	// UMINQV_VPZ_D
    UINT64_C(72294400),	// UMINQV_VPZ_H
    UINT64_C(76488704),	// UMINQV_VPZ_S
    UINT64_C(67837952),	// UMINV_VPZ_B
    UINT64_C(80420864),	// UMINV_VPZ_D
    UINT64_C(72032256),	// UMINV_VPZ_H
    UINT64_C(76226560),	// UMINV_VPZ_S
    UINT64_C(1848748032),	// UMINVv16i8v
    UINT64_C(779200512),	// UMINVv4i16v
    UINT64_C(1857136640),	// UMINVv4i32v
    UINT64_C(1852942336),	// UMINVv8i16v
    UINT64_C(775006208),	// UMINVv8i8v
    UINT64_C(298582016),	// UMINWri
    UINT64_C(448818176),	// UMINWrr
    UINT64_C(2446065664),	// UMINXri
    UINT64_C(2596301824),	// UMINXrr
    UINT64_C(3240144929),	// UMIN_VG2_2Z2Z_B
    UINT64_C(3252727841),	// UMIN_VG2_2Z2Z_D
    UINT64_C(3244339233),	// UMIN_VG2_2Z2Z_H
    UINT64_C(3248533537),	// UMIN_VG2_2Z2Z_S
    UINT64_C(3240140833),	// UMIN_VG2_2ZZ_B
    UINT64_C(3252723745),	// UMIN_VG2_2ZZ_D
    UINT64_C(3244335137),	// UMIN_VG2_2ZZ_H
    UINT64_C(3248529441),	// UMIN_VG2_2ZZ_S
    UINT64_C(3240146977),	// UMIN_VG4_4Z4Z_B
    UINT64_C(3252729889),	// UMIN_VG4_4Z4Z_D
    UINT64_C(3244341281),	// UMIN_VG4_4Z4Z_H
    UINT64_C(3248535585),	// UMIN_VG4_4Z4Z_S
    UINT64_C(3240142881),	// UMIN_VG4_4ZZ_B
    UINT64_C(3252725793),	// UMIN_VG4_4ZZ_D
    UINT64_C(3244337185),	// UMIN_VG4_4ZZ_H
    UINT64_C(3248531489),	// UMIN_VG4_4ZZ_S
    UINT64_C(623624192),	// UMIN_ZI_B
    UINT64_C(636207104),	// UMIN_ZI_D
    UINT64_C(627818496),	// UMIN_ZI_H
    UINT64_C(632012800),	// UMIN_ZI_S
    UINT64_C(67829760),	// UMIN_ZPmZ_B
    UINT64_C(80412672),	// UMIN_ZPmZ_D
    UINT64_C(72024064),	// UMIN_ZPmZ_H
    UINT64_C(76218368),	// UMIN_ZPmZ_S
    UINT64_C(1847618560),	// UMINv16i8
    UINT64_C(782265344),	// UMINv2i32
    UINT64_C(778071040),	// UMINv4i16
    UINT64_C(1856007168),	// UMINv4i32
    UINT64_C(1851812864),	// UMINv8i16
    UINT64_C(773876736),	// UMINv8i8
    UINT64_C(1155567616),	// UMLALB_ZZZI_D
    UINT64_C(1151373312),	// UMLALB_ZZZI_S
    UINT64_C(1153452032),	// UMLALB_ZZZ_D
    UINT64_C(1145063424),	// UMLALB_ZZZ_H
    UINT64_C(1149257728),	// UMLALB_ZZZ_S
    UINT64_C(3238002704),	// UMLALL_MZZI_BtoS
    UINT64_C(3246391312),	// UMLALL_MZZI_HtoD
    UINT64_C(3240100880),	// UMLALL_MZZ_BtoS
    UINT64_C(3244295184),	// UMLALL_MZZ_HtoD
    UINT64_C(3248488464),	// UMLALL_VG2_M2Z2Z_BtoS
    UINT64_C(3252682768),	// UMLALL_VG2_M2Z2Z_HtoD
    UINT64_C(3239051280),	// UMLALL_VG2_M2ZZI_BtoS
    UINT64_C(3247439888),	// UMLALL_VG2_M2ZZI_HtoD
    UINT64_C(3240099856),	// UMLALL_VG2_M2ZZ_BtoS
    UINT64_C(3244294160),	// UMLALL_VG2_M2ZZ_HtoD
    UINT64_C(3248554000),	// UMLALL_VG4_M4Z4Z_BtoS
    UINT64_C(3252748304),	// UMLALL_VG4_M4Z4Z_HtoD
    UINT64_C(3239084048),	// UMLALL_VG4_M4ZZI_BtoS
    UINT64_C(3247472656),	// UMLALL_VG4_M4ZZI_HtoD
    UINT64_C(3241148432),	// UMLALL_VG4_M4ZZ_BtoS
    UINT64_C(3245342736),	// UMLALL_VG4_M4ZZ_HtoD
    UINT64_C(1155568640),	// UMLALT_ZZZI_D
    UINT64_C(1151374336),	// UMLALT_ZZZI_S
    UINT64_C(1153453056),	// UMLALT_ZZZ_D
    UINT64_C(1145064448),	// UMLALT_ZZZ_H
    UINT64_C(1149258752),	// UMLALT_ZZZ_S
    UINT64_C(3250589712),	// UMLAL_MZZI_HtoS
    UINT64_C(3244297232),	// UMLAL_MZZ_HtoS
    UINT64_C(3252684816),	// UMLAL_VG2_M2Z2Z_HtoS
    UINT64_C(3251638288),	// UMLAL_VG2_M2ZZI_S
    UINT64_C(3244296208),	// UMLAL_VG2_M2ZZ_HtoS
    UINT64_C(3252750352),	// UMLAL_VG4_M4Z4Z_HtoS
    UINT64_C(3251671056),	// UMLAL_VG4_M4ZZI_HtoS
    UINT64_C(3245344784),	// UMLAL_VG4_M4ZZ_HtoS
    UINT64_C(1847623680),	// UMLALv16i8_v8i16
    UINT64_C(796925952),	// UMLALv2i32_indexed
    UINT64_C(782270464),	// UMLALv2i32_v2i64
    UINT64_C(792731648),	// UMLALv4i16_indexed
    UINT64_C(778076160),	// UMLALv4i16_v4i32
    UINT64_C(1870667776),	// UMLALv4i32_indexed
    UINT64_C(1856012288),	// UMLALv4i32_v2i64
    UINT64_C(1866473472),	// UMLALv8i16_indexed
    UINT64_C(1851817984),	// UMLALv8i16_v4i32
    UINT64_C(773881856),	// UMLALv8i8_v8i16
    UINT64_C(1155575808),	// UMLSLB_ZZZI_D
    UINT64_C(1151381504),	// UMLSLB_ZZZI_S
    UINT64_C(1153456128),	// UMLSLB_ZZZ_D
    UINT64_C(1145067520),	// UMLSLB_ZZZ_H
    UINT64_C(1149261824),	// UMLSLB_ZZZ_S
    UINT64_C(3238002712),	// UMLSLL_MZZI_BtoS
    UINT64_C(3246391320),	// UMLSLL_MZZI_HtoD
    UINT64_C(3240100888),	// UMLSLL_MZZ_BtoS
    UINT64_C(3244295192),	// UMLSLL_MZZ_HtoD
    UINT64_C(3248488472),	// UMLSLL_VG2_M2Z2Z_BtoS
    UINT64_C(3252682776),	// UMLSLL_VG2_M2Z2Z_HtoD
    UINT64_C(3239051288),	// UMLSLL_VG2_M2ZZI_BtoS
    UINT64_C(3247439896),	// UMLSLL_VG2_M2ZZI_HtoD
    UINT64_C(3240099864),	// UMLSLL_VG2_M2ZZ_BtoS
    UINT64_C(3244294168),	// UMLSLL_VG2_M2ZZ_HtoD
    UINT64_C(3248554008),	// UMLSLL_VG4_M4Z4Z_BtoS
    UINT64_C(3252748312),	// UMLSLL_VG4_M4Z4Z_HtoD
    UINT64_C(3239084056),	// UMLSLL_VG4_M4ZZI_BtoS
    UINT64_C(3247472664),	// UMLSLL_VG4_M4ZZI_HtoD
    UINT64_C(3241148440),	// UMLSLL_VG4_M4ZZ_BtoS
    UINT64_C(3245342744),	// UMLSLL_VG4_M4ZZ_HtoD
    UINT64_C(1155576832),	// UMLSLT_ZZZI_D
    UINT64_C(1151382528),	// UMLSLT_ZZZI_S
    UINT64_C(1153457152),	// UMLSLT_ZZZ_D
    UINT64_C(1145068544),	// UMLSLT_ZZZ_H
    UINT64_C(1149262848),	// UMLSLT_ZZZ_S
    UINT64_C(3250589720),	// UMLSL_MZZI_HtoS
    UINT64_C(3244297240),	// UMLSL_MZZ_HtoS
    UINT64_C(3252684824),	// UMLSL_VG2_M2Z2Z_HtoS
    UINT64_C(3251638296),	// UMLSL_VG2_M2ZZI_S
    UINT64_C(3244296216),	// UMLSL_VG2_M2ZZ_HtoS
    UINT64_C(3252750360),	// UMLSL_VG4_M4Z4Z_HtoS
    UINT64_C(3251671064),	// UMLSL_VG4_M4ZZI_HtoS
    UINT64_C(3245344792),	// UMLSL_VG4_M4ZZ_HtoS
    UINT64_C(1847631872),	// UMLSLv16i8_v8i16
    UINT64_C(796942336),	// UMLSLv2i32_indexed
    UINT64_C(782278656),	// UMLSLv2i32_v2i64
    UINT64_C(792748032),	// UMLSLv4i16_indexed
    UINT64_C(778084352),	// UMLSLv4i16_v4i32
    UINT64_C(1870684160),	// UMLSLv4i32_indexed
    UINT64_C(1856020480),	// UMLSLv4i32_v2i64
    UINT64_C(1866489856),	// UMLSLv8i16_indexed
    UINT64_C(1851826176),	// UMLSLv8i16_v4i32
    UINT64_C(773890048),	// UMLSLv8i8_v8i16
    UINT64_C(1853924352),	// UMMLA
    UINT64_C(1170249728),	// UMMLA_ZZZ
    UINT64_C(2167439872),	// UMOP4A_M2Z2Z_BToS
    UINT64_C(2165342728),	// UMOP4A_M2Z2Z_HToS
    UINT64_C(2716860936),	// UMOP4A_M2Z2Z_HtoD
    UINT64_C(2166391296),	// UMOP4A_M2ZZ_BToS
    UINT64_C(2164294152),	// UMOP4A_M2ZZ_HToS
    UINT64_C(2715812360),	// UMOP4A_M2ZZ_HtoD
    UINT64_C(2167439360),	// UMOP4A_MZ2Z_BToS
    UINT64_C(2165342216),	// UMOP4A_MZ2Z_HToS
    UINT64_C(2716860424),	// UMOP4A_MZ2Z_HtoD
    UINT64_C(2166390784),	// UMOP4A_MZZ_BToS
    UINT64_C(2164293640),	// UMOP4A_MZZ_HToS
    UINT64_C(2715811848),	// UMOP4A_MZZ_HtoD
    UINT64_C(2167439888),	// UMOP4S_M2Z2Z_BToS
    UINT64_C(2165342744),	// UMOP4S_M2Z2Z_HToS
    UINT64_C(2716860952),	// UMOP4S_M2Z2Z_HtoD
    UINT64_C(2166391312),	// UMOP4S_M2ZZ_BToS
    UINT64_C(2164294168),	// UMOP4S_M2ZZ_HToS
    UINT64_C(2715812376),	// UMOP4S_M2ZZ_HtoD
    UINT64_C(2167439376),	// UMOP4S_MZ2Z_BToS
    UINT64_C(2165342232),	// UMOP4S_MZ2Z_HToS
    UINT64_C(2716860440),	// UMOP4S_MZ2Z_HtoD
    UINT64_C(2166390800),	// UMOP4S_MZZ_BToS
    UINT64_C(2164293656),	// UMOP4S_MZZ_HToS
    UINT64_C(2715811864),	// UMOP4S_MZZ_HtoD
    UINT64_C(2715811840),	// UMOPA_MPPZZ_D
    UINT64_C(2709520392),	// UMOPA_MPPZZ_HtoS
    UINT64_C(2711617536),	// UMOPA_MPPZZ_S
    UINT64_C(2715811856),	// UMOPS_MPPZZ_D
    UINT64_C(2709520408),	// UMOPS_MPPZZ_HtoS
    UINT64_C(2711617552),	// UMOPS_MPPZZ_S
    UINT64_C(235027456),	// UMOVvi16
    UINT64_C(235027456),	// UMOVvi16_idx0
    UINT64_C(235158528),	// UMOVvi32
    UINT64_C(235158528),	// UMOVvi32_idx0
    UINT64_C(1309162496),	// UMOVvi64
    UINT64_C(1309162496),	// UMOVvi64_idx0
    UINT64_C(234961920),	// UMOVvi8
    UINT64_C(234961920),	// UMOVvi8_idx0
    UINT64_C(2610987008),	// UMSUBLrrr
    UINT64_C(68354048),	// UMULH_ZPmZ_B
    UINT64_C(80936960),	// UMULH_ZPmZ_D
    UINT64_C(72548352),	// UMULH_ZPmZ_H
    UINT64_C(76742656),	// UMULH_ZPmZ_S
    UINT64_C(69233664),	// UMULH_ZZZ_B
    UINT64_C(81816576),	// UMULH_ZZZ_D
    UINT64_C(73427968),	// UMULH_ZZZ_H
    UINT64_C(77622272),	// UMULH_ZZZ_S
    UINT64_C(2613083136),	// UMULHrr
    UINT64_C(1155584000),	// UMULLB_ZZZI_D
    UINT64_C(1151389696),	// UMULLB_ZZZI_S
    UINT64_C(1170241536),	// UMULLB_ZZZ_D
    UINT64_C(1161852928),	// UMULLB_ZZZ_H
    UINT64_C(1166047232),	// UMULLB_ZZZ_S
    UINT64_C(1155585024),	// UMULLT_ZZZI_D
    UINT64_C(1151390720),	// UMULLT_ZZZI_S
    UINT64_C(1170242560),	// UMULLT_ZZZ_D
    UINT64_C(1161853952),	// UMULLT_ZZZ_H
    UINT64_C(1166048256),	// UMULLT_ZZZ_S
    UINT64_C(1847640064),	// UMULLv16i8_v8i16
    UINT64_C(796958720),	// UMULLv2i32_indexed
    UINT64_C(782286848),	// UMULLv2i32_v2i64
    UINT64_C(792764416),	// UMULLv4i16_indexed
    UINT64_C(778092544),	// UMULLv4i16_v4i32
    UINT64_C(1870700544),	// UMULLv4i32_indexed
    UINT64_C(1856028672),	// UMULLv4i32_v2i64
    UINT64_C(1866506240),	// UMULLv8i16_indexed
    UINT64_C(1851834368),	// UMULLv8i16_v4i32
    UINT64_C(773898240),	// UMULLv8i8_v8i16
    UINT64_C(623230976),	// UQADD_ZI_B
    UINT64_C(635813888),	// UQADD_ZI_D
    UINT64_C(627425280),	// UQADD_ZI_H
    UINT64_C(631619584),	// UQADD_ZI_S
    UINT64_C(1142521856),	// UQADD_ZPmZ_B
    UINT64_C(1155104768),	// UQADD_ZPmZ_D
    UINT64_C(1146716160),	// UQADD_ZPmZ_H
    UINT64_C(1150910464),	// UQADD_ZPmZ_S
    UINT64_C(69211136),	// UQADD_ZZZ_B
    UINT64_C(81794048),	// UQADD_ZZZ_D
    UINT64_C(73405440),	// UQADD_ZZZ_H
    UINT64_C(77599744),	// UQADD_ZZZ_S
    UINT64_C(1847593984),	// UQADDv16i8
    UINT64_C(2120223744),	// UQADDv1i16
    UINT64_C(2124418048),	// UQADDv1i32
    UINT64_C(2128612352),	// UQADDv1i64
    UINT64_C(2116029440),	// UQADDv1i8
    UINT64_C(782240768),	// UQADDv2i32
    UINT64_C(1860176896),	// UQADDv2i64
    UINT64_C(778046464),	// UQADDv4i16
    UINT64_C(1855982592),	// UQADDv4i32
    UINT64_C(1851788288),	// UQADDv8i16
    UINT64_C(773852160),	// UQADDv8i8
    UINT64_C(1160857600),	// UQCVTN_Z2Z_StoH
    UINT64_C(3249791072),	// UQCVTN_Z4Z_DtoH
    UINT64_C(3241402464),	// UQCVTN_Z4Z_StoB
    UINT64_C(3240353824),	// UQCVT_Z2Z_StoH
    UINT64_C(3249791008),	// UQCVT_Z4Z_DtoH
    UINT64_C(3241402400),	// UQCVT_Z4Z_StoB
    UINT64_C(69270528),	// UQDECB_WPiI
    UINT64_C(70319104),	// UQDECB_XPiI
    UINT64_C(81853440),	// UQDECD_WPiI
    UINT64_C(82902016),	// UQDECD_XPiI
    UINT64_C(81841152),	// UQDECD_ZPiI
    UINT64_C(73464832),	// UQDECH_WPiI
    UINT64_C(74513408),	// UQDECH_XPiI
    UINT64_C(73452544),	// UQDECH_ZPiI
    UINT64_C(623609856),	// UQDECP_WP_B
    UINT64_C(636192768),	// UQDECP_WP_D
    UINT64_C(627804160),	// UQDECP_WP_H
    UINT64_C(631998464),	// UQDECP_WP_S
    UINT64_C(623610880),	// UQDECP_XP_B
    UINT64_C(636193792),	// UQDECP_XP_D
    UINT64_C(627805184),	// UQDECP_XP_H
    UINT64_C(631999488),	// UQDECP_XP_S
    UINT64_C(636190720),	// UQDECP_ZP_D
    UINT64_C(627802112),	// UQDECP_ZP_H
    UINT64_C(631996416),	// UQDECP_ZP_S
    UINT64_C(77659136),	// UQDECW_WPiI
    UINT64_C(78707712),	// UQDECW_XPiI
    UINT64_C(77646848),	// UQDECW_ZPiI
    UINT64_C(69268480),	// UQINCB_WPiI
    UINT64_C(70317056),	// UQINCB_XPiI
    UINT64_C(81851392),	// UQINCD_WPiI
    UINT64_C(82899968),	// UQINCD_XPiI
    UINT64_C(81839104),	// UQINCD_ZPiI
    UINT64_C(73462784),	// UQINCH_WPiI
    UINT64_C(74511360),	// UQINCH_XPiI
    UINT64_C(73450496),	// UQINCH_ZPiI
    UINT64_C(623478784),	// UQINCP_WP_B
    UINT64_C(636061696),	// UQINCP_WP_D
    UINT64_C(627673088),	// UQINCP_WP_H
    UINT64_C(631867392),	// UQINCP_WP_S
    UINT64_C(623479808),	// UQINCP_XP_B
    UINT64_C(636062720),	// UQINCP_XP_D
    UINT64_C(627674112),	// UQINCP_XP_H
    UINT64_C(631868416),	// UQINCP_XP_S
    UINT64_C(636059648),	// UQINCP_ZP_D
    UINT64_C(627671040),	// UQINCP_ZP_H
    UINT64_C(631865344),	// UQINCP_ZP_S
    UINT64_C(77657088),	// UQINCW_WPiI
    UINT64_C(78705664),	// UQINCW_XPiI
    UINT64_C(77644800),	// UQINCW_ZPiI
    UINT64_C(1141866496),	// UQRSHLR_ZPmZ_B
    UINT64_C(1154449408),	// UQRSHLR_ZPmZ_D
    UINT64_C(1146060800),	// UQRSHLR_ZPmZ_H
    UINT64_C(1150255104),	// UQRSHLR_ZPmZ_S
    UINT64_C(1141604352),	// UQRSHL_ZPmZ_B
    UINT64_C(1154187264),	// UQRSHL_ZPmZ_D
    UINT64_C(1145798656),	// UQRSHL_ZPmZ_H
    UINT64_C(1149992960),	// UQRSHL_ZPmZ_S
    UINT64_C(1847614464),	// UQRSHLv16i8
    UINT64_C(2120244224),	// UQRSHLv1i16
    UINT64_C(2124438528),	// UQRSHLv1i32
    UINT64_C(2128632832),	// UQRSHLv1i64
    UINT64_C(2116049920),	// UQRSHLv1i8
    UINT64_C(782261248),	// UQRSHLv2i32
    UINT64_C(1860197376),	// UQRSHLv2i64
    UINT64_C(778066944),	// UQRSHLv4i16
    UINT64_C(1856003072),	// UQRSHLv4i32
    UINT64_C(1851808768),	// UQRSHLv8i16
    UINT64_C(773872640),	// UQRSHLv8i8
    UINT64_C(1160263680),	// UQRSHRNB_ZZI_B
    UINT64_C(1160787968),	// UQRSHRNB_ZZI_H
    UINT64_C(1163933696),	// UQRSHRNB_ZZI_S
    UINT64_C(1160264704),	// UQRSHRNT_ZZI_B
    UINT64_C(1160788992),	// UQRSHRNT_ZZI_H
    UINT64_C(1163934720),	// UQRSHRNT_ZZI_S
    UINT64_C(3244350496),	// UQRSHRN_VG4_Z4ZI_B
    UINT64_C(3248544800),	// UQRSHRN_VG4_Z4ZI_H
    UINT64_C(1168652288),	// UQRSHRN_Z2ZI_HtoB
    UINT64_C(1169176576),	// UQRSHRN_Z2ZI_StoH
    UINT64_C(2131270656),	// UQRSHRNb
    UINT64_C(2131794944),	// UQRSHRNh
    UINT64_C(2132843520),	// UQRSHRNs
    UINT64_C(1862835200),	// UQRSHRNv16i8_shift
    UINT64_C(790666240),	// UQRSHRNv2i32_shift
    UINT64_C(789617664),	// UQRSHRNv4i16_shift
    UINT64_C(1864408064),	// UQRSHRNv4i32_shift
    UINT64_C(1863359488),	// UQRSHRNv8i16_shift
    UINT64_C(789093376),	// UQRSHRNv8i8_shift
    UINT64_C(3252737056),	// UQRSHR_VG2_Z2ZI_H
    UINT64_C(3244349472),	// UQRSHR_VG4_Z4ZI_B
    UINT64_C(3248543776),	// UQRSHR_VG4_Z4ZI_H
    UINT64_C(1141735424),	// UQSHLR_ZPmZ_B
    UINT64_C(1154318336),	// UQSHLR_ZPmZ_D
    UINT64_C(1145929728),	// UQSHLR_ZPmZ_H
    UINT64_C(1150124032),	// UQSHLR_ZPmZ_S
    UINT64_C(67600640),	// UQSHL_ZPmI_B
    UINT64_C(75988992),	// UQSHL_ZPmI_D
    UINT64_C(67600896),	// UQSHL_ZPmI_H
    UINT64_C(71794688),	// UQSHL_ZPmI_S
    UINT64_C(1141473280),	// UQSHL_ZPmZ_B
    UINT64_C(1154056192),	// UQSHL_ZPmZ_D
    UINT64_C(1145667584),	// UQSHL_ZPmZ_H
    UINT64_C(1149861888),	// UQSHL_ZPmZ_S
    UINT64_C(2131260416),	// UQSHLb
    UINT64_C(2134930432),	// UQSHLd
    UINT64_C(2131784704),	// UQSHLh
    UINT64_C(2132833280),	// UQSHLs
    UINT64_C(1847610368),	// UQSHLv16i8
    UINT64_C(1862824960),	// UQSHLv16i8_shift
    UINT64_C(2120240128),	// UQSHLv1i16
    UINT64_C(2124434432),	// UQSHLv1i32
    UINT64_C(2128628736),	// UQSHLv1i64
    UINT64_C(2116045824),	// UQSHLv1i8
    UINT64_C(782257152),	// UQSHLv2i32
    UINT64_C(790656000),	// UQSHLv2i32_shift
    UINT64_C(1860193280),	// UQSHLv2i64
    UINT64_C(1866494976),	// UQSHLv2i64_shift
    UINT64_C(778062848),	// UQSHLv4i16
    UINT64_C(789607424),	// UQSHLv4i16_shift
    UINT64_C(1855998976),	// UQSHLv4i32
    UINT64_C(1864397824),	// UQSHLv4i32_shift
    UINT64_C(1851804672),	// UQSHLv8i16
    UINT64_C(1863349248),	// UQSHLv8i16_shift
    UINT64_C(773868544),	// UQSHLv8i8
    UINT64_C(789083136),	// UQSHLv8i8_shift
    UINT64_C(1160261632),	// UQSHRNB_ZZI_B
    UINT64_C(1160785920),	// UQSHRNB_ZZI_H
    UINT64_C(1163931648),	// UQSHRNB_ZZI_S
    UINT64_C(1160262656),	// UQSHRNT_ZZI_B
    UINT64_C(1160786944),	// UQSHRNT_ZZI_H
    UINT64_C(1163932672),	// UQSHRNT_ZZI_S
    UINT64_C(1168642048),	// UQSHRN_Z2ZI_HtoB
    UINT64_C(1169166336),	// UQSHRN_Z2ZI_StoH
    UINT64_C(2131268608),	// UQSHRNb
    UINT64_C(2131792896),	// UQSHRNh
    UINT64_C(2132841472),	// UQSHRNs
    UINT64_C(1862833152),	// UQSHRNv16i8_shift
    UINT64_C(790664192),	// UQSHRNv2i32_shift
    UINT64_C(789615616),	// UQSHRNv4i16_shift
    UINT64_C(1864406016),	// UQSHRNv4i32_shift
    UINT64_C(1863357440),	// UQSHRNv8i16_shift
    UINT64_C(789091328),	// UQSHRNv8i8_shift
    UINT64_C(1142915072),	// UQSUBR_ZPmZ_B
    UINT64_C(1155497984),	// UQSUBR_ZPmZ_D
    UINT64_C(1147109376),	// UQSUBR_ZPmZ_H
    UINT64_C(1151303680),	// UQSUBR_ZPmZ_S
    UINT64_C(623362048),	// UQSUB_ZI_B
    UINT64_C(635944960),	// UQSUB_ZI_D
    UINT64_C(627556352),	// UQSUB_ZI_H
    UINT64_C(631750656),	// UQSUB_ZI_S
    UINT64_C(1142652928),	// UQSUB_ZPmZ_B
    UINT64_C(1155235840),	// UQSUB_ZPmZ_D
    UINT64_C(1146847232),	// UQSUB_ZPmZ_H
    UINT64_C(1151041536),	// UQSUB_ZPmZ_S
    UINT64_C(69213184),	// UQSUB_ZZZ_B
    UINT64_C(81796096),	// UQSUB_ZZZ_D
    UINT64_C(73407488),	// UQSUB_ZZZ_H
    UINT64_C(77601792),	// UQSUB_ZZZ_S
    UINT64_C(1847602176),	// UQSUBv16i8
    UINT64_C(2120231936),	// UQSUBv1i16
    UINT64_C(2124426240),	// UQSUBv1i32
    UINT64_C(2128620544),	// UQSUBv1i64
    UINT64_C(2116037632),	// UQSUBv1i8
    UINT64_C(782248960),	// UQSUBv2i32
    UINT64_C(1860185088),	// UQSUBv2i64
    UINT64_C(778054656),	// UQSUBv4i16
    UINT64_C(1855990784),	// UQSUBv4i32
    UINT64_C(1851796480),	// UQSUBv8i16
    UINT64_C(773860352),	// UQSUBv8i8
    UINT64_C(1160267776),	// UQXTNB_ZZ_B
    UINT64_C(1160792064),	// UQXTNB_ZZ_H
    UINT64_C(1163937792),	// UQXTNB_ZZ_S
    UINT64_C(1160268800),	// UQXTNT_ZZ_B
    UINT64_C(1160793088),	// UQXTNT_ZZ_H
    UINT64_C(1163938816),	// UQXTNT_ZZ_S
    UINT64_C(1847674880),	// UQXTNv16i8
    UINT64_C(2120304640),	// UQXTNv1i16
    UINT64_C(2124498944),	// UQXTNv1i32
    UINT64_C(2116110336),	// UQXTNv1i8
    UINT64_C(782321664),	// UQXTNv2i32
    UINT64_C(778127360),	// UQXTNv4i16
    UINT64_C(1856063488),	// UQXTNv4i32
    UINT64_C(1851869184),	// UQXTNv8i16
    UINT64_C(773933056),	// UQXTNv8i8
    UINT64_C(1149280256),	// URECPE_ZPmZ_S
    UINT64_C(1149411328),	// URECPE_ZPzZ_S
    UINT64_C(245483520),	// URECPEv2i32
    UINT64_C(1319225344),	// URECPEv4i32
    UINT64_C(1142259712),	// URHADD_ZPmZ_B
    UINT64_C(1154842624),	// URHADD_ZPmZ_D
    UINT64_C(1146454016),	// URHADD_ZPmZ_H
    UINT64_C(1150648320),	// URHADD_ZPmZ_S
    UINT64_C(1847596032),	// URHADDv16i8
    UINT64_C(782242816),	// URHADDv2i32
    UINT64_C(778048512),	// URHADDv4i16
    UINT64_C(1855984640),	// URHADDv4i32
    UINT64_C(1851790336),	// URHADDv8i16
    UINT64_C(773854208),	// URHADDv8i8
    UINT64_C(1141342208),	// URSHLR_ZPmZ_B
    UINT64_C(1153925120),	// URSHLR_ZPmZ_D
    UINT64_C(1145536512),	// URSHLR_ZPmZ_H
    UINT64_C(1149730816),	// URSHLR_ZPmZ_S
    UINT64_C(3240145441),	// URSHL_VG2_2Z2Z_B
    UINT64_C(3252728353),	// URSHL_VG2_2Z2Z_D
    UINT64_C(3244339745),	// URSHL_VG2_2Z2Z_H
    UINT64_C(3248534049),	// URSHL_VG2_2Z2Z_S
    UINT64_C(3240141345),	// URSHL_VG2_2ZZ_B
    UINT64_C(3252724257),	// URSHL_VG2_2ZZ_D
    UINT64_C(3244335649),	// URSHL_VG2_2ZZ_H
    UINT64_C(3248529953),	// URSHL_VG2_2ZZ_S
    UINT64_C(3240147489),	// URSHL_VG4_4Z4Z_B
    UINT64_C(3252730401),	// URSHL_VG4_4Z4Z_D
    UINT64_C(3244341793),	// URSHL_VG4_4Z4Z_H
    UINT64_C(3248536097),	// URSHL_VG4_4Z4Z_S
    UINT64_C(3240143393),	// URSHL_VG4_4ZZ_B
    UINT64_C(3252726305),	// URSHL_VG4_4ZZ_D
    UINT64_C(3244337697),	// URSHL_VG4_4ZZ_H
    UINT64_C(3248532001),	// URSHL_VG4_4ZZ_S
    UINT64_C(1141080064),	// URSHL_ZPmZ_B
    UINT64_C(1153662976),	// URSHL_ZPmZ_D
    UINT64_C(1145274368),	// URSHL_ZPmZ_H
    UINT64_C(1149468672),	// URSHL_ZPmZ_S
    UINT64_C(1847612416),	// URSHLv16i8
    UINT64_C(2128630784),	// URSHLv1i64
    UINT64_C(782259200),	// URSHLv2i32
    UINT64_C(1860195328),	// URSHLv2i64
    UINT64_C(778064896),	// URSHLv4i16
    UINT64_C(1856001024),	// URSHLv4i32
    UINT64_C(1851806720),	// URSHLv8i16
    UINT64_C(773870592),	// URSHLv8i8
    UINT64_C(67993856),	// URSHR_ZPmI_B
    UINT64_C(76382208),	// URSHR_ZPmI_D
    UINT64_C(67994112),	// URSHR_ZPmI_H
    UINT64_C(72187904),	// URSHR_ZPmI_S
    UINT64_C(2134909952),	// URSHRd
    UINT64_C(1862804480),	// URSHRv16i8_shift
    UINT64_C(790635520),	// URSHRv2i32_shift
    UINT64_C(1866474496),	// URSHRv2i64_shift
    UINT64_C(789586944),	// URSHRv4i16_shift
    UINT64_C(1864377344),	// URSHRv4i32_shift
    UINT64_C(1863328768),	// URSHRv8i16_shift
    UINT64_C(789062656),	// URSHRv8i8_shift
    UINT64_C(1149345792),	// URSQRTE_ZPmZ_S
    UINT64_C(1149476864),	// URSQRTE_ZPzZ_S
    UINT64_C(782354432),	// URSQRTEv2i32
    UINT64_C(1856096256),	// URSQRTEv4i32
    UINT64_C(1158212608),	// URSRA_ZZI_B
    UINT64_C(1166076928),	// URSRA_ZZI_D
    UINT64_C(1158736896),	// URSRA_ZZI_H
    UINT64_C(1161882624),	// URSRA_ZZI_S
    UINT64_C(2134914048),	// URSRAd
    UINT64_C(1862808576),	// URSRAv16i8_shift
    UINT64_C(790639616),	// URSRAv2i32_shift
    UINT64_C(1866478592),	// URSRAv2i64_shift
    UINT64_C(789591040),	// URSRAv4i16_shift
    UINT64_C(1864381440),	// URSRAv4i32_shift
    UINT64_C(1863332864),	// URSRAv8i16_shift
    UINT64_C(789066752),	// URSRAv8i8_shift
    UINT64_C(3248493576),	// USDOT_VG2_M2Z2Z_BToS
    UINT64_C(3243249704),	// USDOT_VG2_M2ZZI_BToS
    UINT64_C(3240104968),	// USDOT_VG2_M2ZZ_BToS
    UINT64_C(3248559112),	// USDOT_VG4_M4Z4Z_BToS
    UINT64_C(3243282472),	// USDOT_VG4_M4ZZI_BToS
    UINT64_C(3241153544),	// USDOT_VG4_M4ZZ_BToS
    UINT64_C(1149270016),	// USDOT_ZZZ
    UINT64_C(1151342592),	// USDOT_ZZZI
    UINT64_C(1333850112),	// USDOTlanev16i8
    UINT64_C(260108288),	// USDOTlanev8i8
    UINT64_C(1317051392),	// USDOTv16i8
    UINT64_C(243309568),	// USDOTv8i8
    UINT64_C(1161865216),	// USHLLB_ZZI_D
    UINT64_C(1158195200),	// USHLLB_ZZI_H
    UINT64_C(1158719488),	// USHLLB_ZZI_S
    UINT64_C(1161866240),	// USHLLT_ZZI_D
    UINT64_C(1158196224),	// USHLLT_ZZI_H
    UINT64_C(1158720512),	// USHLLT_ZZI_S
    UINT64_C(1862837248),	// USHLLv16i8_shift
    UINT64_C(790668288),	// USHLLv2i32_shift
    UINT64_C(789619712),	// USHLLv4i16_shift
    UINT64_C(1864410112),	// USHLLv4i32_shift
    UINT64_C(1863361536),	// USHLLv8i16_shift
    UINT64_C(789095424),	// USHLLv8i8_shift
    UINT64_C(1847608320),	// USHLv16i8
    UINT64_C(2128626688),	// USHLv1i64
    UINT64_C(782255104),	// USHLv2i32
    UINT64_C(1860191232),	// USHLv2i64
    UINT64_C(778060800),	// USHLv4i16
    UINT64_C(1855996928),	// USHLv4i32
    UINT64_C(1851802624),	// USHLv8i16
    UINT64_C(773866496),	// USHLv8i8
    UINT64_C(2134901760),	// USHRd
    UINT64_C(1862796288),	// USHRv16i8_shift
    UINT64_C(790627328),	// USHRv2i32_shift
    UINT64_C(1866466304),	// USHRv2i64_shift
    UINT64_C(789578752),	// USHRv4i16_shift
    UINT64_C(1864369152),	// USHRv4i32_shift
    UINT64_C(1863320576),	// USHRv8i16_shift
    UINT64_C(789054464),	// USHRv8i8_shift
    UINT64_C(3238002692),	// USMLALL_MZZI_BtoS
    UINT64_C(3240100868),	// USMLALL_MZZ_BtoS
    UINT64_C(3248488452),	// USMLALL_VG2_M2Z2Z_BtoS
    UINT64_C(3239051296),	// USMLALL_VG2_M2ZZI_BtoS
    UINT64_C(3240099844),	// USMLALL_VG2_M2ZZ_BtoS
    UINT64_C(3248553988),	// USMLALL_VG4_M4Z4Z_BtoS
    UINT64_C(3239084064),	// USMLALL_VG4_M4ZZI_BtoS
    UINT64_C(3241148420),	// USMLALL_VG4_M4ZZ_BtoS
    UINT64_C(1317055488),	// USMMLA
    UINT64_C(1166055424),	// USMMLA_ZZZ
    UINT64_C(2165342720),	// USMOP4A_M2Z2Z_BToS
    UINT64_C(2714763784),	// USMOP4A_M2Z2Z_HtoD
    UINT64_C(2164294144),	// USMOP4A_M2ZZ_BToS
    UINT64_C(2713715208),	// USMOP4A_M2ZZ_HtoD
    UINT64_C(2165342208),	// USMOP4A_MZ2Z_BToS
    UINT64_C(2714763272),	// USMOP4A_MZ2Z_HtoD
    UINT64_C(2164293632),	// USMOP4A_MZZ_BToS
    UINT64_C(2713714696),	// USMOP4A_MZZ_HtoD
    UINT64_C(2165342736),	// USMOP4S_M2Z2Z_BToS
    UINT64_C(2714763800),	// USMOP4S_M2Z2Z_HtoD
    UINT64_C(2164294160),	// USMOP4S_M2ZZ_BToS
    UINT64_C(2713715224),	// USMOP4S_M2ZZ_HtoD
    UINT64_C(2165342224),	// USMOP4S_MZ2Z_BToS
    UINT64_C(2714763288),	// USMOP4S_MZ2Z_HtoD
    UINT64_C(2164293648),	// USMOP4S_MZZ_BToS
    UINT64_C(2713714712),	// USMOP4S_MZZ_HtoD
    UINT64_C(2713714688),	// USMOPA_MPPZZ_D
    UINT64_C(2709520384),	// USMOPA_MPPZZ_S
    UINT64_C(2713714704),	// USMOPS_MPPZZ_D
    UINT64_C(2709520400),	// USMOPS_MPPZZ_S
    UINT64_C(1142784000),	// USQADD_ZPmZ_B
    UINT64_C(1155366912),	// USQADD_ZPmZ_D
    UINT64_C(1146978304),	// USQADD_ZPmZ_H
    UINT64_C(1151172608),	// USQADD_ZPmZ_S
    UINT64_C(1847605248),	// USQADDv16i8
    UINT64_C(2120235008),	// USQADDv1i16
    UINT64_C(2124429312),	// USQADDv1i32
    UINT64_C(2128623616),	// USQADDv1i64
    UINT64_C(2116040704),	// USQADDv1i8
    UINT64_C(782252032),	// USQADDv2i32
    UINT64_C(1860188160),	// USQADDv2i64
    UINT64_C(778057728),	// USQADDv4i16
    UINT64_C(1855993856),	// USQADDv4i32
    UINT64_C(1851799552),	// USQADDv8i16
    UINT64_C(773863424),	// USQADDv8i8
    UINT64_C(1158210560),	// USRA_ZZI_B
    UINT64_C(1166074880),	// USRA_ZZI_D
    UINT64_C(1158734848),	// USRA_ZZI_H
    UINT64_C(1161880576),	// USRA_ZZI_S
    UINT64_C(2134905856),	// USRAd
    UINT64_C(1862800384),	// USRAv16i8_shift
    UINT64_C(790631424),	// USRAv2i32_shift
    UINT64_C(1866470400),	// USRAv2i64_shift
    UINT64_C(789582848),	// USRAv4i16_shift
    UINT64_C(1864373248),	// USRAv4i32_shift
    UINT64_C(1863324672),	// USRAv8i16_shift
    UINT64_C(789058560),	// USRAv8i8_shift
    UINT64_C(2168487936),	// USTMOPA_M2ZZZI_BtoS
    UINT64_C(1170216960),	// USUBLB_ZZZ_D
    UINT64_C(1161828352),	// USUBLB_ZZZ_H
    UINT64_C(1166022656),	// USUBLB_ZZZ_S
    UINT64_C(1170217984),	// USUBLT_ZZZ_D
    UINT64_C(1161829376),	// USUBLT_ZZZ_H
    UINT64_C(1166023680),	// USUBLT_ZZZ_S
    UINT64_C(1847599104),	// USUBLv16i8_v8i16
    UINT64_C(782245888),	// USUBLv2i32_v2i64
    UINT64_C(778051584),	// USUBLv4i16_v4i32
    UINT64_C(1855987712),	// USUBLv4i32_v2i64
    UINT64_C(1851793408),	// USUBLv8i16_v4i32
    UINT64_C(773857280),	// USUBLv8i8_v8i16
    UINT64_C(1170233344),	// USUBWB_ZZZ_D
    UINT64_C(1161844736),	// USUBWB_ZZZ_H
    UINT64_C(1166039040),	// USUBWB_ZZZ_S
    UINT64_C(1170234368),	// USUBWT_ZZZ_D
    UINT64_C(1161845760),	// USUBWT_ZZZ_H
    UINT64_C(1166040064),	// USUBWT_ZZZ_S
    UINT64_C(1847603200),	// USUBWv16i8_v8i16
    UINT64_C(782249984),	// USUBWv2i32_v2i64
    UINT64_C(778055680),	// USUBWv4i16_v4i32
    UINT64_C(1855991808),	// USUBWv4i32_v2i64
    UINT64_C(1851797504),	// USUBWv8i16_v4i32
    UINT64_C(773861376),	// USUBWv8i8_v8i16
    UINT64_C(3243278376),	// USVDOT_VG4_M4ZZI_BToS
    UINT64_C(2170585088),	// UTMOPA_M2ZZZI_BtoS
    UINT64_C(2168487944),	// UTMOPA_M2ZZZI_HtoS
    UINT64_C(99825664),	// UUNPKHI_ZZ_D
    UINT64_C(91437056),	// UUNPKHI_ZZ_H
    UINT64_C(95631360),	// UUNPKHI_ZZ_S
    UINT64_C(99760128),	// UUNPKLO_ZZ_D
    UINT64_C(91371520),	// UUNPKLO_ZZ_H
    UINT64_C(95565824),	// UUNPKLO_ZZ_S
    UINT64_C(3253067777),	// UUNPK_VG2_2ZZ_D
    UINT64_C(3244679169),	// UUNPK_VG2_2ZZ_H
    UINT64_C(3248873473),	// UUNPK_VG2_2ZZ_S
    UINT64_C(3254116353),	// UUNPK_VG4_4Z2Z_D
    UINT64_C(3245727745),	// UUNPK_VG4_4Z2Z_H
    UINT64_C(3249922049),	// UUNPK_VG4_4Z2Z_S
    UINT64_C(3243245616),	// UVDOT_VG2_M2ZZI_HtoS
    UINT64_C(3243278384),	// UVDOT_VG4_M4ZZI_BtoS
    UINT64_C(3251669016),	// UVDOT_VG4_M4ZZI_HtoD
    UINT64_C(80846848),	// UXTB_ZPmZ_D
    UINT64_C(72458240),	// UXTB_ZPmZ_H
    UINT64_C(76652544),	// UXTB_ZPmZ_S
    UINT64_C(79798272),	// UXTB_ZPzZ_D
    UINT64_C(71409664),	// UXTB_ZPzZ_H
    UINT64_C(75603968),	// UXTB_ZPzZ_S
    UINT64_C(80977920),	// UXTH_ZPmZ_D
    UINT64_C(76783616),	// UXTH_ZPmZ_S
    UINT64_C(79929344),	// UXTH_ZPzZ_D
    UINT64_C(75735040),	// UXTH_ZPzZ_S
    UINT64_C(81108992),	// UXTW_ZPmZ_D
    UINT64_C(80060416),	// UXTW_ZPzZ_D
    UINT64_C(86001664),	// UZP1_PPP_B
    UINT64_C(98584576),	// UZP1_PPP_D
    UINT64_C(90195968),	// UZP1_PPP_H
    UINT64_C(94390272),	// UZP1_PPP_S
    UINT64_C(86009856),	// UZP1_ZZZ_B
    UINT64_C(98592768),	// UZP1_ZZZ_D
    UINT64_C(90204160),	// UZP1_ZZZ_H
    UINT64_C(94373888),	// UZP1_ZZZ_Q
    UINT64_C(94398464),	// UZP1_ZZZ_S
    UINT64_C(1308628992),	// UZP1v16i8
    UINT64_C(243275776),	// UZP1v2i32
    UINT64_C(1321211904),	// UZP1v2i64
    UINT64_C(239081472),	// UZP1v4i16
    UINT64_C(1317017600),	// UZP1v4i32
    UINT64_C(1312823296),	// UZP1v8i16
    UINT64_C(234887168),	// UZP1v8i8
    UINT64_C(86002688),	// UZP2_PPP_B
    UINT64_C(98585600),	// UZP2_PPP_D
    UINT64_C(90196992),	// UZP2_PPP_H
    UINT64_C(94391296),	// UZP2_PPP_S
    UINT64_C(86010880),	// UZP2_ZZZ_B
    UINT64_C(98593792),	// UZP2_ZZZ_D
    UINT64_C(90205184),	// UZP2_ZZZ_H
    UINT64_C(94374912),	// UZP2_ZZZ_Q
    UINT64_C(94399488),	// UZP2_ZZZ_S
    UINT64_C(1308645376),	// UZP2v16i8
    UINT64_C(243292160),	// UZP2v2i32
    UINT64_C(1321228288),	// UZP2v2i64
    UINT64_C(239097856),	// UZP2v4i16
    UINT64_C(1317033984),	// UZP2v4i32
    UINT64_C(1312839680),	// UZP2v8i16
    UINT64_C(234903552),	// UZP2v8i8
    UINT64_C(1140910080),	// UZPQ1_ZZZ_B
    UINT64_C(1153492992),	// UZPQ1_ZZZ_D
    UINT64_C(1145104384),	// UZPQ1_ZZZ_H
    UINT64_C(1149298688),	// UZPQ1_ZZZ_S
    UINT64_C(1140911104),	// UZPQ2_ZZZ_B
    UINT64_C(1153494016),	// UZPQ2_ZZZ_D
    UINT64_C(1145105408),	// UZPQ2_ZZZ_H
    UINT64_C(1149299712),	// UZPQ2_ZZZ_S
    UINT64_C(3240153089),	// UZP_VG2_2ZZZ_B
    UINT64_C(3252736001),	// UZP_VG2_2ZZZ_D
    UINT64_C(3244347393),	// UZP_VG2_2ZZZ_H
    UINT64_C(3240154113),	// UZP_VG2_2ZZZ_Q
    UINT64_C(3248541697),	// UZP_VG2_2ZZZ_S
    UINT64_C(3241598978),	// UZP_VG4_4Z4Z_B
    UINT64_C(3254181890),	// UZP_VG4_4Z4Z_D
    UINT64_C(3245793282),	// UZP_VG4_4Z4Z_H
    UINT64_C(3241664514),	// UZP_VG4_4Z4Z_Q
    UINT64_C(3249987586),	// UZP_VG4_4Z4Z_S
    UINT64_C(3573747712),	// WFET
    UINT64_C(3573747744),	// WFIT
    UINT64_C(622874640),	// WHILEGE_2PXX_B
    UINT64_C(635457552),	// WHILEGE_2PXX_D
    UINT64_C(627068944),	// WHILEGE_2PXX_H
    UINT64_C(631263248),	// WHILEGE_2PXX_S
    UINT64_C(622870544),	// WHILEGE_CXX_B
    UINT64_C(635453456),	// WHILEGE_CXX_D
    UINT64_C(627064848),	// WHILEGE_CXX_H
    UINT64_C(631259152),	// WHILEGE_CXX_S
    UINT64_C(622854144),	// WHILEGE_PWW_B
    UINT64_C(635437056),	// WHILEGE_PWW_D
    UINT64_C(627048448),	// WHILEGE_PWW_H
    UINT64_C(631242752),	// WHILEGE_PWW_S
    UINT64_C(622858240),	// WHILEGE_PXX_B
    UINT64_C(635441152),	// WHILEGE_PXX_D
    UINT64_C(627052544),	// WHILEGE_PXX_H
    UINT64_C(631246848),	// WHILEGE_PXX_S
    UINT64_C(622874641),	// WHILEGT_2PXX_B
    UINT64_C(635457553),	// WHILEGT_2PXX_D
    UINT64_C(627068945),	// WHILEGT_2PXX_H
    UINT64_C(631263249),	// WHILEGT_2PXX_S
    UINT64_C(622870552),	// WHILEGT_CXX_B
    UINT64_C(635453464),	// WHILEGT_CXX_D
    UINT64_C(627064856),	// WHILEGT_CXX_H
    UINT64_C(631259160),	// WHILEGT_CXX_S
    UINT64_C(622854160),	// WHILEGT_PWW_B
    UINT64_C(635437072),	// WHILEGT_PWW_D
    UINT64_C(627048464),	// WHILEGT_PWW_H
    UINT64_C(631242768),	// WHILEGT_PWW_S
    UINT64_C(622858256),	// WHILEGT_PXX_B
    UINT64_C(635441168),	// WHILEGT_PXX_D
    UINT64_C(627052560),	// WHILEGT_PXX_H
    UINT64_C(631246864),	// WHILEGT_PXX_S
    UINT64_C(622876689),	// WHILEHI_2PXX_B
    UINT64_C(635459601),	// WHILEHI_2PXX_D
    UINT64_C(627070993),	// WHILEHI_2PXX_H
    UINT64_C(631265297),	// WHILEHI_2PXX_S
    UINT64_C(622872600),	// WHILEHI_CXX_B
    UINT64_C(635455512),	// WHILEHI_CXX_D
    UINT64_C(627066904),	// WHILEHI_CXX_H
    UINT64_C(631261208),	// WHILEHI_CXX_S
    UINT64_C(622856208),	// WHILEHI_PWW_B
    UINT64_C(635439120),	// WHILEHI_PWW_D
    UINT64_C(627050512),	// WHILEHI_PWW_H
    UINT64_C(631244816),	// WHILEHI_PWW_S
    UINT64_C(622860304),	// WHILEHI_PXX_B
    UINT64_C(635443216),	// WHILEHI_PXX_D
    UINT64_C(627054608),	// WHILEHI_PXX_H
    UINT64_C(631248912),	// WHILEHI_PXX_S
    UINT64_C(622876688),	// WHILEHS_2PXX_B
    UINT64_C(635459600),	// WHILEHS_2PXX_D
    UINT64_C(627070992),	// WHILEHS_2PXX_H
    UINT64_C(631265296),	// WHILEHS_2PXX_S
    UINT64_C(622872592),	// WHILEHS_CXX_B
    UINT64_C(635455504),	// WHILEHS_CXX_D
    UINT64_C(627066896),	// WHILEHS_CXX_H
    UINT64_C(631261200),	// WHILEHS_CXX_S
    UINT64_C(622856192),	// WHILEHS_PWW_B
    UINT64_C(635439104),	// WHILEHS_PWW_D
    UINT64_C(627050496),	// WHILEHS_PWW_H
    UINT64_C(631244800),	// WHILEHS_PWW_S
    UINT64_C(622860288),	// WHILEHS_PXX_B
    UINT64_C(635443200),	// WHILEHS_PXX_D
    UINT64_C(627054592),	// WHILEHS_PXX_H
    UINT64_C(631248896),	// WHILEHS_PXX_S
    UINT64_C(622875665),	// WHILELE_2PXX_B
    UINT64_C(635458577),	// WHILELE_2PXX_D
    UINT64_C(627069969),	// WHILELE_2PXX_H
    UINT64_C(631264273),	// WHILELE_2PXX_S
    UINT64_C(622871576),	// WHILELE_CXX_B
    UINT64_C(635454488),	// WHILELE_CXX_D
    UINT64_C(627065880),	// WHILELE_CXX_H
    UINT64_C(631260184),	// WHILELE_CXX_S
    UINT64_C(622855184),	// WHILELE_PWW_B
    UINT64_C(635438096),	// WHILELE_PWW_D
    UINT64_C(627049488),	// WHILELE_PWW_H
    UINT64_C(631243792),	// WHILELE_PWW_S
    UINT64_C(622859280),	// WHILELE_PXX_B
    UINT64_C(635442192),	// WHILELE_PXX_D
    UINT64_C(627053584),	// WHILELE_PXX_H
    UINT64_C(631247888),	// WHILELE_PXX_S
    UINT64_C(622877712),	// WHILELO_2PXX_B
    UINT64_C(635460624),	// WHILELO_2PXX_D
    UINT64_C(627072016),	// WHILELO_2PXX_H
    UINT64_C(631266320),	// WHILELO_2PXX_S
    UINT64_C(622873616),	// WHILELO_CXX_B
    UINT64_C(635456528),	// WHILELO_CXX_D
    UINT64_C(627067920),	// WHILELO_CXX_H
    UINT64_C(631262224),	// WHILELO_CXX_S
    UINT64_C(622857216),	// WHILELO_PWW_B
    UINT64_C(635440128),	// WHILELO_PWW_D
    UINT64_C(627051520),	// WHILELO_PWW_H
    UINT64_C(631245824),	// WHILELO_PWW_S
    UINT64_C(622861312),	// WHILELO_PXX_B
    UINT64_C(635444224),	// WHILELO_PXX_D
    UINT64_C(627055616),	// WHILELO_PXX_H
    UINT64_C(631249920),	// WHILELO_PXX_S
    UINT64_C(622877713),	// WHILELS_2PXX_B
    UINT64_C(635460625),	// WHILELS_2PXX_D
    UINT64_C(627072017),	// WHILELS_2PXX_H
    UINT64_C(631266321),	// WHILELS_2PXX_S
    UINT64_C(622873624),	// WHILELS_CXX_B
    UINT64_C(635456536),	// WHILELS_CXX_D
    UINT64_C(627067928),	// WHILELS_CXX_H
    UINT64_C(631262232),	// WHILELS_CXX_S
    UINT64_C(622857232),	// WHILELS_PWW_B
    UINT64_C(635440144),	// WHILELS_PWW_D
    UINT64_C(627051536),	// WHILELS_PWW_H
    UINT64_C(631245840),	// WHILELS_PWW_S
    UINT64_C(622861328),	// WHILELS_PXX_B
    UINT64_C(635444240),	// WHILELS_PXX_D
    UINT64_C(627055632),	// WHILELS_PXX_H
    UINT64_C(631249936),	// WHILELS_PXX_S
    UINT64_C(622875664),	// WHILELT_2PXX_B
    UINT64_C(635458576),	// WHILELT_2PXX_D
    UINT64_C(627069968),	// WHILELT_2PXX_H
    UINT64_C(631264272),	// WHILELT_2PXX_S
    UINT64_C(622871568),	// WHILELT_CXX_B
    UINT64_C(635454480),	// WHILELT_CXX_D
    UINT64_C(627065872),	// WHILELT_CXX_H
    UINT64_C(631260176),	// WHILELT_CXX_S
    UINT64_C(622855168),	// WHILELT_PWW_B
    UINT64_C(635438080),	// WHILELT_PWW_D
    UINT64_C(627049472),	// WHILELT_PWW_H
    UINT64_C(631243776),	// WHILELT_PWW_S
    UINT64_C(622859264),	// WHILELT_PXX_B
    UINT64_C(635442176),	// WHILELT_PXX_D
    UINT64_C(627053568),	// WHILELT_PXX_H
    UINT64_C(631247872),	// WHILELT_PXX_S
    UINT64_C(622866448),	// WHILERW_PXX_B
    UINT64_C(635449360),	// WHILERW_PXX_D
    UINT64_C(627060752),	// WHILERW_PXX_H
    UINT64_C(631255056),	// WHILERW_PXX_S
    UINT64_C(622866432),	// WHILEWR_PXX_B
    UINT64_C(635449344),	// WHILEWR_PXX_D
    UINT64_C(627060736),	// WHILEWR_PXX_H
    UINT64_C(631255040),	// WHILEWR_PXX_S
    UINT64_C(623415296),	// WRFFR
    UINT64_C(3573563455),	// XAFLAG
    UINT64_C(3464495104),	// XAR
    UINT64_C(69743616),	// XAR_ZZZI_B
    UINT64_C(77607936),	// XAR_ZZZI_D
    UINT64_C(70267904),	// XAR_ZZZI_H
    UINT64_C(73413632),	// XAR_ZZZI_S
    UINT64_C(3670099936),	// XPACD
    UINT64_C(3670098912),	// XPACI
    UINT64_C(3573752063),	// XPACLRI
    UINT64_C(1310795776),	// XTNv16i8
    UINT64_C(245442560),	// XTNv2i32
    UINT64_C(241248256),	// XTNv4i16
    UINT64_C(1319184384),	// XTNv4i32
    UINT64_C(1314990080),	// XTNv8i16
    UINT64_C(237053952),	// XTNv8i8
    UINT64_C(3221749760),	// ZERO_M
    UINT64_C(3222044672),	// ZERO_MXI_2Z
    UINT64_C(3222175744),	// ZERO_MXI_4Z
    UINT64_C(3222077440),	// ZERO_MXI_VG2_2Z
    UINT64_C(3222208512),	// ZERO_MXI_VG2_4Z
    UINT64_C(3222011904),	// ZERO_MXI_VG2_Z
    UINT64_C(3222110208),	// ZERO_MXI_VG4_2Z
    UINT64_C(3222241280),	// ZERO_MXI_VG4_4Z
    UINT64_C(3222142976),	// ZERO_MXI_VG4_Z
    UINT64_C(3225944065),	// ZERO_T
    UINT64_C(85999616),	// ZIP1_PPP_B
    UINT64_C(98582528),	// ZIP1_PPP_D
    UINT64_C(90193920),	// ZIP1_PPP_H
    UINT64_C(94388224),	// ZIP1_PPP_S
    UINT64_C(86007808),	// ZIP1_ZZZ_B
    UINT64_C(98590720),	// ZIP1_ZZZ_D
    UINT64_C(90202112),	// ZIP1_ZZZ_H
    UINT64_C(94371840),	// ZIP1_ZZZ_Q
    UINT64_C(94396416),	// ZIP1_ZZZ_S
    UINT64_C(1308637184),	// ZIP1v16i8
    UINT64_C(243283968),	// ZIP1v2i32
    UINT64_C(1321220096),	// ZIP1v2i64
    UINT64_C(239089664),	// ZIP1v4i16
    UINT64_C(1317025792),	// ZIP1v4i32
    UINT64_C(1312831488),	// ZIP1v8i16
    UINT64_C(234895360),	// ZIP1v8i8
    UINT64_C(86000640),	// ZIP2_PPP_B
    UINT64_C(98583552),	// ZIP2_PPP_D
    UINT64_C(90194944),	// ZIP2_PPP_H
    UINT64_C(94389248),	// ZIP2_PPP_S
    UINT64_C(86008832),	// ZIP2_ZZZ_B
    UINT64_C(98591744),	// ZIP2_ZZZ_D
    UINT64_C(90203136),	// ZIP2_ZZZ_H
    UINT64_C(94372864),	// ZIP2_ZZZ_Q
    UINT64_C(94397440),	// ZIP2_ZZZ_S
    UINT64_C(1308653568),	// ZIP2v16i8
    UINT64_C(243300352),	// ZIP2v2i32
    UINT64_C(1321236480),	// ZIP2v2i64
    UINT64_C(239106048),	// ZIP2v4i16
    UINT64_C(1317042176),	// ZIP2v4i32
    UINT64_C(1312847872),	// ZIP2v8i16
    UINT64_C(234911744),	// ZIP2v8i8
    UINT64_C(1140908032),	// ZIPQ1_ZZZ_B
    UINT64_C(1153490944),	// ZIPQ1_ZZZ_D
    UINT64_C(1145102336),	// ZIPQ1_ZZZ_H
    UINT64_C(1149296640),	// ZIPQ1_ZZZ_S
    UINT64_C(1140909056),	// ZIPQ2_ZZZ_B
    UINT64_C(1153491968),	// ZIPQ2_ZZZ_D
    UINT64_C(1145103360),	// ZIPQ2_ZZZ_H
    UINT64_C(1149297664),	// ZIPQ2_ZZZ_S
    UINT64_C(3240153088),	// ZIP_VG2_2ZZZ_B
    UINT64_C(3252736000),	// ZIP_VG2_2ZZZ_D
    UINT64_C(3244347392),	// ZIP_VG2_2ZZZ_H
    UINT64_C(3240154112),	// ZIP_VG2_2ZZZ_Q
    UINT64_C(3248541696),	// ZIP_VG2_2ZZZ_S
    UINT64_C(3241598976),	// ZIP_VG4_4Z4Z_B
    UINT64_C(3254181888),	// ZIP_VG4_4Z4Z_D
    UINT64_C(3245793280),	// ZIP_VG4_4Z4Z_H
    UINT64_C(3241664512),	// ZIP_VG4_4Z4Z_Q
    UINT64_C(3249987584),	// ZIP_VG4_4Z4Z_S
  };
  constexpr unsigned FirstSupportedOpcode = 1644;

  const unsigned opcode = MI.getOpcode();
  if (opcode < FirstSupportedOpcode)
    reportUnsupportedInst(MI);
  unsigned TableIndex = opcode - FirstSupportedOpcode;
  uint64_t Value = InstBits[TableIndex];
  uint64_t op = 0;
  (void)op;  // suppress warning
  switch (opcode) {
    case AArch64::AUTIA1716:
    case AArch64::AUTIA171615:
    case AArch64::AUTIASP:
    case AArch64::AUTIAZ:
    case AArch64::AUTIB1716:
    case AArch64::AUTIB171615:
    case AArch64::AUTIBSP:
    case AArch64::AUTIBZ:
    case AArch64::AXFLAG:
    case AArch64::BRB_IALL:
    case AArch64::BRB_INJ:
    case AArch64::CFINV:
    case AArch64::CHKFEAT:
    case AArch64::DRPS:
    case AArch64::ERET:
    case AArch64::ERETAA:
    case AArch64::ERETAB:
    case AArch64::GCSPOPCX:
    case AArch64::GCSPOPX:
    case AArch64::GCSPUSHX:
    case AArch64::NOP:
    case AArch64::PACIA1716:
    case AArch64::PACIA171615:
    case AArch64::PACIASP:
    case AArch64::PACIASPPC:
    case AArch64::PACIAZ:
    case AArch64::PACIB1716:
    case AArch64::PACIB171615:
    case AArch64::PACIBSP:
    case AArch64::PACIBSPPC:
    case AArch64::PACIBZ:
    case AArch64::PACM:
    case AArch64::PACNBIASPPC:
    case AArch64::PACNBIBSPPC:
    case AArch64::RETAA:
    case AArch64::RETAB:
    case AArch64::SB:
    case AArch64::SETFFR:
    case AArch64::STCPH:
    case AArch64::TSB:
    case AArch64::XAFLAG:
    case AArch64::XPACLRI:
    case AArch64::ZERO_T: {
      break;
    }
    case AArch64::DSBnXS: {
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xc) << 8;
      break;
    }
    case AArch64::CLREX:
    case AArch64::DMB:
    case AArch64::DSB:
    case AArch64::ISB: {
      // op: CRm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf) << 8;
      break;
    }
    case AArch64::PTRUE_C_B:
    case AArch64::PTRUE_C_D:
    case AArch64::PTRUE_C_H:
    case AArch64::PTRUE_C_S: {
      // op: PNd
      op = EncodePNR_p8to15(MI, 0, Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::WHILEGE_CXX_B:
    case AArch64::WHILEGE_CXX_D:
    case AArch64::WHILEGE_CXX_H:
    case AArch64::WHILEGE_CXX_S:
    case AArch64::WHILEGT_CXX_B:
    case AArch64::WHILEGT_CXX_D:
    case AArch64::WHILEGT_CXX_H:
    case AArch64::WHILEGT_CXX_S:
    case AArch64::WHILEHI_CXX_B:
    case AArch64::WHILEHI_CXX_D:
    case AArch64::WHILEHI_CXX_H:
    case AArch64::WHILEHI_CXX_S:
    case AArch64::WHILEHS_CXX_B:
    case AArch64::WHILEHS_CXX_D:
    case AArch64::WHILEHS_CXX_H:
    case AArch64::WHILEHS_CXX_S:
    case AArch64::WHILELE_CXX_B:
    case AArch64::WHILELE_CXX_D:
    case AArch64::WHILELE_CXX_H:
    case AArch64::WHILELE_CXX_S:
    case AArch64::WHILELO_CXX_B:
    case AArch64::WHILELO_CXX_D:
    case AArch64::WHILELO_CXX_H:
    case AArch64::WHILELO_CXX_S:
    case AArch64::WHILELS_CXX_B:
    case AArch64::WHILELS_CXX_D:
    case AArch64::WHILELS_CXX_H:
    case AArch64::WHILELS_CXX_S:
    case AArch64::WHILELT_CXX_B:
    case AArch64::WHILELT_CXX_D:
    case AArch64::WHILELT_CXX_H:
    case AArch64::WHILELT_CXX_S: {
      // op: PNd
      op = EncodePNR_p8to15(MI, 0, Fixups, STI);
      Value |= (op & 0x7);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: vl
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 13;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SEL_VG2_2ZC2Z2Z_B:
    case AArch64::SEL_VG2_2ZC2Z2Z_D:
    case AArch64::SEL_VG2_2ZC2Z2Z_H:
    case AArch64::SEL_VG2_2ZC2Z2Z_S: {
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zm
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 17;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::SEL_VG4_4ZC4Z4Z_B:
    case AArch64::SEL_VG4_4ZC4Z4Z_D:
    case AArch64::SEL_VG4_4ZC4Z4Z_H:
    case AArch64::SEL_VG4_4ZC4Z4Z_S: {
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zm
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case AArch64::WHILEGE_2PXX_B:
    case AArch64::WHILEGE_2PXX_D:
    case AArch64::WHILEGE_2PXX_H:
    case AArch64::WHILEGE_2PXX_S:
    case AArch64::WHILEGT_2PXX_B:
    case AArch64::WHILEGT_2PXX_D:
    case AArch64::WHILEGT_2PXX_H:
    case AArch64::WHILEGT_2PXX_S:
    case AArch64::WHILEHI_2PXX_B:
    case AArch64::WHILEHI_2PXX_D:
    case AArch64::WHILEHI_2PXX_H:
    case AArch64::WHILEHI_2PXX_S:
    case AArch64::WHILEHS_2PXX_B:
    case AArch64::WHILEHS_2PXX_D:
    case AArch64::WHILEHS_2PXX_H:
    case AArch64::WHILEHS_2PXX_S:
    case AArch64::WHILELE_2PXX_B:
    case AArch64::WHILELE_2PXX_D:
    case AArch64::WHILELE_2PXX_H:
    case AArch64::WHILELE_2PXX_S:
    case AArch64::WHILELO_2PXX_B:
    case AArch64::WHILELO_2PXX_D:
    case AArch64::WHILELO_2PXX_H:
    case AArch64::WHILELO_2PXX_S:
    case AArch64::WHILELS_2PXX_B:
    case AArch64::WHILELS_2PXX_D:
    case AArch64::WHILELS_2PXX_H:
    case AArch64::WHILELS_2PXX_S:
    case AArch64::WHILELT_2PXX_B:
    case AArch64::WHILELT_2PXX_D:
    case AArch64::WHILELT_2PXX_H:
    case AArch64::WHILELT_2PXX_S: {
      // op: Pd
      op = EncodeRegMul_MinMax<2, 0, 14>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 1;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::PFALSE:
    case AArch64::RDFFR_P: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::PEXT_2PCI_B:
    case AArch64::PEXT_2PCI_D:
    case AArch64::PEXT_2PCI_H:
    case AArch64::PEXT_2PCI_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: PNn
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 8;
      break;
    }
    case AArch64::PEXT_PCI_B:
    case AArch64::PEXT_PCI_D:
    case AArch64::PEXT_PCI_H:
    case AArch64::PEXT_PCI_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: PNn
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 8;
      break;
    }
    case AArch64::CMPEQ_PPzZZ_B:
    case AArch64::CMPEQ_PPzZZ_D:
    case AArch64::CMPEQ_PPzZZ_H:
    case AArch64::CMPEQ_PPzZZ_S:
    case AArch64::CMPEQ_WIDE_PPzZZ_B:
    case AArch64::CMPEQ_WIDE_PPzZZ_H:
    case AArch64::CMPEQ_WIDE_PPzZZ_S:
    case AArch64::CMPGE_PPzZZ_B:
    case AArch64::CMPGE_PPzZZ_D:
    case AArch64::CMPGE_PPzZZ_H:
    case AArch64::CMPGE_PPzZZ_S:
    case AArch64::CMPGE_WIDE_PPzZZ_B:
    case AArch64::CMPGE_WIDE_PPzZZ_H:
    case AArch64::CMPGE_WIDE_PPzZZ_S:
    case AArch64::CMPGT_PPzZZ_B:
    case AArch64::CMPGT_PPzZZ_D:
    case AArch64::CMPGT_PPzZZ_H:
    case AArch64::CMPGT_PPzZZ_S:
    case AArch64::CMPGT_WIDE_PPzZZ_B:
    case AArch64::CMPGT_WIDE_PPzZZ_H:
    case AArch64::CMPGT_WIDE_PPzZZ_S:
    case AArch64::CMPHI_PPzZZ_B:
    case AArch64::CMPHI_PPzZZ_D:
    case AArch64::CMPHI_PPzZZ_H:
    case AArch64::CMPHI_PPzZZ_S:
    case AArch64::CMPHI_WIDE_PPzZZ_B:
    case AArch64::CMPHI_WIDE_PPzZZ_H:
    case AArch64::CMPHI_WIDE_PPzZZ_S:
    case AArch64::CMPHS_PPzZZ_B:
    case AArch64::CMPHS_PPzZZ_D:
    case AArch64::CMPHS_PPzZZ_H:
    case AArch64::CMPHS_PPzZZ_S:
    case AArch64::CMPHS_WIDE_PPzZZ_B:
    case AArch64::CMPHS_WIDE_PPzZZ_H:
    case AArch64::CMPHS_WIDE_PPzZZ_S:
    case AArch64::CMPLE_WIDE_PPzZZ_B:
    case AArch64::CMPLE_WIDE_PPzZZ_H:
    case AArch64::CMPLE_WIDE_PPzZZ_S:
    case AArch64::CMPLO_WIDE_PPzZZ_B:
    case AArch64::CMPLO_WIDE_PPzZZ_H:
    case AArch64::CMPLO_WIDE_PPzZZ_S:
    case AArch64::CMPLS_WIDE_PPzZZ_B:
    case AArch64::CMPLS_WIDE_PPzZZ_H:
    case AArch64::CMPLS_WIDE_PPzZZ_S:
    case AArch64::CMPLT_WIDE_PPzZZ_B:
    case AArch64::CMPLT_WIDE_PPzZZ_H:
    case AArch64::CMPLT_WIDE_PPzZZ_S:
    case AArch64::CMPNE_PPzZZ_B:
    case AArch64::CMPNE_PPzZZ_D:
    case AArch64::CMPNE_PPzZZ_H:
    case AArch64::CMPNE_PPzZZ_S:
    case AArch64::CMPNE_WIDE_PPzZZ_B:
    case AArch64::CMPNE_WIDE_PPzZZ_H:
    case AArch64::CMPNE_WIDE_PPzZZ_S:
    case AArch64::FACGE_PPzZZ_D:
    case AArch64::FACGE_PPzZZ_H:
    case AArch64::FACGE_PPzZZ_S:
    case AArch64::FACGT_PPzZZ_D:
    case AArch64::FACGT_PPzZZ_H:
    case AArch64::FACGT_PPzZZ_S:
    case AArch64::FCMEQ_PPzZZ_D:
    case AArch64::FCMEQ_PPzZZ_H:
    case AArch64::FCMEQ_PPzZZ_S:
    case AArch64::FCMGE_PPzZZ_D:
    case AArch64::FCMGE_PPzZZ_H:
    case AArch64::FCMGE_PPzZZ_S:
    case AArch64::FCMGT_PPzZZ_D:
    case AArch64::FCMGT_PPzZZ_H:
    case AArch64::FCMGT_PPzZZ_S:
    case AArch64::FCMNE_PPzZZ_D:
    case AArch64::FCMNE_PPzZZ_H:
    case AArch64::FCMNE_PPzZZ_S:
    case AArch64::FCMUO_PPzZZ_D:
    case AArch64::FCMUO_PPzZZ_H:
    case AArch64::FCMUO_PPzZZ_S:
    case AArch64::MATCH_PPzZZ_B:
    case AArch64::MATCH_PPzZZ_H:
    case AArch64::NMATCH_PPzZZ_B:
    case AArch64::NMATCH_PPzZZ_H: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::FCMEQ_PPzZ0_D:
    case AArch64::FCMEQ_PPzZ0_H:
    case AArch64::FCMEQ_PPzZ0_S:
    case AArch64::FCMGE_PPzZ0_D:
    case AArch64::FCMGE_PPzZ0_H:
    case AArch64::FCMGE_PPzZ0_S:
    case AArch64::FCMGT_PPzZ0_D:
    case AArch64::FCMGT_PPzZ0_H:
    case AArch64::FCMGT_PPzZ0_S:
    case AArch64::FCMLE_PPzZ0_D:
    case AArch64::FCMLE_PPzZ0_H:
    case AArch64::FCMLE_PPzZ0_S:
    case AArch64::FCMLT_PPzZ0_D:
    case AArch64::FCMLT_PPzZ0_H:
    case AArch64::FCMLT_PPzZ0_S:
    case AArch64::FCMNE_PPzZ0_D:
    case AArch64::FCMNE_PPzZ0_H:
    case AArch64::FCMNE_PPzZ0_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::CMPEQ_PPzZI_B:
    case AArch64::CMPEQ_PPzZI_D:
    case AArch64::CMPEQ_PPzZI_H:
    case AArch64::CMPEQ_PPzZI_S:
    case AArch64::CMPGE_PPzZI_B:
    case AArch64::CMPGE_PPzZI_D:
    case AArch64::CMPGE_PPzZI_H:
    case AArch64::CMPGE_PPzZI_S:
    case AArch64::CMPGT_PPzZI_B:
    case AArch64::CMPGT_PPzZI_D:
    case AArch64::CMPGT_PPzZI_H:
    case AArch64::CMPGT_PPzZI_S:
    case AArch64::CMPLE_PPzZI_B:
    case AArch64::CMPLE_PPzZI_D:
    case AArch64::CMPLE_PPzZI_H:
    case AArch64::CMPLE_PPzZI_S:
    case AArch64::CMPLT_PPzZI_B:
    case AArch64::CMPLT_PPzZI_D:
    case AArch64::CMPLT_PPzZI_H:
    case AArch64::CMPLT_PPzZI_S:
    case AArch64::CMPNE_PPzZI_B:
    case AArch64::CMPNE_PPzZI_D:
    case AArch64::CMPNE_PPzZI_H:
    case AArch64::CMPNE_PPzZI_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::CMPHI_PPzZI_B:
    case AArch64::CMPHI_PPzZI_D:
    case AArch64::CMPHI_PPzZI_H:
    case AArch64::CMPHI_PPzZI_S:
    case AArch64::CMPHS_PPzZI_B:
    case AArch64::CMPHS_PPzZI_D:
    case AArch64::CMPHS_PPzZI_H:
    case AArch64::CMPHS_PPzZI_S:
    case AArch64::CMPLO_PPzZI_B:
    case AArch64::CMPLO_PPzZI_D:
    case AArch64::CMPLO_PPzZI_H:
    case AArch64::CMPLO_PPzZI_S:
    case AArch64::CMPLS_PPzZI_B:
    case AArch64::CMPLS_PPzZI_D:
    case AArch64::CMPLS_PPzZI_H:
    case AArch64::CMPLS_PPzZI_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm7
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7f) << 14;
      break;
    }
    case AArch64::ANDS_PPzPP:
    case AArch64::AND_PPzPP:
    case AArch64::BICS_PPzPP:
    case AArch64::BIC_PPzPP:
    case AArch64::BRKPAS_PPzPP:
    case AArch64::BRKPA_PPzPP:
    case AArch64::BRKPBS_PPzPP:
    case AArch64::BRKPB_PPzPP:
    case AArch64::EORS_PPzPP:
    case AArch64::EOR_PPzPP:
    case AArch64::NANDS_PPzPP:
    case AArch64::NAND_PPzPP:
    case AArch64::NORS_PPzPP:
    case AArch64::NOR_PPzPP:
    case AArch64::ORNS_PPzPP:
    case AArch64::ORN_PPzPP:
    case AArch64::ORRS_PPzPP:
    case AArch64::ORR_PPzPP:
    case AArch64::SEL_PPPP: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::BRKAS_PPzP:
    case AArch64::BRKA_PPzP:
    case AArch64::BRKBS_PPzP:
    case AArch64::BRKB_PPzP: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::RDFFRS_PPz:
    case AArch64::RDFFR_PPz: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::BRKA_PPmP:
    case AArch64::BRKB_PPmP: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::TRN1_PPP_B:
    case AArch64::TRN1_PPP_D:
    case AArch64::TRN1_PPP_H:
    case AArch64::TRN1_PPP_S:
    case AArch64::TRN2_PPP_B:
    case AArch64::TRN2_PPP_D:
    case AArch64::TRN2_PPP_H:
    case AArch64::TRN2_PPP_S:
    case AArch64::UZP1_PPP_B:
    case AArch64::UZP1_PPP_D:
    case AArch64::UZP1_PPP_H:
    case AArch64::UZP1_PPP_S:
    case AArch64::UZP2_PPP_B:
    case AArch64::UZP2_PPP_D:
    case AArch64::UZP2_PPP_H:
    case AArch64::UZP2_PPP_S:
    case AArch64::ZIP1_PPP_B:
    case AArch64::ZIP1_PPP_D:
    case AArch64::ZIP1_PPP_H:
    case AArch64::ZIP1_PPP_S:
    case AArch64::ZIP2_PPP_B:
    case AArch64::ZIP2_PPP_D:
    case AArch64::ZIP2_PPP_H:
    case AArch64::ZIP2_PPP_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::PUNPKHI_PP:
    case AArch64::PUNPKLO_PP:
    case AArch64::REV_PP_B:
    case AArch64::REV_PP_D:
    case AArch64::REV_PP_H:
    case AArch64::REV_PP_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::WHILEGE_PWW_B:
    case AArch64::WHILEGE_PWW_D:
    case AArch64::WHILEGE_PWW_H:
    case AArch64::WHILEGE_PWW_S:
    case AArch64::WHILEGE_PXX_B:
    case AArch64::WHILEGE_PXX_D:
    case AArch64::WHILEGE_PXX_H:
    case AArch64::WHILEGE_PXX_S:
    case AArch64::WHILEGT_PWW_B:
    case AArch64::WHILEGT_PWW_D:
    case AArch64::WHILEGT_PWW_H:
    case AArch64::WHILEGT_PWW_S:
    case AArch64::WHILEGT_PXX_B:
    case AArch64::WHILEGT_PXX_D:
    case AArch64::WHILEGT_PXX_H:
    case AArch64::WHILEGT_PXX_S:
    case AArch64::WHILEHI_PWW_B:
    case AArch64::WHILEHI_PWW_D:
    case AArch64::WHILEHI_PWW_H:
    case AArch64::WHILEHI_PWW_S:
    case AArch64::WHILEHI_PXX_B:
    case AArch64::WHILEHI_PXX_D:
    case AArch64::WHILEHI_PXX_H:
    case AArch64::WHILEHI_PXX_S:
    case AArch64::WHILEHS_PWW_B:
    case AArch64::WHILEHS_PWW_D:
    case AArch64::WHILEHS_PWW_H:
    case AArch64::WHILEHS_PWW_S:
    case AArch64::WHILEHS_PXX_B:
    case AArch64::WHILEHS_PXX_D:
    case AArch64::WHILEHS_PXX_H:
    case AArch64::WHILEHS_PXX_S:
    case AArch64::WHILELE_PWW_B:
    case AArch64::WHILELE_PWW_D:
    case AArch64::WHILELE_PWW_H:
    case AArch64::WHILELE_PWW_S:
    case AArch64::WHILELE_PXX_B:
    case AArch64::WHILELE_PXX_D:
    case AArch64::WHILELE_PXX_H:
    case AArch64::WHILELE_PXX_S:
    case AArch64::WHILELO_PWW_B:
    case AArch64::WHILELO_PWW_D:
    case AArch64::WHILELO_PWW_H:
    case AArch64::WHILELO_PWW_S:
    case AArch64::WHILELO_PXX_B:
    case AArch64::WHILELO_PXX_D:
    case AArch64::WHILELO_PXX_H:
    case AArch64::WHILELO_PXX_S:
    case AArch64::WHILELS_PWW_B:
    case AArch64::WHILELS_PWW_D:
    case AArch64::WHILELS_PWW_H:
    case AArch64::WHILELS_PWW_S:
    case AArch64::WHILELS_PXX_B:
    case AArch64::WHILELS_PXX_D:
    case AArch64::WHILELS_PXX_H:
    case AArch64::WHILELS_PXX_S:
    case AArch64::WHILELT_PWW_B:
    case AArch64::WHILELT_PWW_D:
    case AArch64::WHILELT_PWW_H:
    case AArch64::WHILELT_PWW_S:
    case AArch64::WHILELT_PXX_B:
    case AArch64::WHILELT_PXX_D:
    case AArch64::WHILELT_PXX_H:
    case AArch64::WHILELT_PXX_S:
    case AArch64::WHILERW_PXX_B:
    case AArch64::WHILERW_PXX_D:
    case AArch64::WHILERW_PXX_H:
    case AArch64::WHILERW_PXX_S:
    case AArch64::WHILEWR_PXX_B:
    case AArch64::WHILEWR_PXX_D:
    case AArch64::WHILEWR_PXX_H:
    case AArch64::WHILEWR_PXX_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::PMOV_PZI_B: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::PMOV_PZI_H: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 17;
      break;
    }
    case AArch64::PMOV_PZI_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 17;
      break;
    }
    case AArch64::PMOV_PZI_D: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x4) << 20;
      Value |= (op & 0x3) << 17;
      break;
    }
    case AArch64::PTRUES_B:
    case AArch64::PTRUES_D:
    case AArch64::PTRUES_H:
    case AArch64::PTRUES_S:
    case AArch64::PTRUE_B:
    case AArch64::PTRUE_D:
    case AArch64::PTRUE_H:
    case AArch64::PTRUE_S: {
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: pattern
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::BRKNS_PPzP:
    case AArch64::BRKN_PPzP: {
      // op: Pdm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::PFIRST_B:
    case AArch64::PNEXT_B:
    case AArch64::PNEXT_D:
    case AArch64::PNEXT_H:
    case AArch64::PNEXT_S: {
      // op: Pdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::PTEST_PP: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::LASTA_RPZ_B:
    case AArch64::LASTA_RPZ_D:
    case AArch64::LASTA_RPZ_H:
    case AArch64::LASTA_RPZ_S:
    case AArch64::LASTB_RPZ_B:
    case AArch64::LASTB_RPZ_D:
    case AArch64::LASTB_RPZ_H:
    case AArch64::LASTB_RPZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::CLASTA_RPZ_B:
    case AArch64::CLASTA_RPZ_D:
    case AArch64::CLASTA_RPZ_H:
    case AArch64::CLASTA_RPZ_S:
    case AArch64::CLASTB_RPZ_B:
    case AArch64::CLASTB_RPZ_D:
    case AArch64::CLASTB_RPZ_H:
    case AArch64::CLASTB_RPZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::LD2B:
    case AArch64::LD2D:
    case AArch64::LD2H:
    case AArch64::LD2Q:
    case AArch64::LD2W:
    case AArch64::LD3B:
    case AArch64::LD3D:
    case AArch64::LD3H:
    case AArch64::LD3Q:
    case AArch64::LD3W:
    case AArch64::LD4B:
    case AArch64::LD4D:
    case AArch64::LD4H:
    case AArch64::LD4Q:
    case AArch64::LD4W:
    case AArch64::LDNT1B_ZRR:
    case AArch64::LDNT1D_ZRR:
    case AArch64::LDNT1H_ZRR:
    case AArch64::LDNT1W_ZRR:
    case AArch64::ST1B:
    case AArch64::ST1B_D:
    case AArch64::ST1B_H:
    case AArch64::ST1B_S:
    case AArch64::ST1D:
    case AArch64::ST1D_Q:
    case AArch64::ST1H:
    case AArch64::ST1H_D:
    case AArch64::ST1H_S:
    case AArch64::ST1W:
    case AArch64::ST1W_D:
    case AArch64::ST1W_Q:
    case AArch64::ST2B:
    case AArch64::ST2D:
    case AArch64::ST2H:
    case AArch64::ST2W:
    case AArch64::ST3B:
    case AArch64::ST3D:
    case AArch64::ST3H:
    case AArch64::ST3W:
    case AArch64::ST4B:
    case AArch64::ST4D:
    case AArch64::ST4H:
    case AArch64::ST4W:
    case AArch64::STNT1B_ZRR:
    case AArch64::STNT1D_ZRR:
    case AArch64::STNT1H_ZRR:
    case AArch64::STNT1W_ZRR: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::LDNT1B_ZZR_D:
    case AArch64::LDNT1B_ZZR_S:
    case AArch64::LDNT1D_ZZR_D:
    case AArch64::LDNT1H_ZZR_D:
    case AArch64::LDNT1H_ZZR_S:
    case AArch64::LDNT1SB_ZZR_D:
    case AArch64::LDNT1SB_ZZR_S:
    case AArch64::LDNT1SH_ZZR_D:
    case AArch64::LDNT1SH_ZZR_S:
    case AArch64::LDNT1SW_ZZR_D:
    case AArch64::LDNT1W_ZZR_D:
    case AArch64::LDNT1W_ZZR_S:
    case AArch64::STNT1B_ZZR_D:
    case AArch64::STNT1B_ZZR_S:
    case AArch64::STNT1D_ZZR_D:
    case AArch64::STNT1H_ZZR_D:
    case AArch64::STNT1H_ZZR_S:
    case AArch64::STNT1W_ZZR_D:
    case AArch64::STNT1W_ZZR_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::GLD1B_D:
    case AArch64::GLD1B_D_SXTW:
    case AArch64::GLD1B_D_UXTW:
    case AArch64::GLD1B_S_SXTW:
    case AArch64::GLD1B_S_UXTW:
    case AArch64::GLD1D:
    case AArch64::GLD1D_SCALED:
    case AArch64::GLD1D_SXTW:
    case AArch64::GLD1D_SXTW_SCALED:
    case AArch64::GLD1D_UXTW:
    case AArch64::GLD1D_UXTW_SCALED:
    case AArch64::GLD1H_D:
    case AArch64::GLD1H_D_SCALED:
    case AArch64::GLD1H_D_SXTW:
    case AArch64::GLD1H_D_SXTW_SCALED:
    case AArch64::GLD1H_D_UXTW:
    case AArch64::GLD1H_D_UXTW_SCALED:
    case AArch64::GLD1H_S_SXTW:
    case AArch64::GLD1H_S_SXTW_SCALED:
    case AArch64::GLD1H_S_UXTW:
    case AArch64::GLD1H_S_UXTW_SCALED:
    case AArch64::GLD1SB_D:
    case AArch64::GLD1SB_D_SXTW:
    case AArch64::GLD1SB_D_UXTW:
    case AArch64::GLD1SB_S_SXTW:
    case AArch64::GLD1SB_S_UXTW:
    case AArch64::GLD1SH_D:
    case AArch64::GLD1SH_D_SCALED:
    case AArch64::GLD1SH_D_SXTW:
    case AArch64::GLD1SH_D_SXTW_SCALED:
    case AArch64::GLD1SH_D_UXTW:
    case AArch64::GLD1SH_D_UXTW_SCALED:
    case AArch64::GLD1SH_S_SXTW:
    case AArch64::GLD1SH_S_SXTW_SCALED:
    case AArch64::GLD1SH_S_UXTW:
    case AArch64::GLD1SH_S_UXTW_SCALED:
    case AArch64::GLD1SW_D:
    case AArch64::GLD1SW_D_SCALED:
    case AArch64::GLD1SW_D_SXTW:
    case AArch64::GLD1SW_D_SXTW_SCALED:
    case AArch64::GLD1SW_D_UXTW:
    case AArch64::GLD1SW_D_UXTW_SCALED:
    case AArch64::GLD1W_D:
    case AArch64::GLD1W_D_SCALED:
    case AArch64::GLD1W_D_SXTW:
    case AArch64::GLD1W_D_SXTW_SCALED:
    case AArch64::GLD1W_D_UXTW:
    case AArch64::GLD1W_D_UXTW_SCALED:
    case AArch64::GLD1W_SXTW:
    case AArch64::GLD1W_SXTW_SCALED:
    case AArch64::GLD1W_UXTW:
    case AArch64::GLD1W_UXTW_SCALED:
    case AArch64::GLDFF1B_D:
    case AArch64::GLDFF1B_D_SXTW:
    case AArch64::GLDFF1B_D_UXTW:
    case AArch64::GLDFF1B_S_SXTW:
    case AArch64::GLDFF1B_S_UXTW:
    case AArch64::GLDFF1D:
    case AArch64::GLDFF1D_SCALED:
    case AArch64::GLDFF1D_SXTW:
    case AArch64::GLDFF1D_SXTW_SCALED:
    case AArch64::GLDFF1D_UXTW:
    case AArch64::GLDFF1D_UXTW_SCALED:
    case AArch64::GLDFF1H_D:
    case AArch64::GLDFF1H_D_SCALED:
    case AArch64::GLDFF1H_D_SXTW:
    case AArch64::GLDFF1H_D_SXTW_SCALED:
    case AArch64::GLDFF1H_D_UXTW:
    case AArch64::GLDFF1H_D_UXTW_SCALED:
    case AArch64::GLDFF1H_S_SXTW:
    case AArch64::GLDFF1H_S_SXTW_SCALED:
    case AArch64::GLDFF1H_S_UXTW:
    case AArch64::GLDFF1H_S_UXTW_SCALED:
    case AArch64::GLDFF1SB_D:
    case AArch64::GLDFF1SB_D_SXTW:
    case AArch64::GLDFF1SB_D_UXTW:
    case AArch64::GLDFF1SB_S_SXTW:
    case AArch64::GLDFF1SB_S_UXTW:
    case AArch64::GLDFF1SH_D:
    case AArch64::GLDFF1SH_D_SCALED:
    case AArch64::GLDFF1SH_D_SXTW:
    case AArch64::GLDFF1SH_D_SXTW_SCALED:
    case AArch64::GLDFF1SH_D_UXTW:
    case AArch64::GLDFF1SH_D_UXTW_SCALED:
    case AArch64::GLDFF1SH_S_SXTW:
    case AArch64::GLDFF1SH_S_SXTW_SCALED:
    case AArch64::GLDFF1SH_S_UXTW:
    case AArch64::GLDFF1SH_S_UXTW_SCALED:
    case AArch64::GLDFF1SW_D:
    case AArch64::GLDFF1SW_D_SCALED:
    case AArch64::GLDFF1SW_D_SXTW:
    case AArch64::GLDFF1SW_D_SXTW_SCALED:
    case AArch64::GLDFF1SW_D_UXTW:
    case AArch64::GLDFF1SW_D_UXTW_SCALED:
    case AArch64::GLDFF1W_D:
    case AArch64::GLDFF1W_D_SCALED:
    case AArch64::GLDFF1W_D_SXTW:
    case AArch64::GLDFF1W_D_SXTW_SCALED:
    case AArch64::GLDFF1W_D_UXTW:
    case AArch64::GLDFF1W_D_UXTW_SCALED:
    case AArch64::GLDFF1W_SXTW:
    case AArch64::GLDFF1W_SXTW_SCALED:
    case AArch64::GLDFF1W_UXTW:
    case AArch64::GLDFF1W_UXTW_SCALED:
    case AArch64::SST1B_D:
    case AArch64::SST1B_D_SXTW:
    case AArch64::SST1B_D_UXTW:
    case AArch64::SST1B_S_SXTW:
    case AArch64::SST1B_S_UXTW:
    case AArch64::SST1D:
    case AArch64::SST1D_SCALED:
    case AArch64::SST1D_SXTW:
    case AArch64::SST1D_SXTW_SCALED:
    case AArch64::SST1D_UXTW:
    case AArch64::SST1D_UXTW_SCALED:
    case AArch64::SST1H_D:
    case AArch64::SST1H_D_SCALED:
    case AArch64::SST1H_D_SXTW:
    case AArch64::SST1H_D_SXTW_SCALED:
    case AArch64::SST1H_D_UXTW:
    case AArch64::SST1H_D_UXTW_SCALED:
    case AArch64::SST1H_S_SXTW:
    case AArch64::SST1H_S_SXTW_SCALED:
    case AArch64::SST1H_S_UXTW:
    case AArch64::SST1H_S_UXTW_SCALED:
    case AArch64::SST1W_D:
    case AArch64::SST1W_D_SCALED:
    case AArch64::SST1W_D_SXTW:
    case AArch64::SST1W_D_SXTW_SCALED:
    case AArch64::SST1W_D_UXTW:
    case AArch64::SST1W_D_UXTW_SCALED:
    case AArch64::SST1W_SXTW:
    case AArch64::SST1W_SXTW_SCALED:
    case AArch64::SST1W_UXTW:
    case AArch64::SST1W_UXTW_SCALED: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::PRFB_D_SCALED:
    case AArch64::PRFB_D_SXTW_SCALED:
    case AArch64::PRFB_D_UXTW_SCALED:
    case AArch64::PRFB_S_SXTW_SCALED:
    case AArch64::PRFB_S_UXTW_SCALED:
    case AArch64::PRFD_D_SCALED:
    case AArch64::PRFD_D_SXTW_SCALED:
    case AArch64::PRFD_D_UXTW_SCALED:
    case AArch64::PRFD_S_SXTW_SCALED:
    case AArch64::PRFD_S_UXTW_SCALED:
    case AArch64::PRFH_D_SCALED:
    case AArch64::PRFH_D_SXTW_SCALED:
    case AArch64::PRFH_D_UXTW_SCALED:
    case AArch64::PRFH_S_SXTW_SCALED:
    case AArch64::PRFH_S_UXTW_SCALED:
    case AArch64::PRFW_D_SCALED:
    case AArch64::PRFW_D_SXTW_SCALED:
    case AArch64::PRFW_D_UXTW_SCALED:
    case AArch64::PRFW_S_SXTW_SCALED:
    case AArch64::PRFW_S_UXTW_SCALED: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: prfop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::LD1B_D_IMM:
    case AArch64::LD1B_H_IMM:
    case AArch64::LD1B_IMM:
    case AArch64::LD1B_S_IMM:
    case AArch64::LD1D_IMM:
    case AArch64::LD1H_D_IMM:
    case AArch64::LD1H_IMM:
    case AArch64::LD1H_S_IMM:
    case AArch64::LD1SB_D_IMM:
    case AArch64::LD1SB_H_IMM:
    case AArch64::LD1SB_S_IMM:
    case AArch64::LD1SH_D_IMM:
    case AArch64::LD1SH_S_IMM:
    case AArch64::LD1SW_D_IMM:
    case AArch64::LD1W_D_IMM:
    case AArch64::LD1W_IMM:
    case AArch64::LDNF1B_D_IMM:
    case AArch64::LDNF1B_H_IMM:
    case AArch64::LDNF1B_IMM:
    case AArch64::LDNF1B_S_IMM:
    case AArch64::LDNF1D_IMM:
    case AArch64::LDNF1H_D_IMM:
    case AArch64::LDNF1H_IMM:
    case AArch64::LDNF1H_S_IMM:
    case AArch64::LDNF1SB_D_IMM:
    case AArch64::LDNF1SB_H_IMM:
    case AArch64::LDNF1SB_S_IMM:
    case AArch64::LDNF1SH_D_IMM:
    case AArch64::LDNF1SH_S_IMM:
    case AArch64::LDNF1SW_D_IMM:
    case AArch64::LDNF1W_D_IMM:
    case AArch64::LDNF1W_IMM:
    case AArch64::ST1B_D_IMM:
    case AArch64::ST1B_H_IMM:
    case AArch64::ST1B_IMM:
    case AArch64::ST1B_S_IMM:
    case AArch64::ST1D_IMM:
    case AArch64::ST1D_Q_IMM:
    case AArch64::ST1H_D_IMM:
    case AArch64::ST1H_IMM:
    case AArch64::ST1H_S_IMM:
    case AArch64::ST1W_D_IMM:
    case AArch64::ST1W_IMM:
    case AArch64::ST1W_Q_IMM:
    case AArch64::ST2B_IMM:
    case AArch64::ST2D_IMM:
    case AArch64::ST2H_IMM:
    case AArch64::ST2W_IMM:
    case AArch64::ST3B_IMM:
    case AArch64::ST3D_IMM:
    case AArch64::ST3H_IMM:
    case AArch64::ST3W_IMM:
    case AArch64::ST4B_IMM:
    case AArch64::ST4D_IMM:
    case AArch64::ST4H_IMM:
    case AArch64::ST4W_IMM:
    case AArch64::STNT1B_ZRI:
    case AArch64::STNT1D_ZRI:
    case AArch64::STNT1H_ZRI:
    case AArch64::STNT1W_ZRI: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::LD1RB_D_IMM:
    case AArch64::LD1RB_H_IMM:
    case AArch64::LD1RB_IMM:
    case AArch64::LD1RB_S_IMM:
    case AArch64::LD1RD_IMM:
    case AArch64::LD1RH_D_IMM:
    case AArch64::LD1RH_IMM:
    case AArch64::LD1RH_S_IMM:
    case AArch64::LD1RSB_D_IMM:
    case AArch64::LD1RSB_H_IMM:
    case AArch64::LD1RSB_S_IMM:
    case AArch64::LD1RSH_D_IMM:
    case AArch64::LD1RSH_S_IMM:
    case AArch64::LD1RSW_IMM:
    case AArch64::LD1RW_D_IMM:
    case AArch64::LD1RW_IMM: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      break;
    }
    case AArch64::ANDV_VPZ_B:
    case AArch64::ANDV_VPZ_D:
    case AArch64::ANDV_VPZ_H:
    case AArch64::ANDV_VPZ_S:
    case AArch64::EORV_VPZ_B:
    case AArch64::EORV_VPZ_D:
    case AArch64::EORV_VPZ_H:
    case AArch64::EORV_VPZ_S:
    case AArch64::LASTA_VPZ_B:
    case AArch64::LASTA_VPZ_D:
    case AArch64::LASTA_VPZ_H:
    case AArch64::LASTA_VPZ_S:
    case AArch64::LASTB_VPZ_B:
    case AArch64::LASTB_VPZ_D:
    case AArch64::LASTB_VPZ_H:
    case AArch64::LASTB_VPZ_S:
    case AArch64::ORV_VPZ_B:
    case AArch64::ORV_VPZ_D:
    case AArch64::ORV_VPZ_H:
    case AArch64::ORV_VPZ_S:
    case AArch64::SADDV_VPZ_B:
    case AArch64::SADDV_VPZ_H:
    case AArch64::SADDV_VPZ_S:
    case AArch64::SMAXV_VPZ_B:
    case AArch64::SMAXV_VPZ_D:
    case AArch64::SMAXV_VPZ_H:
    case AArch64::SMAXV_VPZ_S:
    case AArch64::SMINV_VPZ_B:
    case AArch64::SMINV_VPZ_D:
    case AArch64::SMINV_VPZ_H:
    case AArch64::SMINV_VPZ_S:
    case AArch64::UADDV_VPZ_B:
    case AArch64::UADDV_VPZ_D:
    case AArch64::UADDV_VPZ_H:
    case AArch64::UADDV_VPZ_S:
    case AArch64::UMAXV_VPZ_B:
    case AArch64::UMAXV_VPZ_D:
    case AArch64::UMAXV_VPZ_H:
    case AArch64::UMAXV_VPZ_S:
    case AArch64::UMINV_VPZ_B:
    case AArch64::UMINV_VPZ_D:
    case AArch64::UMINV_VPZ_H:
    case AArch64::UMINV_VPZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::CLASTA_VPZ_B:
    case AArch64::CLASTA_VPZ_D:
    case AArch64::CLASTA_VPZ_H:
    case AArch64::CLASTA_VPZ_S:
    case AArch64::CLASTB_VPZ_B:
    case AArch64::CLASTB_VPZ_D:
    case AArch64::CLASTB_VPZ_H:
    case AArch64::CLASTB_VPZ_S:
    case AArch64::FADDA_VPZ_D:
    case AArch64::FADDA_VPZ_H:
    case AArch64::FADDA_VPZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Vdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::FMAD_ZPmZZ_D:
    case AArch64::FMAD_ZPmZZ_H:
    case AArch64::FMAD_ZPmZZ_S:
    case AArch64::FMSB_ZPmZZ_D:
    case AArch64::FMSB_ZPmZZ_H:
    case AArch64::FMSB_ZPmZZ_S:
    case AArch64::FNMAD_ZPmZZ_D:
    case AArch64::FNMAD_ZPmZZ_H:
    case AArch64::FNMAD_ZPmZZ_S:
    case AArch64::FNMSB_ZPmZZ_D:
    case AArch64::FNMSB_ZPmZZ_H:
    case AArch64::FNMSB_ZPmZZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Za
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::ABS_ZPzZ_B:
    case AArch64::ABS_ZPzZ_D:
    case AArch64::ABS_ZPzZ_H:
    case AArch64::ABS_ZPzZ_S:
    case AArch64::BFCVT_ZPzZ_StoH:
    case AArch64::CLS_ZPzZ_B:
    case AArch64::CLS_ZPzZ_D:
    case AArch64::CLS_ZPzZ_H:
    case AArch64::CLS_ZPzZ_S:
    case AArch64::CLZ_ZPzZ_B:
    case AArch64::CLZ_ZPzZ_D:
    case AArch64::CLZ_ZPzZ_H:
    case AArch64::CLZ_ZPzZ_S:
    case AArch64::CNOT_ZPzZ_B:
    case AArch64::CNOT_ZPzZ_D:
    case AArch64::CNOT_ZPzZ_H:
    case AArch64::CNOT_ZPzZ_S:
    case AArch64::CNT_ZPzZ_B:
    case AArch64::CNT_ZPzZ_D:
    case AArch64::CNT_ZPzZ_H:
    case AArch64::CNT_ZPzZ_S:
    case AArch64::COMPACT_ZPZ_B:
    case AArch64::COMPACT_ZPZ_D:
    case AArch64::COMPACT_ZPZ_H:
    case AArch64::COMPACT_ZPZ_S:
    case AArch64::FABS_ZPzZ_D:
    case AArch64::FABS_ZPzZ_H:
    case AArch64::FABS_ZPzZ_S:
    case AArch64::FCVTX_ZPzZ_DtoS:
    case AArch64::FCVTZS_ZPzZ_DtoD:
    case AArch64::FCVTZS_ZPzZ_DtoS:
    case AArch64::FCVTZS_ZPzZ_HtoD:
    case AArch64::FCVTZS_ZPzZ_HtoH:
    case AArch64::FCVTZS_ZPzZ_HtoS:
    case AArch64::FCVTZS_ZPzZ_StoD:
    case AArch64::FCVTZS_ZPzZ_StoS:
    case AArch64::FCVTZU_ZPzZ_DtoD:
    case AArch64::FCVTZU_ZPzZ_DtoS:
    case AArch64::FCVTZU_ZPzZ_HtoD:
    case AArch64::FCVTZU_ZPzZ_HtoH:
    case AArch64::FCVTZU_ZPzZ_HtoS:
    case AArch64::FCVTZU_ZPzZ_StoD:
    case AArch64::FCVTZU_ZPzZ_StoS:
    case AArch64::FCVT_ZPzZ_DtoH:
    case AArch64::FCVT_ZPzZ_DtoS:
    case AArch64::FCVT_ZPzZ_HtoD:
    case AArch64::FCVT_ZPzZ_HtoS:
    case AArch64::FCVT_ZPzZ_StoD:
    case AArch64::FCVT_ZPzZ_StoH:
    case AArch64::FLOGB_ZPzZ_D:
    case AArch64::FLOGB_ZPzZ_H:
    case AArch64::FLOGB_ZPzZ_S:
    case AArch64::FNEG_ZPzZ_D:
    case AArch64::FNEG_ZPzZ_H:
    case AArch64::FNEG_ZPzZ_S:
    case AArch64::FRECPX_ZPzZ_D:
    case AArch64::FRECPX_ZPzZ_H:
    case AArch64::FRECPX_ZPzZ_S:
    case AArch64::FRINT32X_ZPzZ_D:
    case AArch64::FRINT32X_ZPzZ_S:
    case AArch64::FRINT32Z_ZPzZ_D:
    case AArch64::FRINT32Z_ZPzZ_S:
    case AArch64::FRINT64X_ZPzZ_D:
    case AArch64::FRINT64X_ZPzZ_S:
    case AArch64::FRINT64Z_ZPzZ_D:
    case AArch64::FRINT64Z_ZPzZ_S:
    case AArch64::FRINTA_ZPzZ_D:
    case AArch64::FRINTA_ZPzZ_H:
    case AArch64::FRINTA_ZPzZ_S:
    case AArch64::FRINTI_ZPzZ_D:
    case AArch64::FRINTI_ZPzZ_H:
    case AArch64::FRINTI_ZPzZ_S:
    case AArch64::FRINTM_ZPzZ_D:
    case AArch64::FRINTM_ZPzZ_H:
    case AArch64::FRINTM_ZPzZ_S:
    case AArch64::FRINTN_ZPzZ_D:
    case AArch64::FRINTN_ZPzZ_H:
    case AArch64::FRINTN_ZPzZ_S:
    case AArch64::FRINTP_ZPzZ_D:
    case AArch64::FRINTP_ZPzZ_H:
    case AArch64::FRINTP_ZPzZ_S:
    case AArch64::FRINTX_ZPzZ_D:
    case AArch64::FRINTX_ZPzZ_H:
    case AArch64::FRINTX_ZPzZ_S:
    case AArch64::FRINTZ_ZPzZ_D:
    case AArch64::FRINTZ_ZPzZ_H:
    case AArch64::FRINTZ_ZPzZ_S:
    case AArch64::FSQRT_ZPZz_D:
    case AArch64::FSQRT_ZPZz_H:
    case AArch64::FSQRT_ZPZz_S:
    case AArch64::MOVPRFX_ZPzZ_B:
    case AArch64::MOVPRFX_ZPzZ_D:
    case AArch64::MOVPRFX_ZPzZ_H:
    case AArch64::MOVPRFX_ZPzZ_S:
    case AArch64::NEG_ZPzZ_B:
    case AArch64::NEG_ZPzZ_D:
    case AArch64::NEG_ZPzZ_H:
    case AArch64::NEG_ZPzZ_S:
    case AArch64::NOT_ZPzZ_B:
    case AArch64::NOT_ZPzZ_D:
    case AArch64::NOT_ZPzZ_H:
    case AArch64::NOT_ZPzZ_S:
    case AArch64::SCVTF_ZPzZ_DtoD:
    case AArch64::SCVTF_ZPzZ_DtoH:
    case AArch64::SCVTF_ZPzZ_DtoS:
    case AArch64::SCVTF_ZPzZ_HtoH:
    case AArch64::SCVTF_ZPzZ_StoD:
    case AArch64::SCVTF_ZPzZ_StoH:
    case AArch64::SCVTF_ZPzZ_StoS:
    case AArch64::SQABS_ZPzZ_B:
    case AArch64::SQABS_ZPzZ_D:
    case AArch64::SQABS_ZPzZ_H:
    case AArch64::SQABS_ZPzZ_S:
    case AArch64::SQNEG_ZPzZ_B:
    case AArch64::SQNEG_ZPzZ_D:
    case AArch64::SQNEG_ZPzZ_H:
    case AArch64::SQNEG_ZPzZ_S:
    case AArch64::SXTB_ZPzZ_D:
    case AArch64::SXTB_ZPzZ_H:
    case AArch64::SXTB_ZPzZ_S:
    case AArch64::SXTH_ZPzZ_D:
    case AArch64::SXTH_ZPzZ_S:
    case AArch64::SXTW_ZPzZ_D:
    case AArch64::UCVTF_ZPzZ_DtoD:
    case AArch64::UCVTF_ZPzZ_DtoH:
    case AArch64::UCVTF_ZPzZ_DtoS:
    case AArch64::UCVTF_ZPzZ_HtoH:
    case AArch64::UCVTF_ZPzZ_StoD:
    case AArch64::UCVTF_ZPzZ_StoH:
    case AArch64::UCVTF_ZPzZ_StoS:
    case AArch64::URECPE_ZPzZ_S:
    case AArch64::URSQRTE_ZPzZ_S:
    case AArch64::UXTB_ZPzZ_D:
    case AArch64::UXTB_ZPzZ_H:
    case AArch64::UXTB_ZPzZ_S:
    case AArch64::UXTH_ZPzZ_D:
    case AArch64::UXTH_ZPzZ_S:
    case AArch64::UXTW_ZPzZ_D: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::BFMLA_ZPmZZ:
    case AArch64::BFMLS_ZPmZZ:
    case AArch64::FMLA_ZPmZZ_D:
    case AArch64::FMLA_ZPmZZ_H:
    case AArch64::FMLA_ZPmZZ_S:
    case AArch64::FMLS_ZPmZZ_D:
    case AArch64::FMLS_ZPmZZ_H:
    case AArch64::FMLS_ZPmZZ_S:
    case AArch64::FNMLA_ZPmZZ_D:
    case AArch64::FNMLA_ZPmZZ_H:
    case AArch64::FNMLA_ZPmZZ_S:
    case AArch64::FNMLS_ZPmZZ_D:
    case AArch64::FNMLS_ZPmZZ_H:
    case AArch64::FNMLS_ZPmZZ_S:
    case AArch64::MLA_ZPmZZ_B:
    case AArch64::MLA_ZPmZZ_D:
    case AArch64::MLA_ZPmZZ_H:
    case AArch64::MLA_ZPmZZ_S:
    case AArch64::MLS_ZPmZZ_B:
    case AArch64::MLS_ZPmZZ_D:
    case AArch64::MLS_ZPmZZ_H:
    case AArch64::MLS_ZPmZZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::MAD_ZPmZZ_B:
    case AArch64::MAD_ZPmZZ_D:
    case AArch64::MAD_ZPmZZ_H:
    case AArch64::MAD_ZPmZZ_S:
    case AArch64::MSB_ZPmZZ_B:
    case AArch64::MSB_ZPmZZ_D:
    case AArch64::MSB_ZPmZZ_H:
    case AArch64::MSB_ZPmZZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Za
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::ADD_ZPmZ_B:
    case AArch64::ADD_ZPmZ_CPA:
    case AArch64::ADD_ZPmZ_D:
    case AArch64::ADD_ZPmZ_H:
    case AArch64::ADD_ZPmZ_S:
    case AArch64::AND_ZPmZ_B:
    case AArch64::AND_ZPmZ_D:
    case AArch64::AND_ZPmZ_H:
    case AArch64::AND_ZPmZ_S:
    case AArch64::ASRR_ZPmZ_B:
    case AArch64::ASRR_ZPmZ_D:
    case AArch64::ASRR_ZPmZ_H:
    case AArch64::ASRR_ZPmZ_S:
    case AArch64::ASR_WIDE_ZPmZ_B:
    case AArch64::ASR_WIDE_ZPmZ_H:
    case AArch64::ASR_WIDE_ZPmZ_S:
    case AArch64::ASR_ZPmZ_B:
    case AArch64::ASR_ZPmZ_D:
    case AArch64::ASR_ZPmZ_H:
    case AArch64::ASR_ZPmZ_S:
    case AArch64::BFADD_ZPmZZ:
    case AArch64::BFMAXNM_ZPmZZ:
    case AArch64::BFMAX_ZPmZZ:
    case AArch64::BFMINNM_ZPmZZ:
    case AArch64::BFMIN_ZPmZZ:
    case AArch64::BFMUL_ZPmZZ:
    case AArch64::BFSCALE_ZPZZ_H:
    case AArch64::BFSUB_ZPmZZ:
    case AArch64::BIC_ZPmZ_B:
    case AArch64::BIC_ZPmZ_D:
    case AArch64::BIC_ZPmZ_H:
    case AArch64::BIC_ZPmZ_S:
    case AArch64::CLASTA_ZPZ_B:
    case AArch64::CLASTA_ZPZ_D:
    case AArch64::CLASTA_ZPZ_H:
    case AArch64::CLASTA_ZPZ_S:
    case AArch64::CLASTB_ZPZ_B:
    case AArch64::CLASTB_ZPZ_D:
    case AArch64::CLASTB_ZPZ_H:
    case AArch64::CLASTB_ZPZ_S:
    case AArch64::EOR_ZPmZ_B:
    case AArch64::EOR_ZPmZ_D:
    case AArch64::EOR_ZPmZ_H:
    case AArch64::EOR_ZPmZ_S:
    case AArch64::FABD_ZPmZ_D:
    case AArch64::FABD_ZPmZ_H:
    case AArch64::FABD_ZPmZ_S:
    case AArch64::FADD_ZPmZ_D:
    case AArch64::FADD_ZPmZ_H:
    case AArch64::FADD_ZPmZ_S:
    case AArch64::FAMAX_ZPmZ_D:
    case AArch64::FAMAX_ZPmZ_H:
    case AArch64::FAMAX_ZPmZ_S:
    case AArch64::FAMIN_ZPmZ_D:
    case AArch64::FAMIN_ZPmZ_H:
    case AArch64::FAMIN_ZPmZ_S:
    case AArch64::FDIVR_ZPmZ_D:
    case AArch64::FDIVR_ZPmZ_H:
    case AArch64::FDIVR_ZPmZ_S:
    case AArch64::FDIV_ZPmZ_D:
    case AArch64::FDIV_ZPmZ_H:
    case AArch64::FDIV_ZPmZ_S:
    case AArch64::FMAXNM_ZPmZ_D:
    case AArch64::FMAXNM_ZPmZ_H:
    case AArch64::FMAXNM_ZPmZ_S:
    case AArch64::FMAX_ZPmZ_D:
    case AArch64::FMAX_ZPmZ_H:
    case AArch64::FMAX_ZPmZ_S:
    case AArch64::FMINNM_ZPmZ_D:
    case AArch64::FMINNM_ZPmZ_H:
    case AArch64::FMINNM_ZPmZ_S:
    case AArch64::FMIN_ZPmZ_D:
    case AArch64::FMIN_ZPmZ_H:
    case AArch64::FMIN_ZPmZ_S:
    case AArch64::FMULX_ZPmZ_D:
    case AArch64::FMULX_ZPmZ_H:
    case AArch64::FMULX_ZPmZ_S:
    case AArch64::FMUL_ZPmZ_D:
    case AArch64::FMUL_ZPmZ_H:
    case AArch64::FMUL_ZPmZ_S:
    case AArch64::FSCALE_ZPmZ_D:
    case AArch64::FSCALE_ZPmZ_H:
    case AArch64::FSCALE_ZPmZ_S:
    case AArch64::FSUBR_ZPmZ_D:
    case AArch64::FSUBR_ZPmZ_H:
    case AArch64::FSUBR_ZPmZ_S:
    case AArch64::FSUB_ZPmZ_D:
    case AArch64::FSUB_ZPmZ_H:
    case AArch64::FSUB_ZPmZ_S:
    case AArch64::LSLR_ZPmZ_B:
    case AArch64::LSLR_ZPmZ_D:
    case AArch64::LSLR_ZPmZ_H:
    case AArch64::LSLR_ZPmZ_S:
    case AArch64::LSL_WIDE_ZPmZ_B:
    case AArch64::LSL_WIDE_ZPmZ_H:
    case AArch64::LSL_WIDE_ZPmZ_S:
    case AArch64::LSL_ZPmZ_B:
    case AArch64::LSL_ZPmZ_D:
    case AArch64::LSL_ZPmZ_H:
    case AArch64::LSL_ZPmZ_S:
    case AArch64::LSRR_ZPmZ_B:
    case AArch64::LSRR_ZPmZ_D:
    case AArch64::LSRR_ZPmZ_H:
    case AArch64::LSRR_ZPmZ_S:
    case AArch64::LSR_WIDE_ZPmZ_B:
    case AArch64::LSR_WIDE_ZPmZ_H:
    case AArch64::LSR_WIDE_ZPmZ_S:
    case AArch64::LSR_ZPmZ_B:
    case AArch64::LSR_ZPmZ_D:
    case AArch64::LSR_ZPmZ_H:
    case AArch64::LSR_ZPmZ_S:
    case AArch64::MUL_ZPmZ_B:
    case AArch64::MUL_ZPmZ_D:
    case AArch64::MUL_ZPmZ_H:
    case AArch64::MUL_ZPmZ_S:
    case AArch64::ORR_ZPmZ_B:
    case AArch64::ORR_ZPmZ_D:
    case AArch64::ORR_ZPmZ_H:
    case AArch64::ORR_ZPmZ_S:
    case AArch64::SABD_ZPmZ_B:
    case AArch64::SABD_ZPmZ_D:
    case AArch64::SABD_ZPmZ_H:
    case AArch64::SABD_ZPmZ_S:
    case AArch64::SDIVR_ZPmZ_D:
    case AArch64::SDIVR_ZPmZ_S:
    case AArch64::SDIV_ZPmZ_D:
    case AArch64::SDIV_ZPmZ_S:
    case AArch64::SMAX_ZPmZ_B:
    case AArch64::SMAX_ZPmZ_D:
    case AArch64::SMAX_ZPmZ_H:
    case AArch64::SMAX_ZPmZ_S:
    case AArch64::SMIN_ZPmZ_B:
    case AArch64::SMIN_ZPmZ_D:
    case AArch64::SMIN_ZPmZ_H:
    case AArch64::SMIN_ZPmZ_S:
    case AArch64::SMULH_ZPmZ_B:
    case AArch64::SMULH_ZPmZ_D:
    case AArch64::SMULH_ZPmZ_H:
    case AArch64::SMULH_ZPmZ_S:
    case AArch64::SPLICE_ZPZ_B:
    case AArch64::SPLICE_ZPZ_D:
    case AArch64::SPLICE_ZPZ_H:
    case AArch64::SPLICE_ZPZ_S:
    case AArch64::SUBR_ZPmZ_B:
    case AArch64::SUBR_ZPmZ_D:
    case AArch64::SUBR_ZPmZ_H:
    case AArch64::SUBR_ZPmZ_S:
    case AArch64::SUB_ZPmZ_B:
    case AArch64::SUB_ZPmZ_CPA:
    case AArch64::SUB_ZPmZ_D:
    case AArch64::SUB_ZPmZ_H:
    case AArch64::SUB_ZPmZ_S:
    case AArch64::UABD_ZPmZ_B:
    case AArch64::UABD_ZPmZ_D:
    case AArch64::UABD_ZPmZ_H:
    case AArch64::UABD_ZPmZ_S:
    case AArch64::UDIVR_ZPmZ_D:
    case AArch64::UDIVR_ZPmZ_S:
    case AArch64::UDIV_ZPmZ_D:
    case AArch64::UDIV_ZPmZ_S:
    case AArch64::UMAX_ZPmZ_B:
    case AArch64::UMAX_ZPmZ_D:
    case AArch64::UMAX_ZPmZ_H:
    case AArch64::UMAX_ZPmZ_S:
    case AArch64::UMIN_ZPmZ_B:
    case AArch64::UMIN_ZPmZ_D:
    case AArch64::UMIN_ZPmZ_H:
    case AArch64::UMIN_ZPmZ_S:
    case AArch64::UMULH_ZPmZ_B:
    case AArch64::UMULH_ZPmZ_D:
    case AArch64::UMULH_ZPmZ_H:
    case AArch64::UMULH_ZPmZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::FADD_ZPmI_D:
    case AArch64::FADD_ZPmI_H:
    case AArch64::FADD_ZPmI_S:
    case AArch64::FMAXNM_ZPmI_D:
    case AArch64::FMAXNM_ZPmI_H:
    case AArch64::FMAXNM_ZPmI_S:
    case AArch64::FMAX_ZPmI_D:
    case AArch64::FMAX_ZPmI_H:
    case AArch64::FMAX_ZPmI_S:
    case AArch64::FMINNM_ZPmI_D:
    case AArch64::FMINNM_ZPmI_H:
    case AArch64::FMINNM_ZPmI_S:
    case AArch64::FMIN_ZPmI_D:
    case AArch64::FMIN_ZPmI_H:
    case AArch64::FMIN_ZPmI_S:
    case AArch64::FMUL_ZPmI_D:
    case AArch64::FMUL_ZPmI_H:
    case AArch64::FMUL_ZPmI_S:
    case AArch64::FSUBR_ZPmI_D:
    case AArch64::FSUBR_ZPmI_H:
    case AArch64::FSUBR_ZPmI_S:
    case AArch64::FSUB_ZPmI_D:
    case AArch64::FSUB_ZPmI_H:
    case AArch64::FSUB_ZPmI_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: i1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 5;
      break;
    }
    case AArch64::LSL_ZPmI_H:
    case AArch64::SQSHLU_ZPmI_H:
    case AArch64::SQSHL_ZPmI_H:
    case AArch64::UQSHL_ZPmI_H: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftL16OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::LSL_ZPmI_S:
    case AArch64::SQSHLU_ZPmI_S:
    case AArch64::SQSHL_ZPmI_S:
    case AArch64::UQSHL_ZPmI_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftL32OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::LSL_ZPmI_D:
    case AArch64::SQSHLU_ZPmI_D:
    case AArch64::SQSHL_ZPmI_D:
    case AArch64::UQSHL_ZPmI_D: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftL64OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x20) << 17;
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::LSL_ZPmI_B:
    case AArch64::SQSHLU_ZPmI_B:
    case AArch64::SQSHL_ZPmI_B:
    case AArch64::UQSHL_ZPmI_B: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftL8OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::ASRD_ZPmI_H:
    case AArch64::ASR_ZPmI_H:
    case AArch64::LSR_ZPmI_H:
    case AArch64::SRSHR_ZPmI_H:
    case AArch64::URSHR_ZPmI_H: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::ASRD_ZPmI_S:
    case AArch64::ASR_ZPmI_S:
    case AArch64::LSR_ZPmI_S:
    case AArch64::SRSHR_ZPmI_S:
    case AArch64::URSHR_ZPmI_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::ASRD_ZPmI_D:
    case AArch64::ASR_ZPmI_D:
    case AArch64::LSR_ZPmI_D:
    case AArch64::SRSHR_ZPmI_D:
    case AArch64::URSHR_ZPmI_D: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x20) << 17;
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::ASRD_ZPmI_B:
    case AArch64::ASR_ZPmI_B:
    case AArch64::LSR_ZPmI_B:
    case AArch64::SRSHR_ZPmI_B:
    case AArch64::URSHR_ZPmI_B: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::ADDP_ZPmZ_B:
    case AArch64::ADDP_ZPmZ_D:
    case AArch64::ADDP_ZPmZ_H:
    case AArch64::ADDP_ZPmZ_S:
    case AArch64::FADDP_ZPmZZ_D:
    case AArch64::FADDP_ZPmZZ_H:
    case AArch64::FADDP_ZPmZZ_S:
    case AArch64::FMAXNMP_ZPmZZ_D:
    case AArch64::FMAXNMP_ZPmZZ_H:
    case AArch64::FMAXNMP_ZPmZZ_S:
    case AArch64::FMAXP_ZPmZZ_D:
    case AArch64::FMAXP_ZPmZZ_H:
    case AArch64::FMAXP_ZPmZZ_S:
    case AArch64::FMINNMP_ZPmZZ_D:
    case AArch64::FMINNMP_ZPmZZ_H:
    case AArch64::FMINNMP_ZPmZZ_S:
    case AArch64::FMINP_ZPmZZ_D:
    case AArch64::FMINP_ZPmZZ_H:
    case AArch64::FMINP_ZPmZZ_S:
    case AArch64::SHADD_ZPmZ_B:
    case AArch64::SHADD_ZPmZ_D:
    case AArch64::SHADD_ZPmZ_H:
    case AArch64::SHADD_ZPmZ_S:
    case AArch64::SHSUBR_ZPmZ_B:
    case AArch64::SHSUBR_ZPmZ_D:
    case AArch64::SHSUBR_ZPmZ_H:
    case AArch64::SHSUBR_ZPmZ_S:
    case AArch64::SHSUB_ZPmZ_B:
    case AArch64::SHSUB_ZPmZ_D:
    case AArch64::SHSUB_ZPmZ_H:
    case AArch64::SHSUB_ZPmZ_S:
    case AArch64::SMAXP_ZPmZ_B:
    case AArch64::SMAXP_ZPmZ_D:
    case AArch64::SMAXP_ZPmZ_H:
    case AArch64::SMAXP_ZPmZ_S:
    case AArch64::SMINP_ZPmZ_B:
    case AArch64::SMINP_ZPmZ_D:
    case AArch64::SMINP_ZPmZ_H:
    case AArch64::SMINP_ZPmZ_S:
    case AArch64::SQADD_ZPmZ_B:
    case AArch64::SQADD_ZPmZ_D:
    case AArch64::SQADD_ZPmZ_H:
    case AArch64::SQADD_ZPmZ_S:
    case AArch64::SQRSHLR_ZPmZ_B:
    case AArch64::SQRSHLR_ZPmZ_D:
    case AArch64::SQRSHLR_ZPmZ_H:
    case AArch64::SQRSHLR_ZPmZ_S:
    case AArch64::SQRSHL_ZPmZ_B:
    case AArch64::SQRSHL_ZPmZ_D:
    case AArch64::SQRSHL_ZPmZ_H:
    case AArch64::SQRSHL_ZPmZ_S:
    case AArch64::SQSHLR_ZPmZ_B:
    case AArch64::SQSHLR_ZPmZ_D:
    case AArch64::SQSHLR_ZPmZ_H:
    case AArch64::SQSHLR_ZPmZ_S:
    case AArch64::SQSHL_ZPmZ_B:
    case AArch64::SQSHL_ZPmZ_D:
    case AArch64::SQSHL_ZPmZ_H:
    case AArch64::SQSHL_ZPmZ_S:
    case AArch64::SQSUBR_ZPmZ_B:
    case AArch64::SQSUBR_ZPmZ_D:
    case AArch64::SQSUBR_ZPmZ_H:
    case AArch64::SQSUBR_ZPmZ_S:
    case AArch64::SQSUB_ZPmZ_B:
    case AArch64::SQSUB_ZPmZ_D:
    case AArch64::SQSUB_ZPmZ_H:
    case AArch64::SQSUB_ZPmZ_S:
    case AArch64::SRHADD_ZPmZ_B:
    case AArch64::SRHADD_ZPmZ_D:
    case AArch64::SRHADD_ZPmZ_H:
    case AArch64::SRHADD_ZPmZ_S:
    case AArch64::SRSHLR_ZPmZ_B:
    case AArch64::SRSHLR_ZPmZ_D:
    case AArch64::SRSHLR_ZPmZ_H:
    case AArch64::SRSHLR_ZPmZ_S:
    case AArch64::SRSHL_ZPmZ_B:
    case AArch64::SRSHL_ZPmZ_D:
    case AArch64::SRSHL_ZPmZ_H:
    case AArch64::SRSHL_ZPmZ_S:
    case AArch64::SUBP_ZPmZZ_B:
    case AArch64::SUBP_ZPmZZ_D:
    case AArch64::SUBP_ZPmZZ_H:
    case AArch64::SUBP_ZPmZZ_S:
    case AArch64::SUQADD_ZPmZ_B:
    case AArch64::SUQADD_ZPmZ_D:
    case AArch64::SUQADD_ZPmZ_H:
    case AArch64::SUQADD_ZPmZ_S:
    case AArch64::UHADD_ZPmZ_B:
    case AArch64::UHADD_ZPmZ_D:
    case AArch64::UHADD_ZPmZ_H:
    case AArch64::UHADD_ZPmZ_S:
    case AArch64::UHSUBR_ZPmZ_B:
    case AArch64::UHSUBR_ZPmZ_D:
    case AArch64::UHSUBR_ZPmZ_H:
    case AArch64::UHSUBR_ZPmZ_S:
    case AArch64::UHSUB_ZPmZ_B:
    case AArch64::UHSUB_ZPmZ_D:
    case AArch64::UHSUB_ZPmZ_H:
    case AArch64::UHSUB_ZPmZ_S:
    case AArch64::UMAXP_ZPmZ_B:
    case AArch64::UMAXP_ZPmZ_D:
    case AArch64::UMAXP_ZPmZ_H:
    case AArch64::UMAXP_ZPmZ_S:
    case AArch64::UMINP_ZPmZ_B:
    case AArch64::UMINP_ZPmZ_D:
    case AArch64::UMINP_ZPmZ_H:
    case AArch64::UMINP_ZPmZ_S:
    case AArch64::UQADD_ZPmZ_B:
    case AArch64::UQADD_ZPmZ_D:
    case AArch64::UQADD_ZPmZ_H:
    case AArch64::UQADD_ZPmZ_S:
    case AArch64::UQRSHLR_ZPmZ_B:
    case AArch64::UQRSHLR_ZPmZ_D:
    case AArch64::UQRSHLR_ZPmZ_H:
    case AArch64::UQRSHLR_ZPmZ_S:
    case AArch64::UQRSHL_ZPmZ_B:
    case AArch64::UQRSHL_ZPmZ_D:
    case AArch64::UQRSHL_ZPmZ_H:
    case AArch64::UQRSHL_ZPmZ_S:
    case AArch64::UQSHLR_ZPmZ_B:
    case AArch64::UQSHLR_ZPmZ_D:
    case AArch64::UQSHLR_ZPmZ_H:
    case AArch64::UQSHLR_ZPmZ_S:
    case AArch64::UQSHL_ZPmZ_B:
    case AArch64::UQSHL_ZPmZ_D:
    case AArch64::UQSHL_ZPmZ_H:
    case AArch64::UQSHL_ZPmZ_S:
    case AArch64::UQSUBR_ZPmZ_B:
    case AArch64::UQSUBR_ZPmZ_D:
    case AArch64::UQSUBR_ZPmZ_H:
    case AArch64::UQSUBR_ZPmZ_S:
    case AArch64::UQSUB_ZPmZ_B:
    case AArch64::UQSUB_ZPmZ_D:
    case AArch64::UQSUB_ZPmZ_H:
    case AArch64::UQSUB_ZPmZ_S:
    case AArch64::URHADD_ZPmZ_B:
    case AArch64::URHADD_ZPmZ_D:
    case AArch64::URHADD_ZPmZ_H:
    case AArch64::URHADD_ZPmZ_S:
    case AArch64::URSHLR_ZPmZ_B:
    case AArch64::URSHLR_ZPmZ_D:
    case AArch64::URSHLR_ZPmZ_H:
    case AArch64::URSHLR_ZPmZ_S:
    case AArch64::URSHL_ZPmZ_B:
    case AArch64::URSHL_ZPmZ_D:
    case AArch64::URSHL_ZPmZ_H:
    case AArch64::URSHL_ZPmZ_S:
    case AArch64::USQADD_ZPmZ_B:
    case AArch64::USQADD_ZPmZ_D:
    case AArch64::USQADD_ZPmZ_H:
    case AArch64::USQADD_ZPmZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::EXPAND_ZPZ_B:
    case AArch64::EXPAND_ZPZ_D:
    case AArch64::EXPAND_ZPZ_H:
    case AArch64::EXPAND_ZPZ_S:
    case AArch64::SPLICE_ZPZZ_B:
    case AArch64::SPLICE_ZPZZ_D:
    case AArch64::SPLICE_ZPZZ_H:
    case AArch64::SPLICE_ZPZZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::GLD1B_D_IMM:
    case AArch64::GLD1B_S_IMM:
    case AArch64::GLD1D_IMM:
    case AArch64::GLD1H_D_IMM:
    case AArch64::GLD1H_S_IMM:
    case AArch64::GLD1SB_D_IMM:
    case AArch64::GLD1SB_S_IMM:
    case AArch64::GLD1SH_D_IMM:
    case AArch64::GLD1SH_S_IMM:
    case AArch64::GLD1SW_D_IMM:
    case AArch64::GLD1W_D_IMM:
    case AArch64::GLD1W_IMM:
    case AArch64::GLDFF1B_D_IMM:
    case AArch64::GLDFF1B_S_IMM:
    case AArch64::GLDFF1D_IMM:
    case AArch64::GLDFF1H_D_IMM:
    case AArch64::GLDFF1H_S_IMM:
    case AArch64::GLDFF1SB_D_IMM:
    case AArch64::GLDFF1SB_S_IMM:
    case AArch64::GLDFF1SH_D_IMM:
    case AArch64::GLDFF1SH_S_IMM:
    case AArch64::GLDFF1SW_D_IMM:
    case AArch64::GLDFF1W_D_IMM:
    case AArch64::GLDFF1W_IMM: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::PRFB_D_PZI:
    case AArch64::PRFB_S_PZI:
    case AArch64::PRFD_D_PZI:
    case AArch64::PRFD_S_PZI:
    case AArch64::PRFH_D_PZI:
    case AArch64::PRFH_S_PZI:
    case AArch64::PRFW_D_PZI:
    case AArch64::PRFW_S_PZI: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: prfop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::SADALP_ZPmZ_D:
    case AArch64::SADALP_ZPmZ_H:
    case AArch64::SADALP_ZPmZ_S:
    case AArch64::UADALP_ZPmZ_D:
    case AArch64::UADALP_ZPmZ_H:
    case AArch64::UADALP_ZPmZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::SST1B_D_IMM:
    case AArch64::SST1B_S_IMM:
    case AArch64::SST1D_IMM:
    case AArch64::SST1H_D_IMM:
    case AArch64::SST1H_S_IMM:
    case AArch64::SST1W_D_IMM:
    case AArch64::SST1W_IMM: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::CNTP_XPP_B:
    case AArch64::CNTP_XPP_D:
    case AArch64::CNTP_XPP_H:
    case AArch64::CNTP_XPP_S:
    case AArch64::FIRSTP_XPP_B:
    case AArch64::FIRSTP_XPP_D:
    case AArch64::FIRSTP_XPP_H:
    case AArch64::FIRSTP_XPP_S:
    case AArch64::LASTP_XPP_B:
    case AArch64::LASTP_XPP_D:
    case AArch64::LASTP_XPP_H:
    case AArch64::LASTP_XPP_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::SEL_ZPZZ_B:
    case AArch64::SEL_ZPZZ_D:
    case AArch64::SEL_ZPZZ_H:
    case AArch64::SEL_ZPZZ_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::CPY_ZPmR_B:
    case AArch64::CPY_ZPmR_D:
    case AArch64::CPY_ZPmR_H:
    case AArch64::CPY_ZPmR_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::CPY_ZPmV_B:
    case AArch64::CPY_ZPmV_D:
    case AArch64::CPY_ZPmV_H:
    case AArch64::CPY_ZPmV_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::ABS_ZPmZ_B:
    case AArch64::ABS_ZPmZ_D:
    case AArch64::ABS_ZPmZ_H:
    case AArch64::ABS_ZPmZ_S:
    case AArch64::BFCVT_ZPmZ:
    case AArch64::CLS_ZPmZ_B:
    case AArch64::CLS_ZPmZ_D:
    case AArch64::CLS_ZPmZ_H:
    case AArch64::CLS_ZPmZ_S:
    case AArch64::CLZ_ZPmZ_B:
    case AArch64::CLZ_ZPmZ_D:
    case AArch64::CLZ_ZPmZ_H:
    case AArch64::CLZ_ZPmZ_S:
    case AArch64::CNOT_ZPmZ_B:
    case AArch64::CNOT_ZPmZ_D:
    case AArch64::CNOT_ZPmZ_H:
    case AArch64::CNOT_ZPmZ_S:
    case AArch64::CNT_ZPmZ_B:
    case AArch64::CNT_ZPmZ_D:
    case AArch64::CNT_ZPmZ_H:
    case AArch64::CNT_ZPmZ_S:
    case AArch64::FABS_ZPmZ_D:
    case AArch64::FABS_ZPmZ_H:
    case AArch64::FABS_ZPmZ_S:
    case AArch64::FCVTX_ZPmZ_DtoS:
    case AArch64::FCVTZS_ZPmZ_DtoD:
    case AArch64::FCVTZS_ZPmZ_DtoS:
    case AArch64::FCVTZS_ZPmZ_HtoD:
    case AArch64::FCVTZS_ZPmZ_HtoH:
    case AArch64::FCVTZS_ZPmZ_HtoS:
    case AArch64::FCVTZS_ZPmZ_StoD:
    case AArch64::FCVTZS_ZPmZ_StoS:
    case AArch64::FCVTZU_ZPmZ_DtoD:
    case AArch64::FCVTZU_ZPmZ_DtoS:
    case AArch64::FCVTZU_ZPmZ_HtoD:
    case AArch64::FCVTZU_ZPmZ_HtoH:
    case AArch64::FCVTZU_ZPmZ_HtoS:
    case AArch64::FCVTZU_ZPmZ_StoD:
    case AArch64::FCVTZU_ZPmZ_StoS:
    case AArch64::FCVT_ZPmZ_DtoH:
    case AArch64::FCVT_ZPmZ_DtoS:
    case AArch64::FCVT_ZPmZ_HtoD:
    case AArch64::FCVT_ZPmZ_HtoS:
    case AArch64::FCVT_ZPmZ_StoD:
    case AArch64::FCVT_ZPmZ_StoH:
    case AArch64::FLOGB_ZPmZ_D:
    case AArch64::FLOGB_ZPmZ_H:
    case AArch64::FLOGB_ZPmZ_S:
    case AArch64::FNEG_ZPmZ_D:
    case AArch64::FNEG_ZPmZ_H:
    case AArch64::FNEG_ZPmZ_S:
    case AArch64::FRECPX_ZPmZ_D:
    case AArch64::FRECPX_ZPmZ_H:
    case AArch64::FRECPX_ZPmZ_S:
    case AArch64::FRINT32X_ZPmZ_D:
    case AArch64::FRINT32X_ZPmZ_S:
    case AArch64::FRINT32Z_ZPmZ_D:
    case AArch64::FRINT32Z_ZPmZ_S:
    case AArch64::FRINT64X_ZPmZ_D:
    case AArch64::FRINT64X_ZPmZ_S:
    case AArch64::FRINT64Z_ZPmZ_D:
    case AArch64::FRINT64Z_ZPmZ_S:
    case AArch64::FRINTA_ZPmZ_D:
    case AArch64::FRINTA_ZPmZ_H:
    case AArch64::FRINTA_ZPmZ_S:
    case AArch64::FRINTI_ZPmZ_D:
    case AArch64::FRINTI_ZPmZ_H:
    case AArch64::FRINTI_ZPmZ_S:
    case AArch64::FRINTM_ZPmZ_D:
    case AArch64::FRINTM_ZPmZ_H:
    case AArch64::FRINTM_ZPmZ_S:
    case AArch64::FRINTN_ZPmZ_D:
    case AArch64::FRINTN_ZPmZ_H:
    case AArch64::FRINTN_ZPmZ_S:
    case AArch64::FRINTP_ZPmZ_D:
    case AArch64::FRINTP_ZPmZ_H:
    case AArch64::FRINTP_ZPmZ_S:
    case AArch64::FRINTX_ZPmZ_D:
    case AArch64::FRINTX_ZPmZ_H:
    case AArch64::FRINTX_ZPmZ_S:
    case AArch64::FRINTZ_ZPmZ_D:
    case AArch64::FRINTZ_ZPmZ_H:
    case AArch64::FRINTZ_ZPmZ_S:
    case AArch64::FSQRT_ZPmZ_D:
    case AArch64::FSQRT_ZPmZ_H:
    case AArch64::FSQRT_ZPmZ_S:
    case AArch64::MOVPRFX_ZPmZ_B:
    case AArch64::MOVPRFX_ZPmZ_D:
    case AArch64::MOVPRFX_ZPmZ_H:
    case AArch64::MOVPRFX_ZPmZ_S:
    case AArch64::NEG_ZPmZ_B:
    case AArch64::NEG_ZPmZ_D:
    case AArch64::NEG_ZPmZ_H:
    case AArch64::NEG_ZPmZ_S:
    case AArch64::NOT_ZPmZ_B:
    case AArch64::NOT_ZPmZ_D:
    case AArch64::NOT_ZPmZ_H:
    case AArch64::NOT_ZPmZ_S:
    case AArch64::SCVTF_ZPmZ_DtoD:
    case AArch64::SCVTF_ZPmZ_DtoH:
    case AArch64::SCVTF_ZPmZ_DtoS:
    case AArch64::SCVTF_ZPmZ_HtoH:
    case AArch64::SCVTF_ZPmZ_StoD:
    case AArch64::SCVTF_ZPmZ_StoH:
    case AArch64::SCVTF_ZPmZ_StoS:
    case AArch64::SQABS_ZPmZ_B:
    case AArch64::SQABS_ZPmZ_D:
    case AArch64::SQABS_ZPmZ_H:
    case AArch64::SQABS_ZPmZ_S:
    case AArch64::SQNEG_ZPmZ_B:
    case AArch64::SQNEG_ZPmZ_D:
    case AArch64::SQNEG_ZPmZ_H:
    case AArch64::SQNEG_ZPmZ_S:
    case AArch64::SXTB_ZPmZ_D:
    case AArch64::SXTB_ZPmZ_H:
    case AArch64::SXTB_ZPmZ_S:
    case AArch64::SXTH_ZPmZ_D:
    case AArch64::SXTH_ZPmZ_S:
    case AArch64::SXTW_ZPmZ_D:
    case AArch64::UCVTF_ZPmZ_DtoD:
    case AArch64::UCVTF_ZPmZ_DtoH:
    case AArch64::UCVTF_ZPmZ_DtoS:
    case AArch64::UCVTF_ZPmZ_HtoH:
    case AArch64::UCVTF_ZPmZ_StoD:
    case AArch64::UCVTF_ZPmZ_StoH:
    case AArch64::UCVTF_ZPmZ_StoS:
    case AArch64::URECPE_ZPmZ_S:
    case AArch64::URSQRTE_ZPmZ_S:
    case AArch64::UXTB_ZPmZ_D:
    case AArch64::UXTB_ZPmZ_H:
    case AArch64::UXTB_ZPmZ_S:
    case AArch64::UXTH_ZPmZ_D:
    case AArch64::UXTH_ZPmZ_S:
    case AArch64::UXTW_ZPmZ_D: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::FCPY_ZPmI_D:
    case AArch64::FCPY_ZPmI_H:
    case AArch64::FCPY_ZPmI_S: {
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xff) << 5;
      break;
    }
    case AArch64::DECP_ZP_D:
    case AArch64::DECP_ZP_H:
    case AArch64::DECP_ZP_S:
    case AArch64::INCP_ZP_D:
    case AArch64::INCP_ZP_H:
    case AArch64::INCP_ZP_S:
    case AArch64::SQDECP_ZP_D:
    case AArch64::SQDECP_ZP_H:
    case AArch64::SQDECP_ZP_S:
    case AArch64::SQINCP_ZP_D:
    case AArch64::SQINCP_ZP_H:
    case AArch64::SQINCP_ZP_S:
    case AArch64::UQDECP_ZP_D:
    case AArch64::UQDECP_ZP_H:
    case AArch64::UQDECP_ZP_S:
    case AArch64::UQINCP_ZP_D:
    case AArch64::UQINCP_ZP_H:
    case AArch64::UQINCP_ZP_S: {
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::ADDHA_MPPZ_S:
    case AArch64::ADDVA_MPPZ_S: {
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 13;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::ADDHA_MPPZ_D:
    case AArch64::ADDVA_MPPZ_D: {
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 13;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::WRFFR: {
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::LDR_PXI:
    case AArch64::STR_PXI: {
      // op: Pt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm9
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f8) << 13;
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::XPACD:
    case AArch64::XPACI: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::CNTP_XCI_B:
    case AArch64::CNTP_XCI_D:
    case AArch64::CNTP_XCI_H:
    case AArch64::CNTP_XCI_S: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: PNn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: vl
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 10;
      break;
    }
    case AArch64::ADDPL_XXI:
    case AArch64::ADDSPL_XXI:
    case AArch64::ADDSVL_XXI:
    case AArch64::ADDVL_XXI: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3f) << 5;
      break;
    }
    case AArch64::ABSWr:
    case AArch64::ABSXr:
    case AArch64::ABSv16i8:
    case AArch64::ABSv1i64:
    case AArch64::ABSv2i32:
    case AArch64::ABSv2i64:
    case AArch64::ABSv4i16:
    case AArch64::ABSv4i32:
    case AArch64::ABSv8i16:
    case AArch64::ABSv8i8:
    case AArch64::ADDPv2i64p:
    case AArch64::ADDVv16i8v:
    case AArch64::ADDVv4i16v:
    case AArch64::ADDVv4i32v:
    case AArch64::ADDVv8i16v:
    case AArch64::ADDVv8i8v:
    case AArch64::AESIMCrr:
    case AArch64::AESMCrr:
    case AArch64::BF1CVTL:
    case AArch64::BF1CVTL2:
    case AArch64::BF2CVTL:
    case AArch64::BF2CVTL2:
    case AArch64::BFCVT:
    case AArch64::BFCVTN:
    case AArch64::CLSWr:
    case AArch64::CLSXr:
    case AArch64::CLSv16i8:
    case AArch64::CLSv2i32:
    case AArch64::CLSv4i16:
    case AArch64::CLSv4i32:
    case AArch64::CLSv8i16:
    case AArch64::CLSv8i8:
    case AArch64::CLZWr:
    case AArch64::CLZXr:
    case AArch64::CLZv16i8:
    case AArch64::CLZv2i32:
    case AArch64::CLZv4i16:
    case AArch64::CLZv4i32:
    case AArch64::CLZv8i16:
    case AArch64::CLZv8i8:
    case AArch64::CMEQv16i8rz:
    case AArch64::CMEQv1i64rz:
    case AArch64::CMEQv2i32rz:
    case AArch64::CMEQv2i64rz:
    case AArch64::CMEQv4i16rz:
    case AArch64::CMEQv4i32rz:
    case AArch64::CMEQv8i16rz:
    case AArch64::CMEQv8i8rz:
    case AArch64::CMGEv16i8rz:
    case AArch64::CMGEv1i64rz:
    case AArch64::CMGEv2i32rz:
    case AArch64::CMGEv2i64rz:
    case AArch64::CMGEv4i16rz:
    case AArch64::CMGEv4i32rz:
    case AArch64::CMGEv8i16rz:
    case AArch64::CMGEv8i8rz:
    case AArch64::CMGTv16i8rz:
    case AArch64::CMGTv1i64rz:
    case AArch64::CMGTv2i32rz:
    case AArch64::CMGTv2i64rz:
    case AArch64::CMGTv4i16rz:
    case AArch64::CMGTv4i32rz:
    case AArch64::CMGTv8i16rz:
    case AArch64::CMGTv8i8rz:
    case AArch64::CMLEv16i8rz:
    case AArch64::CMLEv1i64rz:
    case AArch64::CMLEv2i32rz:
    case AArch64::CMLEv2i64rz:
    case AArch64::CMLEv4i16rz:
    case AArch64::CMLEv4i32rz:
    case AArch64::CMLEv8i16rz:
    case AArch64::CMLEv8i8rz:
    case AArch64::CMLTv16i8rz:
    case AArch64::CMLTv1i64rz:
    case AArch64::CMLTv2i32rz:
    case AArch64::CMLTv2i64rz:
    case AArch64::CMLTv4i16rz:
    case AArch64::CMLTv4i32rz:
    case AArch64::CMLTv8i16rz:
    case AArch64::CMLTv8i8rz:
    case AArch64::CNTWr:
    case AArch64::CNTXr:
    case AArch64::CNTv16i8:
    case AArch64::CNTv8i8:
    case AArch64::CTZWr:
    case AArch64::CTZXr:
    case AArch64::DUPv16i8gpr:
    case AArch64::DUPv2i32gpr:
    case AArch64::DUPv2i64gpr:
    case AArch64::DUPv4i16gpr:
    case AArch64::DUPv4i32gpr:
    case AArch64::DUPv8i16gpr:
    case AArch64::DUPv8i8gpr:
    case AArch64::F1CVTL:
    case AArch64::F1CVTL2:
    case AArch64::F2CVTL:
    case AArch64::F2CVTL2:
    case AArch64::FABSDr:
    case AArch64::FABSHr:
    case AArch64::FABSSr:
    case AArch64::FABSv2f32:
    case AArch64::FABSv2f64:
    case AArch64::FABSv4f16:
    case AArch64::FABSv4f32:
    case AArch64::FABSv8f16:
    case AArch64::FADDPv2i16p:
    case AArch64::FADDPv2i32p:
    case AArch64::FADDPv2i64p:
    case AArch64::FCMEQv1i16rz:
    case AArch64::FCMEQv1i32rz:
    case AArch64::FCMEQv1i64rz:
    case AArch64::FCMEQv2i32rz:
    case AArch64::FCMEQv2i64rz:
    case AArch64::FCMEQv4i16rz:
    case AArch64::FCMEQv4i32rz:
    case AArch64::FCMEQv8i16rz:
    case AArch64::FCMGEv1i16rz:
    case AArch64::FCMGEv1i32rz:
    case AArch64::FCMGEv1i64rz:
    case AArch64::FCMGEv2i32rz:
    case AArch64::FCMGEv2i64rz:
    case AArch64::FCMGEv4i16rz:
    case AArch64::FCMGEv4i32rz:
    case AArch64::FCMGEv8i16rz:
    case AArch64::FCMGTv1i16rz:
    case AArch64::FCMGTv1i32rz:
    case AArch64::FCMGTv1i64rz:
    case AArch64::FCMGTv2i32rz:
    case AArch64::FCMGTv2i64rz:
    case AArch64::FCMGTv4i16rz:
    case AArch64::FCMGTv4i32rz:
    case AArch64::FCMGTv8i16rz:
    case AArch64::FCMLEv1i16rz:
    case AArch64::FCMLEv1i32rz:
    case AArch64::FCMLEv1i64rz:
    case AArch64::FCMLEv2i32rz:
    case AArch64::FCMLEv2i64rz:
    case AArch64::FCMLEv4i16rz:
    case AArch64::FCMLEv4i32rz:
    case AArch64::FCMLEv8i16rz:
    case AArch64::FCMLTv1i16rz:
    case AArch64::FCMLTv1i32rz:
    case AArch64::FCMLTv1i64rz:
    case AArch64::FCMLTv2i32rz:
    case AArch64::FCMLTv2i64rz:
    case AArch64::FCMLTv4i16rz:
    case AArch64::FCMLTv4i32rz:
    case AArch64::FCMLTv8i16rz:
    case AArch64::FCVTASDHr:
    case AArch64::FCVTASDSr:
    case AArch64::FCVTASSDr:
    case AArch64::FCVTASSHr:
    case AArch64::FCVTASUWDr:
    case AArch64::FCVTASUWHr:
    case AArch64::FCVTASUWSr:
    case AArch64::FCVTASUXDr:
    case AArch64::FCVTASUXHr:
    case AArch64::FCVTASUXSr:
    case AArch64::FCVTASv1f16:
    case AArch64::FCVTASv1i32:
    case AArch64::FCVTASv1i64:
    case AArch64::FCVTASv2f32:
    case AArch64::FCVTASv2f64:
    case AArch64::FCVTASv4f16:
    case AArch64::FCVTASv4f32:
    case AArch64::FCVTASv8f16:
    case AArch64::FCVTAUDHr:
    case AArch64::FCVTAUDSr:
    case AArch64::FCVTAUSDr:
    case AArch64::FCVTAUSHr:
    case AArch64::FCVTAUUWDr:
    case AArch64::FCVTAUUWHr:
    case AArch64::FCVTAUUWSr:
    case AArch64::FCVTAUUXDr:
    case AArch64::FCVTAUUXHr:
    case AArch64::FCVTAUUXSr:
    case AArch64::FCVTAUv1f16:
    case AArch64::FCVTAUv1i32:
    case AArch64::FCVTAUv1i64:
    case AArch64::FCVTAUv2f32:
    case AArch64::FCVTAUv2f64:
    case AArch64::FCVTAUv4f16:
    case AArch64::FCVTAUv4f32:
    case AArch64::FCVTAUv8f16:
    case AArch64::FCVTDHr:
    case AArch64::FCVTDSr:
    case AArch64::FCVTHDr:
    case AArch64::FCVTHSr:
    case AArch64::FCVTLv2i32:
    case AArch64::FCVTLv4i16:
    case AArch64::FCVTLv4i32:
    case AArch64::FCVTLv8i16:
    case AArch64::FCVTMSDHr:
    case AArch64::FCVTMSDSr:
    case AArch64::FCVTMSSDr:
    case AArch64::FCVTMSSHr:
    case AArch64::FCVTMSUWDr:
    case AArch64::FCVTMSUWHr:
    case AArch64::FCVTMSUWSr:
    case AArch64::FCVTMSUXDr:
    case AArch64::FCVTMSUXHr:
    case AArch64::FCVTMSUXSr:
    case AArch64::FCVTMSv1f16:
    case AArch64::FCVTMSv1i32:
    case AArch64::FCVTMSv1i64:
    case AArch64::FCVTMSv2f32:
    case AArch64::FCVTMSv2f64:
    case AArch64::FCVTMSv4f16:
    case AArch64::FCVTMSv4f32:
    case AArch64::FCVTMSv8f16:
    case AArch64::FCVTMUDHr:
    case AArch64::FCVTMUDSr:
    case AArch64::FCVTMUSDr:
    case AArch64::FCVTMUSHr:
    case AArch64::FCVTMUUWDr:
    case AArch64::FCVTMUUWHr:
    case AArch64::FCVTMUUWSr:
    case AArch64::FCVTMUUXDr:
    case AArch64::FCVTMUUXHr:
    case AArch64::FCVTMUUXSr:
    case AArch64::FCVTMUv1f16:
    case AArch64::FCVTMUv1i32:
    case AArch64::FCVTMUv1i64:
    case AArch64::FCVTMUv2f32:
    case AArch64::FCVTMUv2f64:
    case AArch64::FCVTMUv4f16:
    case AArch64::FCVTMUv4f32:
    case AArch64::FCVTMUv8f16:
    case AArch64::FCVTNSDHr:
    case AArch64::FCVTNSDSr:
    case AArch64::FCVTNSSDr:
    case AArch64::FCVTNSSHr:
    case AArch64::FCVTNSUWDr:
    case AArch64::FCVTNSUWHr:
    case AArch64::FCVTNSUWSr:
    case AArch64::FCVTNSUXDr:
    case AArch64::FCVTNSUXHr:
    case AArch64::FCVTNSUXSr:
    case AArch64::FCVTNSv1f16:
    case AArch64::FCVTNSv1i32:
    case AArch64::FCVTNSv1i64:
    case AArch64::FCVTNSv2f32:
    case AArch64::FCVTNSv2f64:
    case AArch64::FCVTNSv4f16:
    case AArch64::FCVTNSv4f32:
    case AArch64::FCVTNSv8f16:
    case AArch64::FCVTNUDHr:
    case AArch64::FCVTNUDSr:
    case AArch64::FCVTNUSDr:
    case AArch64::FCVTNUSHr:
    case AArch64::FCVTNUUWDr:
    case AArch64::FCVTNUUWHr:
    case AArch64::FCVTNUUWSr:
    case AArch64::FCVTNUUXDr:
    case AArch64::FCVTNUUXHr:
    case AArch64::FCVTNUUXSr:
    case AArch64::FCVTNUv1f16:
    case AArch64::FCVTNUv1i32:
    case AArch64::FCVTNUv1i64:
    case AArch64::FCVTNUv2f32:
    case AArch64::FCVTNUv2f64:
    case AArch64::FCVTNUv4f16:
    case AArch64::FCVTNUv4f32:
    case AArch64::FCVTNUv8f16:
    case AArch64::FCVTNv2i32:
    case AArch64::FCVTNv4i16:
    case AArch64::FCVTPSDHr:
    case AArch64::FCVTPSDSr:
    case AArch64::FCVTPSSDr:
    case AArch64::FCVTPSSHr:
    case AArch64::FCVTPSUWDr:
    case AArch64::FCVTPSUWHr:
    case AArch64::FCVTPSUWSr:
    case AArch64::FCVTPSUXDr:
    case AArch64::FCVTPSUXHr:
    case AArch64::FCVTPSUXSr:
    case AArch64::FCVTPSv1f16:
    case AArch64::FCVTPSv1i32:
    case AArch64::FCVTPSv1i64:
    case AArch64::FCVTPSv2f32:
    case AArch64::FCVTPSv2f64:
    case AArch64::FCVTPSv4f16:
    case AArch64::FCVTPSv4f32:
    case AArch64::FCVTPSv8f16:
    case AArch64::FCVTPUDHr:
    case AArch64::FCVTPUDSr:
    case AArch64::FCVTPUSDr:
    case AArch64::FCVTPUSHr:
    case AArch64::FCVTPUUWDr:
    case AArch64::FCVTPUUWHr:
    case AArch64::FCVTPUUWSr:
    case AArch64::FCVTPUUXDr:
    case AArch64::FCVTPUUXHr:
    case AArch64::FCVTPUUXSr:
    case AArch64::FCVTPUv1f16:
    case AArch64::FCVTPUv1i32:
    case AArch64::FCVTPUv1i64:
    case AArch64::FCVTPUv2f32:
    case AArch64::FCVTPUv2f64:
    case AArch64::FCVTPUv4f16:
    case AArch64::FCVTPUv4f32:
    case AArch64::FCVTPUv8f16:
    case AArch64::FCVTSDr:
    case AArch64::FCVTSHr:
    case AArch64::FCVTXNv1i64:
    case AArch64::FCVTXNv2f32:
    case AArch64::FCVTZSDHr:
    case AArch64::FCVTZSDSr:
    case AArch64::FCVTZSSDr:
    case AArch64::FCVTZSSHr:
    case AArch64::FCVTZSUWDr:
    case AArch64::FCVTZSUWHr:
    case AArch64::FCVTZSUWSr:
    case AArch64::FCVTZSUXDr:
    case AArch64::FCVTZSUXHr:
    case AArch64::FCVTZSUXSr:
    case AArch64::FCVTZSv1f16:
    case AArch64::FCVTZSv1i32:
    case AArch64::FCVTZSv1i64:
    case AArch64::FCVTZSv2f32:
    case AArch64::FCVTZSv2f64:
    case AArch64::FCVTZSv4f16:
    case AArch64::FCVTZSv4f32:
    case AArch64::FCVTZSv8f16:
    case AArch64::FCVTZUDHr:
    case AArch64::FCVTZUDSr:
    case AArch64::FCVTZUSDr:
    case AArch64::FCVTZUSHr:
    case AArch64::FCVTZUUWDr:
    case AArch64::FCVTZUUWHr:
    case AArch64::FCVTZUUWSr:
    case AArch64::FCVTZUUXDr:
    case AArch64::FCVTZUUXHr:
    case AArch64::FCVTZUUXSr:
    case AArch64::FCVTZUv1f16:
    case AArch64::FCVTZUv1i32:
    case AArch64::FCVTZUv1i64:
    case AArch64::FCVTZUv2f32:
    case AArch64::FCVTZUv2f64:
    case AArch64::FCVTZUv4f16:
    case AArch64::FCVTZUv4f32:
    case AArch64::FCVTZUv8f16:
    case AArch64::FJCVTZS:
    case AArch64::FMAXNMPv2i16p:
    case AArch64::FMAXNMPv2i32p:
    case AArch64::FMAXNMPv2i64p:
    case AArch64::FMAXNMVv4i16v:
    case AArch64::FMAXNMVv4i32v:
    case AArch64::FMAXNMVv8i16v:
    case AArch64::FMAXPv2i16p:
    case AArch64::FMAXPv2i32p:
    case AArch64::FMAXPv2i64p:
    case AArch64::FMAXVv4i16v:
    case AArch64::FMAXVv4i32v:
    case AArch64::FMAXVv8i16v:
    case AArch64::FMINNMPv2i16p:
    case AArch64::FMINNMPv2i32p:
    case AArch64::FMINNMPv2i64p:
    case AArch64::FMINNMVv4i16v:
    case AArch64::FMINNMVv4i32v:
    case AArch64::FMINNMVv8i16v:
    case AArch64::FMINPv2i16p:
    case AArch64::FMINPv2i32p:
    case AArch64::FMINPv2i64p:
    case AArch64::FMINVv4i16v:
    case AArch64::FMINVv4i32v:
    case AArch64::FMINVv8i16v:
    case AArch64::FMOVDXHighr:
    case AArch64::FMOVDXr:
    case AArch64::FMOVDr:
    case AArch64::FMOVHWr:
    case AArch64::FMOVHXr:
    case AArch64::FMOVHr:
    case AArch64::FMOVSWr:
    case AArch64::FMOVSr:
    case AArch64::FMOVWHr:
    case AArch64::FMOVWSr:
    case AArch64::FMOVXDHighr:
    case AArch64::FMOVXDr:
    case AArch64::FMOVXHr:
    case AArch64::FNEGDr:
    case AArch64::FNEGHr:
    case AArch64::FNEGSr:
    case AArch64::FNEGv2f32:
    case AArch64::FNEGv2f64:
    case AArch64::FNEGv4f16:
    case AArch64::FNEGv4f32:
    case AArch64::FNEGv8f16:
    case AArch64::FRECPEv1f16:
    case AArch64::FRECPEv1i32:
    case AArch64::FRECPEv1i64:
    case AArch64::FRECPEv2f32:
    case AArch64::FRECPEv2f64:
    case AArch64::FRECPEv4f16:
    case AArch64::FRECPEv4f32:
    case AArch64::FRECPEv8f16:
    case AArch64::FRECPXv1f16:
    case AArch64::FRECPXv1i32:
    case AArch64::FRECPXv1i64:
    case AArch64::FRINT32XDr:
    case AArch64::FRINT32XSr:
    case AArch64::FRINT32Xv2f32:
    case AArch64::FRINT32Xv2f64:
    case AArch64::FRINT32Xv4f32:
    case AArch64::FRINT32ZDr:
    case AArch64::FRINT32ZSr:
    case AArch64::FRINT32Zv2f32:
    case AArch64::FRINT32Zv2f64:
    case AArch64::FRINT32Zv4f32:
    case AArch64::FRINT64XDr:
    case AArch64::FRINT64XSr:
    case AArch64::FRINT64Xv2f32:
    case AArch64::FRINT64Xv2f64:
    case AArch64::FRINT64Xv4f32:
    case AArch64::FRINT64ZDr:
    case AArch64::FRINT64ZSr:
    case AArch64::FRINT64Zv2f32:
    case AArch64::FRINT64Zv2f64:
    case AArch64::FRINT64Zv4f32:
    case AArch64::FRINTADr:
    case AArch64::FRINTAHr:
    case AArch64::FRINTASr:
    case AArch64::FRINTAv2f32:
    case AArch64::FRINTAv2f64:
    case AArch64::FRINTAv4f16:
    case AArch64::FRINTAv4f32:
    case AArch64::FRINTAv8f16:
    case AArch64::FRINTIDr:
    case AArch64::FRINTIHr:
    case AArch64::FRINTISr:
    case AArch64::FRINTIv2f32:
    case AArch64::FRINTIv2f64:
    case AArch64::FRINTIv4f16:
    case AArch64::FRINTIv4f32:
    case AArch64::FRINTIv8f16:
    case AArch64::FRINTMDr:
    case AArch64::FRINTMHr:
    case AArch64::FRINTMSr:
    case AArch64::FRINTMv2f32:
    case AArch64::FRINTMv2f64:
    case AArch64::FRINTMv4f16:
    case AArch64::FRINTMv4f32:
    case AArch64::FRINTMv8f16:
    case AArch64::FRINTNDr:
    case AArch64::FRINTNHr:
    case AArch64::FRINTNSr:
    case AArch64::FRINTNv2f32:
    case AArch64::FRINTNv2f64:
    case AArch64::FRINTNv4f16:
    case AArch64::FRINTNv4f32:
    case AArch64::FRINTNv8f16:
    case AArch64::FRINTPDr:
    case AArch64::FRINTPHr:
    case AArch64::FRINTPSr:
    case AArch64::FRINTPv2f32:
    case AArch64::FRINTPv2f64:
    case AArch64::FRINTPv4f16:
    case AArch64::FRINTPv4f32:
    case AArch64::FRINTPv8f16:
    case AArch64::FRINTXDr:
    case AArch64::FRINTXHr:
    case AArch64::FRINTXSr:
    case AArch64::FRINTXv2f32:
    case AArch64::FRINTXv2f64:
    case AArch64::FRINTXv4f16:
    case AArch64::FRINTXv4f32:
    case AArch64::FRINTXv8f16:
    case AArch64::FRINTZDr:
    case AArch64::FRINTZHr:
    case AArch64::FRINTZSr:
    case AArch64::FRINTZv2f32:
    case AArch64::FRINTZv2f64:
    case AArch64::FRINTZv4f16:
    case AArch64::FRINTZv4f32:
    case AArch64::FRINTZv8f16:
    case AArch64::FRSQRTEv1f16:
    case AArch64::FRSQRTEv1i32:
    case AArch64::FRSQRTEv1i64:
    case AArch64::FRSQRTEv2f32:
    case AArch64::FRSQRTEv2f64:
    case AArch64::FRSQRTEv4f16:
    case AArch64::FRSQRTEv4f32:
    case AArch64::FRSQRTEv8f16:
    case AArch64::FSQRTDr:
    case AArch64::FSQRTHr:
    case AArch64::FSQRTSr:
    case AArch64::FSQRTv2f32:
    case AArch64::FSQRTv2f64:
    case AArch64::FSQRTv4f16:
    case AArch64::FSQRTv4f32:
    case AArch64::FSQRTv8f16:
    case AArch64::NEGv16i8:
    case AArch64::NEGv1i64:
    case AArch64::NEGv2i32:
    case AArch64::NEGv2i64:
    case AArch64::NEGv4i16:
    case AArch64::NEGv4i32:
    case AArch64::NEGv8i16:
    case AArch64::NEGv8i8:
    case AArch64::NOTv16i8:
    case AArch64::NOTv8i8:
    case AArch64::RBITWr:
    case AArch64::RBITXr:
    case AArch64::RBITv16i8:
    case AArch64::RBITv8i8:
    case AArch64::REV16Wr:
    case AArch64::REV16Xr:
    case AArch64::REV16v16i8:
    case AArch64::REV16v8i8:
    case AArch64::REV32Xr:
    case AArch64::REV32v16i8:
    case AArch64::REV32v4i16:
    case AArch64::REV32v8i16:
    case AArch64::REV32v8i8:
    case AArch64::REV64v16i8:
    case AArch64::REV64v2i32:
    case AArch64::REV64v4i16:
    case AArch64::REV64v4i32:
    case AArch64::REV64v8i16:
    case AArch64::REV64v8i8:
    case AArch64::REVWr:
    case AArch64::REVXr:
    case AArch64::SADDLPv16i8_v8i16:
    case AArch64::SADDLPv2i32_v1i64:
    case AArch64::SADDLPv4i16_v2i32:
    case AArch64::SADDLPv4i32_v2i64:
    case AArch64::SADDLPv8i16_v4i32:
    case AArch64::SADDLPv8i8_v4i16:
    case AArch64::SADDLVv16i8v:
    case AArch64::SADDLVv4i16v:
    case AArch64::SADDLVv4i32v:
    case AArch64::SADDLVv8i16v:
    case AArch64::SADDLVv8i8v:
    case AArch64::SCVTFDSr:
    case AArch64::SCVTFHDr:
    case AArch64::SCVTFHSr:
    case AArch64::SCVTFSDr:
    case AArch64::SCVTFUWDri:
    case AArch64::SCVTFUWHri:
    case AArch64::SCVTFUWSri:
    case AArch64::SCVTFUXDri:
    case AArch64::SCVTFUXHri:
    case AArch64::SCVTFUXSri:
    case AArch64::SCVTFv1i16:
    case AArch64::SCVTFv1i32:
    case AArch64::SCVTFv1i64:
    case AArch64::SCVTFv2f32:
    case AArch64::SCVTFv2f64:
    case AArch64::SCVTFv4f16:
    case AArch64::SCVTFv4f32:
    case AArch64::SCVTFv8f16:
    case AArch64::SHA1Hrr:
    case AArch64::SHLLv16i8:
    case AArch64::SHLLv2i32:
    case AArch64::SHLLv4i16:
    case AArch64::SHLLv4i32:
    case AArch64::SHLLv8i16:
    case AArch64::SHLLv8i8:
    case AArch64::SMAXVv16i8v:
    case AArch64::SMAXVv4i16v:
    case AArch64::SMAXVv4i32v:
    case AArch64::SMAXVv8i16v:
    case AArch64::SMAXVv8i8v:
    case AArch64::SMINVv16i8v:
    case AArch64::SMINVv4i16v:
    case AArch64::SMINVv4i32v:
    case AArch64::SMINVv8i16v:
    case AArch64::SMINVv8i8v:
    case AArch64::SMOVvi16to32_idx0:
    case AArch64::SMOVvi16to64_idx0:
    case AArch64::SMOVvi32to64_idx0:
    case AArch64::SMOVvi8to32_idx0:
    case AArch64::SMOVvi8to64_idx0:
    case AArch64::SQABSv16i8:
    case AArch64::SQABSv1i16:
    case AArch64::SQABSv1i32:
    case AArch64::SQABSv1i64:
    case AArch64::SQABSv1i8:
    case AArch64::SQABSv2i32:
    case AArch64::SQABSv2i64:
    case AArch64::SQABSv4i16:
    case AArch64::SQABSv4i32:
    case AArch64::SQABSv8i16:
    case AArch64::SQABSv8i8:
    case AArch64::SQNEGv16i8:
    case AArch64::SQNEGv1i16:
    case AArch64::SQNEGv1i32:
    case AArch64::SQNEGv1i64:
    case AArch64::SQNEGv1i8:
    case AArch64::SQNEGv2i32:
    case AArch64::SQNEGv2i64:
    case AArch64::SQNEGv4i16:
    case AArch64::SQNEGv4i32:
    case AArch64::SQNEGv8i16:
    case AArch64::SQNEGv8i8:
    case AArch64::SQXTNv1i16:
    case AArch64::SQXTNv1i32:
    case AArch64::SQXTNv1i8:
    case AArch64::SQXTNv2i32:
    case AArch64::SQXTNv4i16:
    case AArch64::SQXTNv8i8:
    case AArch64::SQXTUNv1i16:
    case AArch64::SQXTUNv1i32:
    case AArch64::SQXTUNv1i8:
    case AArch64::SQXTUNv2i32:
    case AArch64::SQXTUNv4i16:
    case AArch64::SQXTUNv8i8:
    case AArch64::UADDLPv16i8_v8i16:
    case AArch64::UADDLPv2i32_v1i64:
    case AArch64::UADDLPv4i16_v2i32:
    case AArch64::UADDLPv4i32_v2i64:
    case AArch64::UADDLPv8i16_v4i32:
    case AArch64::UADDLPv8i8_v4i16:
    case AArch64::UADDLVv16i8v:
    case AArch64::UADDLVv4i16v:
    case AArch64::UADDLVv4i32v:
    case AArch64::UADDLVv8i16v:
    case AArch64::UADDLVv8i8v:
    case AArch64::UCVTFDSr:
    case AArch64::UCVTFHDr:
    case AArch64::UCVTFHSr:
    case AArch64::UCVTFSDr:
    case AArch64::UCVTFUWDri:
    case AArch64::UCVTFUWHri:
    case AArch64::UCVTFUWSri:
    case AArch64::UCVTFUXDri:
    case AArch64::UCVTFUXHri:
    case AArch64::UCVTFUXSri:
    case AArch64::UCVTFv1i16:
    case AArch64::UCVTFv1i32:
    case AArch64::UCVTFv1i64:
    case AArch64::UCVTFv2f32:
    case AArch64::UCVTFv2f64:
    case AArch64::UCVTFv4f16:
    case AArch64::UCVTFv4f32:
    case AArch64::UCVTFv8f16:
    case AArch64::UMAXVv16i8v:
    case AArch64::UMAXVv4i16v:
    case AArch64::UMAXVv4i32v:
    case AArch64::UMAXVv8i16v:
    case AArch64::UMAXVv8i8v:
    case AArch64::UMINVv16i8v:
    case AArch64::UMINVv4i16v:
    case AArch64::UMINVv4i32v:
    case AArch64::UMINVv8i16v:
    case AArch64::UMINVv8i8v:
    case AArch64::UMOVvi16_idx0:
    case AArch64::UMOVvi32_idx0:
    case AArch64::UMOVvi64_idx0:
    case AArch64::UMOVvi8_idx0:
    case AArch64::UQXTNv1i16:
    case AArch64::UQXTNv1i32:
    case AArch64::UQXTNv1i8:
    case AArch64::UQXTNv2i32:
    case AArch64::UQXTNv4i16:
    case AArch64::UQXTNv8i8:
    case AArch64::URECPEv2i32:
    case AArch64::URECPEv4i32:
    case AArch64::URSQRTEv2i32:
    case AArch64::URSQRTEv4i32:
    case AArch64::XTNv2i32:
    case AArch64::XTNv4i16:
    case AArch64::XTNv8i8: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::ADCSWr:
    case AArch64::ADCSXr:
    case AArch64::ADCWr:
    case AArch64::ADCXr:
    case AArch64::ADDHNv2i64_v2i32:
    case AArch64::ADDHNv4i32_v4i16:
    case AArch64::ADDHNv8i16_v8i8:
    case AArch64::ADDPv16i8:
    case AArch64::ADDPv2i32:
    case AArch64::ADDPv2i64:
    case AArch64::ADDPv4i16:
    case AArch64::ADDPv4i32:
    case AArch64::ADDPv8i16:
    case AArch64::ADDPv8i8:
    case AArch64::ADDv16i8:
    case AArch64::ADDv1i64:
    case AArch64::ADDv2i32:
    case AArch64::ADDv2i64:
    case AArch64::ADDv4i16:
    case AArch64::ADDv4i32:
    case AArch64::ADDv8i16:
    case AArch64::ADDv8i8:
    case AArch64::ANDv16i8:
    case AArch64::ANDv8i8:
    case AArch64::ASRVWr:
    case AArch64::ASRVXr:
    case AArch64::BICv16i8:
    case AArch64::BICv8i8:
    case AArch64::CMEQv16i8:
    case AArch64::CMEQv1i64:
    case AArch64::CMEQv2i32:
    case AArch64::CMEQv2i64:
    case AArch64::CMEQv4i16:
    case AArch64::CMEQv4i32:
    case AArch64::CMEQv8i16:
    case AArch64::CMEQv8i8:
    case AArch64::CMGEv16i8:
    case AArch64::CMGEv1i64:
    case AArch64::CMGEv2i32:
    case AArch64::CMGEv2i64:
    case AArch64::CMGEv4i16:
    case AArch64::CMGEv4i32:
    case AArch64::CMGEv8i16:
    case AArch64::CMGEv8i8:
    case AArch64::CMGTv16i8:
    case AArch64::CMGTv1i64:
    case AArch64::CMGTv2i32:
    case AArch64::CMGTv2i64:
    case AArch64::CMGTv4i16:
    case AArch64::CMGTv4i32:
    case AArch64::CMGTv8i16:
    case AArch64::CMGTv8i8:
    case AArch64::CMHIv16i8:
    case AArch64::CMHIv1i64:
    case AArch64::CMHIv2i32:
    case AArch64::CMHIv2i64:
    case AArch64::CMHIv4i16:
    case AArch64::CMHIv4i32:
    case AArch64::CMHIv8i16:
    case AArch64::CMHIv8i8:
    case AArch64::CMHSv16i8:
    case AArch64::CMHSv1i64:
    case AArch64::CMHSv2i32:
    case AArch64::CMHSv2i64:
    case AArch64::CMHSv4i16:
    case AArch64::CMHSv4i32:
    case AArch64::CMHSv8i16:
    case AArch64::CMHSv8i8:
    case AArch64::CMTSTv16i8:
    case AArch64::CMTSTv1i64:
    case AArch64::CMTSTv2i32:
    case AArch64::CMTSTv2i64:
    case AArch64::CMTSTv4i16:
    case AArch64::CMTSTv4i32:
    case AArch64::CMTSTv8i16:
    case AArch64::CMTSTv8i8:
    case AArch64::CRC32Brr:
    case AArch64::CRC32CBrr:
    case AArch64::CRC32CHrr:
    case AArch64::CRC32CWrr:
    case AArch64::CRC32CXrr:
    case AArch64::CRC32Hrr:
    case AArch64::CRC32Wrr:
    case AArch64::CRC32Xrr:
    case AArch64::EORv16i8:
    case AArch64::EORv8i8:
    case AArch64::FABD16:
    case AArch64::FABD32:
    case AArch64::FABD64:
    case AArch64::FABDv2f32:
    case AArch64::FABDv2f64:
    case AArch64::FABDv4f16:
    case AArch64::FABDv4f32:
    case AArch64::FABDv8f16:
    case AArch64::FACGE16:
    case AArch64::FACGE32:
    case AArch64::FACGE64:
    case AArch64::FACGEv2f32:
    case AArch64::FACGEv2f64:
    case AArch64::FACGEv4f16:
    case AArch64::FACGEv4f32:
    case AArch64::FACGEv8f16:
    case AArch64::FACGT16:
    case AArch64::FACGT32:
    case AArch64::FACGT64:
    case AArch64::FACGTv2f32:
    case AArch64::FACGTv2f64:
    case AArch64::FACGTv4f16:
    case AArch64::FACGTv4f32:
    case AArch64::FACGTv8f16:
    case AArch64::FADDDrr:
    case AArch64::FADDHrr:
    case AArch64::FADDPv2f32:
    case AArch64::FADDPv2f64:
    case AArch64::FADDPv4f16:
    case AArch64::FADDPv4f32:
    case AArch64::FADDPv8f16:
    case AArch64::FADDSrr:
    case AArch64::FADDv2f32:
    case AArch64::FADDv2f64:
    case AArch64::FADDv4f16:
    case AArch64::FADDv4f32:
    case AArch64::FADDv8f16:
    case AArch64::FAMAXv2f32:
    case AArch64::FAMAXv2f64:
    case AArch64::FAMAXv4f16:
    case AArch64::FAMAXv4f32:
    case AArch64::FAMAXv8f16:
    case AArch64::FAMINv2f32:
    case AArch64::FAMINv2f64:
    case AArch64::FAMINv4f16:
    case AArch64::FAMINv4f32:
    case AArch64::FAMINv8f16:
    case AArch64::FCMEQ16:
    case AArch64::FCMEQ32:
    case AArch64::FCMEQ64:
    case AArch64::FCMEQv2f32:
    case AArch64::FCMEQv2f64:
    case AArch64::FCMEQv4f16:
    case AArch64::FCMEQv4f32:
    case AArch64::FCMEQv8f16:
    case AArch64::FCMGE16:
    case AArch64::FCMGE32:
    case AArch64::FCMGE64:
    case AArch64::FCMGEv2f32:
    case AArch64::FCMGEv2f64:
    case AArch64::FCMGEv4f16:
    case AArch64::FCMGEv4f32:
    case AArch64::FCMGEv8f16:
    case AArch64::FCMGT16:
    case AArch64::FCMGT32:
    case AArch64::FCMGT64:
    case AArch64::FCMGTv2f32:
    case AArch64::FCMGTv2f64:
    case AArch64::FCMGTv4f16:
    case AArch64::FCMGTv4f32:
    case AArch64::FCMGTv8f16:
    case AArch64::FCVTN_F16v16f8:
    case AArch64::FCVTN_F16v8f8:
    case AArch64::FCVTN_F32v8f8:
    case AArch64::FDIVDrr:
    case AArch64::FDIVHrr:
    case AArch64::FDIVSrr:
    case AArch64::FDIVv2f32:
    case AArch64::FDIVv2f64:
    case AArch64::FDIVv4f16:
    case AArch64::FDIVv4f32:
    case AArch64::FDIVv8f16:
    case AArch64::FMAXDrr:
    case AArch64::FMAXHrr:
    case AArch64::FMAXNMDrr:
    case AArch64::FMAXNMHrr:
    case AArch64::FMAXNMPv2f32:
    case AArch64::FMAXNMPv2f64:
    case AArch64::FMAXNMPv4f16:
    case AArch64::FMAXNMPv4f32:
    case AArch64::FMAXNMPv8f16:
    case AArch64::FMAXNMSrr:
    case AArch64::FMAXNMv2f32:
    case AArch64::FMAXNMv2f64:
    case AArch64::FMAXNMv4f16:
    case AArch64::FMAXNMv4f32:
    case AArch64::FMAXNMv8f16:
    case AArch64::FMAXPv2f32:
    case AArch64::FMAXPv2f64:
    case AArch64::FMAXPv4f16:
    case AArch64::FMAXPv4f32:
    case AArch64::FMAXPv8f16:
    case AArch64::FMAXSrr:
    case AArch64::FMAXv2f32:
    case AArch64::FMAXv2f64:
    case AArch64::FMAXv4f16:
    case AArch64::FMAXv4f32:
    case AArch64::FMAXv8f16:
    case AArch64::FMINDrr:
    case AArch64::FMINHrr:
    case AArch64::FMINNMDrr:
    case AArch64::FMINNMHrr:
    case AArch64::FMINNMPv2f32:
    case AArch64::FMINNMPv2f64:
    case AArch64::FMINNMPv4f16:
    case AArch64::FMINNMPv4f32:
    case AArch64::FMINNMPv8f16:
    case AArch64::FMINNMSrr:
    case AArch64::FMINNMv2f32:
    case AArch64::FMINNMv2f64:
    case AArch64::FMINNMv4f16:
    case AArch64::FMINNMv4f32:
    case AArch64::FMINNMv8f16:
    case AArch64::FMINPv2f32:
    case AArch64::FMINPv2f64:
    case AArch64::FMINPv4f16:
    case AArch64::FMINPv4f32:
    case AArch64::FMINPv8f16:
    case AArch64::FMINSrr:
    case AArch64::FMINv2f32:
    case AArch64::FMINv2f64:
    case AArch64::FMINv4f16:
    case AArch64::FMINv4f32:
    case AArch64::FMINv8f16:
    case AArch64::FMULDrr:
    case AArch64::FMULHrr:
    case AArch64::FMULSrr:
    case AArch64::FMULX16:
    case AArch64::FMULX32:
    case AArch64::FMULX64:
    case AArch64::FMULXv2f32:
    case AArch64::FMULXv2f64:
    case AArch64::FMULXv4f16:
    case AArch64::FMULXv4f32:
    case AArch64::FMULXv8f16:
    case AArch64::FMULv2f32:
    case AArch64::FMULv2f64:
    case AArch64::FMULv4f16:
    case AArch64::FMULv4f32:
    case AArch64::FMULv8f16:
    case AArch64::FNMULDrr:
    case AArch64::FNMULHrr:
    case AArch64::FNMULSrr:
    case AArch64::FRECPS16:
    case AArch64::FRECPS32:
    case AArch64::FRECPS64:
    case AArch64::FRECPSv2f32:
    case AArch64::FRECPSv2f64:
    case AArch64::FRECPSv4f16:
    case AArch64::FRECPSv4f32:
    case AArch64::FRECPSv8f16:
    case AArch64::FRSQRTS16:
    case AArch64::FRSQRTS32:
    case AArch64::FRSQRTS64:
    case AArch64::FRSQRTSv2f32:
    case AArch64::FRSQRTSv2f64:
    case AArch64::FRSQRTSv4f16:
    case AArch64::FRSQRTSv4f32:
    case AArch64::FRSQRTSv8f16:
    case AArch64::FSCALEv2f32:
    case AArch64::FSCALEv2f64:
    case AArch64::FSCALEv4f16:
    case AArch64::FSCALEv4f32:
    case AArch64::FSCALEv8f16:
    case AArch64::FSUBDrr:
    case AArch64::FSUBHrr:
    case AArch64::FSUBSrr:
    case AArch64::FSUBv2f32:
    case AArch64::FSUBv2f64:
    case AArch64::FSUBv4f16:
    case AArch64::FSUBv4f32:
    case AArch64::FSUBv8f16:
    case AArch64::GMI:
    case AArch64::IRG:
    case AArch64::LSLVWr:
    case AArch64::LSLVXr:
    case AArch64::LSRVWr:
    case AArch64::LSRVXr:
    case AArch64::MULv16i8:
    case AArch64::MULv2i32:
    case AArch64::MULv4i16:
    case AArch64::MULv4i32:
    case AArch64::MULv8i16:
    case AArch64::MULv8i8:
    case AArch64::ORNv16i8:
    case AArch64::ORNv8i8:
    case AArch64::ORRv16i8:
    case AArch64::ORRv8i8:
    case AArch64::PACGA:
    case AArch64::PMULLv16i8:
    case AArch64::PMULLv1i64:
    case AArch64::PMULLv2i64:
    case AArch64::PMULLv8i8:
    case AArch64::PMULv16i8:
    case AArch64::PMULv8i8:
    case AArch64::RADDHNv2i64_v2i32:
    case AArch64::RADDHNv4i32_v4i16:
    case AArch64::RADDHNv8i16_v8i8:
    case AArch64::RORVWr:
    case AArch64::RORVXr:
    case AArch64::RSUBHNv2i64_v2i32:
    case AArch64::RSUBHNv4i32_v4i16:
    case AArch64::RSUBHNv8i16_v8i8:
    case AArch64::SABDLv16i8_v8i16:
    case AArch64::SABDLv2i32_v2i64:
    case AArch64::SABDLv4i16_v4i32:
    case AArch64::SABDLv4i32_v2i64:
    case AArch64::SABDLv8i16_v4i32:
    case AArch64::SABDLv8i8_v8i16:
    case AArch64::SABDv16i8:
    case AArch64::SABDv2i32:
    case AArch64::SABDv4i16:
    case AArch64::SABDv4i32:
    case AArch64::SABDv8i16:
    case AArch64::SABDv8i8:
    case AArch64::SADDLv16i8_v8i16:
    case AArch64::SADDLv2i32_v2i64:
    case AArch64::SADDLv4i16_v4i32:
    case AArch64::SADDLv4i32_v2i64:
    case AArch64::SADDLv8i16_v4i32:
    case AArch64::SADDLv8i8_v8i16:
    case AArch64::SADDWv16i8_v8i16:
    case AArch64::SADDWv2i32_v2i64:
    case AArch64::SADDWv4i16_v4i32:
    case AArch64::SADDWv4i32_v2i64:
    case AArch64::SADDWv8i16_v4i32:
    case AArch64::SADDWv8i8_v8i16:
    case AArch64::SBCSWr:
    case AArch64::SBCSXr:
    case AArch64::SBCWr:
    case AArch64::SBCXr:
    case AArch64::SDIVWr:
    case AArch64::SDIVXr:
    case AArch64::SHADDv16i8:
    case AArch64::SHADDv2i32:
    case AArch64::SHADDv4i16:
    case AArch64::SHADDv4i32:
    case AArch64::SHADDv8i16:
    case AArch64::SHADDv8i8:
    case AArch64::SHSUBv16i8:
    case AArch64::SHSUBv2i32:
    case AArch64::SHSUBv4i16:
    case AArch64::SHSUBv4i32:
    case AArch64::SHSUBv8i16:
    case AArch64::SHSUBv8i8:
    case AArch64::SMAXPv16i8:
    case AArch64::SMAXPv2i32:
    case AArch64::SMAXPv4i16:
    case AArch64::SMAXPv4i32:
    case AArch64::SMAXPv8i16:
    case AArch64::SMAXPv8i8:
    case AArch64::SMAXWrr:
    case AArch64::SMAXXrr:
    case AArch64::SMAXv16i8:
    case AArch64::SMAXv2i32:
    case AArch64::SMAXv4i16:
    case AArch64::SMAXv4i32:
    case AArch64::SMAXv8i16:
    case AArch64::SMAXv8i8:
    case AArch64::SMINPv16i8:
    case AArch64::SMINPv2i32:
    case AArch64::SMINPv4i16:
    case AArch64::SMINPv4i32:
    case AArch64::SMINPv8i16:
    case AArch64::SMINPv8i8:
    case AArch64::SMINWrr:
    case AArch64::SMINXrr:
    case AArch64::SMINv16i8:
    case AArch64::SMINv2i32:
    case AArch64::SMINv4i16:
    case AArch64::SMINv4i32:
    case AArch64::SMINv8i16:
    case AArch64::SMINv8i8:
    case AArch64::SMULLv16i8_v8i16:
    case AArch64::SMULLv2i32_v2i64:
    case AArch64::SMULLv4i16_v4i32:
    case AArch64::SMULLv4i32_v2i64:
    case AArch64::SMULLv8i16_v4i32:
    case AArch64::SMULLv8i8_v8i16:
    case AArch64::SQADDv16i8:
    case AArch64::SQADDv1i16:
    case AArch64::SQADDv1i32:
    case AArch64::SQADDv1i64:
    case AArch64::SQADDv1i8:
    case AArch64::SQADDv2i32:
    case AArch64::SQADDv2i64:
    case AArch64::SQADDv4i16:
    case AArch64::SQADDv4i32:
    case AArch64::SQADDv8i16:
    case AArch64::SQADDv8i8:
    case AArch64::SQDMULHv1i16:
    case AArch64::SQDMULHv1i32:
    case AArch64::SQDMULHv2i32:
    case AArch64::SQDMULHv4i16:
    case AArch64::SQDMULHv4i32:
    case AArch64::SQDMULHv8i16:
    case AArch64::SQDMULLi16:
    case AArch64::SQDMULLi32:
    case AArch64::SQDMULLv2i32_v2i64:
    case AArch64::SQDMULLv4i16_v4i32:
    case AArch64::SQDMULLv4i32_v2i64:
    case AArch64::SQDMULLv8i16_v4i32:
    case AArch64::SQRDMULHv1i16:
    case AArch64::SQRDMULHv1i32:
    case AArch64::SQRDMULHv2i32:
    case AArch64::SQRDMULHv4i16:
    case AArch64::SQRDMULHv4i32:
    case AArch64::SQRDMULHv8i16:
    case AArch64::SQRSHLv16i8:
    case AArch64::SQRSHLv1i16:
    case AArch64::SQRSHLv1i32:
    case AArch64::SQRSHLv1i64:
    case AArch64::SQRSHLv1i8:
    case AArch64::SQRSHLv2i32:
    case AArch64::SQRSHLv2i64:
    case AArch64::SQRSHLv4i16:
    case AArch64::SQRSHLv4i32:
    case AArch64::SQRSHLv8i16:
    case AArch64::SQRSHLv8i8:
    case AArch64::SQSHLv16i8:
    case AArch64::SQSHLv1i16:
    case AArch64::SQSHLv1i32:
    case AArch64::SQSHLv1i64:
    case AArch64::SQSHLv1i8:
    case AArch64::SQSHLv2i32:
    case AArch64::SQSHLv2i64:
    case AArch64::SQSHLv4i16:
    case AArch64::SQSHLv4i32:
    case AArch64::SQSHLv8i16:
    case AArch64::SQSHLv8i8:
    case AArch64::SQSUBv16i8:
    case AArch64::SQSUBv1i16:
    case AArch64::SQSUBv1i32:
    case AArch64::SQSUBv1i64:
    case AArch64::SQSUBv1i8:
    case AArch64::SQSUBv2i32:
    case AArch64::SQSUBv2i64:
    case AArch64::SQSUBv4i16:
    case AArch64::SQSUBv4i32:
    case AArch64::SQSUBv8i16:
    case AArch64::SQSUBv8i8:
    case AArch64::SRHADDv16i8:
    case AArch64::SRHADDv2i32:
    case AArch64::SRHADDv4i16:
    case AArch64::SRHADDv4i32:
    case AArch64::SRHADDv8i16:
    case AArch64::SRHADDv8i8:
    case AArch64::SRSHLv16i8:
    case AArch64::SRSHLv1i64:
    case AArch64::SRSHLv2i32:
    case AArch64::SRSHLv2i64:
    case AArch64::SRSHLv4i16:
    case AArch64::SRSHLv4i32:
    case AArch64::SRSHLv8i16:
    case AArch64::SRSHLv8i8:
    case AArch64::SSHLv16i8:
    case AArch64::SSHLv1i64:
    case AArch64::SSHLv2i32:
    case AArch64::SSHLv2i64:
    case AArch64::SSHLv4i16:
    case AArch64::SSHLv4i32:
    case AArch64::SSHLv8i16:
    case AArch64::SSHLv8i8:
    case AArch64::SSUBLv16i8_v8i16:
    case AArch64::SSUBLv2i32_v2i64:
    case AArch64::SSUBLv4i16_v4i32:
    case AArch64::SSUBLv4i32_v2i64:
    case AArch64::SSUBLv8i16_v4i32:
    case AArch64::SSUBLv8i8_v8i16:
    case AArch64::SSUBWv16i8_v8i16:
    case AArch64::SSUBWv2i32_v2i64:
    case AArch64::SSUBWv4i16_v4i32:
    case AArch64::SSUBWv4i32_v2i64:
    case AArch64::SSUBWv8i16_v4i32:
    case AArch64::SSUBWv8i8_v8i16:
    case AArch64::SUBHNv2i64_v2i32:
    case AArch64::SUBHNv4i32_v4i16:
    case AArch64::SUBHNv8i16_v8i8:
    case AArch64::SUBP:
    case AArch64::SUBPS:
    case AArch64::SUBv16i8:
    case AArch64::SUBv1i64:
    case AArch64::SUBv2i32:
    case AArch64::SUBv2i64:
    case AArch64::SUBv4i16:
    case AArch64::SUBv4i32:
    case AArch64::SUBv8i16:
    case AArch64::SUBv8i8:
    case AArch64::TRN1v16i8:
    case AArch64::TRN1v2i32:
    case AArch64::TRN1v2i64:
    case AArch64::TRN1v4i16:
    case AArch64::TRN1v4i32:
    case AArch64::TRN1v8i16:
    case AArch64::TRN1v8i8:
    case AArch64::TRN2v16i8:
    case AArch64::TRN2v2i32:
    case AArch64::TRN2v2i64:
    case AArch64::TRN2v4i16:
    case AArch64::TRN2v4i32:
    case AArch64::TRN2v8i16:
    case AArch64::TRN2v8i8:
    case AArch64::UABDLv16i8_v8i16:
    case AArch64::UABDLv2i32_v2i64:
    case AArch64::UABDLv4i16_v4i32:
    case AArch64::UABDLv4i32_v2i64:
    case AArch64::UABDLv8i16_v4i32:
    case AArch64::UABDLv8i8_v8i16:
    case AArch64::UABDv16i8:
    case AArch64::UABDv2i32:
    case AArch64::UABDv4i16:
    case AArch64::UABDv4i32:
    case AArch64::UABDv8i16:
    case AArch64::UABDv8i8:
    case AArch64::UADDLv16i8_v8i16:
    case AArch64::UADDLv2i32_v2i64:
    case AArch64::UADDLv4i16_v4i32:
    case AArch64::UADDLv4i32_v2i64:
    case AArch64::UADDLv8i16_v4i32:
    case AArch64::UADDLv8i8_v8i16:
    case AArch64::UADDWv16i8_v8i16:
    case AArch64::UADDWv2i32_v2i64:
    case AArch64::UADDWv4i16_v4i32:
    case AArch64::UADDWv4i32_v2i64:
    case AArch64::UADDWv8i16_v4i32:
    case AArch64::UADDWv8i8_v8i16:
    case AArch64::UDIVWr:
    case AArch64::UDIVXr:
    case AArch64::UHADDv16i8:
    case AArch64::UHADDv2i32:
    case AArch64::UHADDv4i16:
    case AArch64::UHADDv4i32:
    case AArch64::UHADDv8i16:
    case AArch64::UHADDv8i8:
    case AArch64::UHSUBv16i8:
    case AArch64::UHSUBv2i32:
    case AArch64::UHSUBv4i16:
    case AArch64::UHSUBv4i32:
    case AArch64::UHSUBv8i16:
    case AArch64::UHSUBv8i8:
    case AArch64::UMAXPv16i8:
    case AArch64::UMAXPv2i32:
    case AArch64::UMAXPv4i16:
    case AArch64::UMAXPv4i32:
    case AArch64::UMAXPv8i16:
    case AArch64::UMAXPv8i8:
    case AArch64::UMAXWrr:
    case AArch64::UMAXXrr:
    case AArch64::UMAXv16i8:
    case AArch64::UMAXv2i32:
    case AArch64::UMAXv4i16:
    case AArch64::UMAXv4i32:
    case AArch64::UMAXv8i16:
    case AArch64::UMAXv8i8:
    case AArch64::UMINPv16i8:
    case AArch64::UMINPv2i32:
    case AArch64::UMINPv4i16:
    case AArch64::UMINPv4i32:
    case AArch64::UMINPv8i16:
    case AArch64::UMINPv8i8:
    case AArch64::UMINWrr:
    case AArch64::UMINXrr:
    case AArch64::UMINv16i8:
    case AArch64::UMINv2i32:
    case AArch64::UMINv4i16:
    case AArch64::UMINv4i32:
    case AArch64::UMINv8i16:
    case AArch64::UMINv8i8:
    case AArch64::UMULLv16i8_v8i16:
    case AArch64::UMULLv2i32_v2i64:
    case AArch64::UMULLv4i16_v4i32:
    case AArch64::UMULLv4i32_v2i64:
    case AArch64::UMULLv8i16_v4i32:
    case AArch64::UMULLv8i8_v8i16:
    case AArch64::UQADDv16i8:
    case AArch64::UQADDv1i16:
    case AArch64::UQADDv1i32:
    case AArch64::UQADDv1i64:
    case AArch64::UQADDv1i8:
    case AArch64::UQADDv2i32:
    case AArch64::UQADDv2i64:
    case AArch64::UQADDv4i16:
    case AArch64::UQADDv4i32:
    case AArch64::UQADDv8i16:
    case AArch64::UQADDv8i8:
    case AArch64::UQRSHLv16i8:
    case AArch64::UQRSHLv1i16:
    case AArch64::UQRSHLv1i32:
    case AArch64::UQRSHLv1i64:
    case AArch64::UQRSHLv1i8:
    case AArch64::UQRSHLv2i32:
    case AArch64::UQRSHLv2i64:
    case AArch64::UQRSHLv4i16:
    case AArch64::UQRSHLv4i32:
    case AArch64::UQRSHLv8i16:
    case AArch64::UQRSHLv8i8:
    case AArch64::UQSHLv16i8:
    case AArch64::UQSHLv1i16:
    case AArch64::UQSHLv1i32:
    case AArch64::UQSHLv1i64:
    case AArch64::UQSHLv1i8:
    case AArch64::UQSHLv2i32:
    case AArch64::UQSHLv2i64:
    case AArch64::UQSHLv4i16:
    case AArch64::UQSHLv4i32:
    case AArch64::UQSHLv8i16:
    case AArch64::UQSHLv8i8:
    case AArch64::UQSUBv16i8:
    case AArch64::UQSUBv1i16:
    case AArch64::UQSUBv1i32:
    case AArch64::UQSUBv1i64:
    case AArch64::UQSUBv1i8:
    case AArch64::UQSUBv2i32:
    case AArch64::UQSUBv2i64:
    case AArch64::UQSUBv4i16:
    case AArch64::UQSUBv4i32:
    case AArch64::UQSUBv8i16:
    case AArch64::UQSUBv8i8:
    case AArch64::URHADDv16i8:
    case AArch64::URHADDv2i32:
    case AArch64::URHADDv4i16:
    case AArch64::URHADDv4i32:
    case AArch64::URHADDv8i16:
    case AArch64::URHADDv8i8:
    case AArch64::URSHLv16i8:
    case AArch64::URSHLv1i64:
    case AArch64::URSHLv2i32:
    case AArch64::URSHLv2i64:
    case AArch64::URSHLv4i16:
    case AArch64::URSHLv4i32:
    case AArch64::URSHLv8i16:
    case AArch64::URSHLv8i8:
    case AArch64::USHLv16i8:
    case AArch64::USHLv1i64:
    case AArch64::USHLv2i32:
    case AArch64::USHLv2i64:
    case AArch64::USHLv4i16:
    case AArch64::USHLv4i32:
    case AArch64::USHLv8i16:
    case AArch64::USHLv8i8:
    case AArch64::USUBLv16i8_v8i16:
    case AArch64::USUBLv2i32_v2i64:
    case AArch64::USUBLv4i16_v4i32:
    case AArch64::USUBLv4i32_v2i64:
    case AArch64::USUBLv8i16_v4i32:
    case AArch64::USUBLv8i8_v8i16:
    case AArch64::USUBWv16i8_v8i16:
    case AArch64::USUBWv2i32_v2i64:
    case AArch64::USUBWv4i16_v4i32:
    case AArch64::USUBWv4i32_v2i64:
    case AArch64::USUBWv8i16_v4i32:
    case AArch64::USUBWv8i8_v8i16:
    case AArch64::UZP1v16i8:
    case AArch64::UZP1v2i32:
    case AArch64::UZP1v2i64:
    case AArch64::UZP1v4i16:
    case AArch64::UZP1v4i32:
    case AArch64::UZP1v8i16:
    case AArch64::UZP1v8i8:
    case AArch64::UZP2v16i8:
    case AArch64::UZP2v2i32:
    case AArch64::UZP2v2i64:
    case AArch64::UZP2v4i16:
    case AArch64::UZP2v4i32:
    case AArch64::UZP2v8i16:
    case AArch64::UZP2v8i8:
    case AArch64::ZIP1v16i8:
    case AArch64::ZIP1v2i32:
    case AArch64::ZIP1v2i64:
    case AArch64::ZIP1v4i16:
    case AArch64::ZIP1v4i32:
    case AArch64::ZIP1v8i16:
    case AArch64::ZIP1v8i8:
    case AArch64::ZIP2v16i8:
    case AArch64::ZIP2v2i32:
    case AArch64::ZIP2v2i64:
    case AArch64::ZIP2v4i16:
    case AArch64::ZIP2v4i32:
    case AArch64::ZIP2v8i16:
    case AArch64::ZIP2v8i8: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::FMADDDrrr:
    case AArch64::FMADDHrrr:
    case AArch64::FMADDSrrr:
    case AArch64::FMSUBDrrr:
    case AArch64::FMSUBHrrr:
    case AArch64::FMSUBSrrr:
    case AArch64::FNMADDDrrr:
    case AArch64::FNMADDHrrr:
    case AArch64::FNMADDSrrr:
    case AArch64::FNMSUBDrrr:
    case AArch64::FNMSUBHrrr:
    case AArch64::FNMSUBSrrr:
    case AArch64::MADDPT:
    case AArch64::MADDWrrr:
    case AArch64::MADDXrrr:
    case AArch64::MSUBPT:
    case AArch64::MSUBWrrr:
    case AArch64::MSUBXrrr:
    case AArch64::SMADDLrrr:
    case AArch64::SMSUBLrrr:
    case AArch64::UMADDLrrr:
    case AArch64::UMSUBLrrr: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Ra
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      break;
    }
    case AArch64::CSELWr:
    case AArch64::CSELXr:
    case AArch64::CSINCWr:
    case AArch64::CSINCXr:
    case AArch64::CSINVWr:
    case AArch64::CSINVXr:
    case AArch64::CSNEGWr:
    case AArch64::CSNEGXr:
    case AArch64::FCSELDrrr:
    case AArch64::FCSELHrrr:
    case AArch64::FCSELSrrr: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: cond
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 12;
      break;
    }
    case AArch64::ADDSXrx64:
    case AArch64::ADDXrx64:
    case AArch64::SUBSXrx64:
    case AArch64::SUBXrx64: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: ext
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x20) << 10;
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::ADDSWrx:
    case AArch64::ADDSXrx:
    case AArch64::ADDWrx:
    case AArch64::ADDXrx:
    case AArch64::SUBSWrx:
    case AArch64::SUBSXrx:
    case AArch64::SUBWrx:
    case AArch64::SUBXrx: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: extend
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      break;
    }
    case AArch64::FMULXv1i64_indexed:
    case AArch64::FMULXv2i64_indexed:
    case AArch64::FMULv1i64_indexed:
    case AArch64::FMULv2i64_indexed: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 11;
      break;
    }
    case AArch64::LUT4_B: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 14;
      break;
    }
    case AArch64::FMULXv1i32_indexed:
    case AArch64::FMULXv2i32_indexed:
    case AArch64::FMULXv4i32_indexed:
    case AArch64::FMULv1i32_indexed:
    case AArch64::FMULv2i32_indexed:
    case AArch64::FMULv4i32_indexed:
    case AArch64::MULv2i32_indexed:
    case AArch64::MULv4i32_indexed:
    case AArch64::SMULLv2i32_indexed:
    case AArch64::SMULLv4i32_indexed:
    case AArch64::SQDMULHv1i32_indexed:
    case AArch64::SQDMULHv2i32_indexed:
    case AArch64::SQDMULHv4i32_indexed:
    case AArch64::SQDMULLv1i64_indexed:
    case AArch64::SQDMULLv2i32_indexed:
    case AArch64::SQDMULLv4i32_indexed:
    case AArch64::SQRDMULHv1i32_indexed:
    case AArch64::SQRDMULHv2i32_indexed:
    case AArch64::SQRDMULHv4i32_indexed:
    case AArch64::UMULLv2i32_indexed:
    case AArch64::UMULLv4i32_indexed: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 21;
      Value |= (op & 0x2) << 10;
      break;
    }
    case AArch64::LUT2_B:
    case AArch64::LUT4_H: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 13;
      break;
    }
    case AArch64::LUT2_H: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 12;
      break;
    }
    case AArch64::EXTRWrri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      break;
    }
    case AArch64::EXTRXrri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      break;
    }
    case AArch64::EXTv8i8: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 11;
      break;
    }
    case AArch64::EXTv16i8: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 11;
      break;
    }
    case AArch64::FCADDv2f32:
    case AArch64::FCADDv2f64:
    case AArch64::FCADDv4f16:
    case AArch64::FCADDv4f32:
    case AArch64::FCADDv8f16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 12;
      break;
    }
    case AArch64::ADDSWrs:
    case AArch64::ADDSXrs:
    case AArch64::ADDWrs:
    case AArch64::ADDXrs:
    case AArch64::ANDSWrs:
    case AArch64::ANDSXrs:
    case AArch64::ANDWrs:
    case AArch64::ANDXrs:
    case AArch64::BICSWrs:
    case AArch64::BICSXrs:
    case AArch64::BICWrs:
    case AArch64::BICXrs:
    case AArch64::EONWrs:
    case AArch64::EONXrs:
    case AArch64::EORWrs:
    case AArch64::EORXrs:
    case AArch64::ORNWrs:
    case AArch64::ORNXrs:
    case AArch64::ORRWrs:
    case AArch64::ORRXrs:
    case AArch64::SUBSWrs:
    case AArch64::SUBSXrs:
    case AArch64::SUBWrs:
    case AArch64::SUBXrs: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: shift
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xc0) << 16;
      Value |= (op & 0x3f) << 10;
      break;
    }
    case AArch64::ADDPT_shift:
    case AArch64::SUBPT_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: shift_imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::SMULHrr:
    case AArch64::UMULHrr: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      Value = fixMulHigh(MI, Value, STI);
      break;
    }
    case AArch64::FMULXv1i16_indexed:
    case AArch64::FMULXv4i16_indexed:
    case AArch64::FMULXv8i16_indexed:
    case AArch64::FMULv1i16_indexed:
    case AArch64::FMULv4i16_indexed:
    case AArch64::FMULv8i16_indexed:
    case AArch64::MULv4i16_indexed:
    case AArch64::MULv8i16_indexed:
    case AArch64::SMULLv4i16_indexed:
    case AArch64::SMULLv8i16_indexed:
    case AArch64::SQDMULHv1i16_indexed:
    case AArch64::SQDMULHv4i16_indexed:
    case AArch64::SQDMULHv8i16_indexed:
    case AArch64::SQDMULLv1i32_indexed:
    case AArch64::SQDMULLv4i16_indexed:
    case AArch64::SQDMULLv8i16_indexed:
    case AArch64::SQRDMULHv1i16_indexed:
    case AArch64::SQRDMULHv4i16_indexed:
    case AArch64::SQRDMULHv8i16_indexed:
    case AArch64::UMULLv4i16_indexed:
    case AArch64::UMULLv8i16_indexed: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 20;
      Value |= (op & 0x4) << 9;
      break;
    }
    case AArch64::DUPv2i64lane:
    case AArch64::UMOVvi64: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 20;
      break;
    }
    case AArch64::DUPv2i32lane:
    case AArch64::DUPv4i32lane:
    case AArch64::SMOVvi32to64:
    case AArch64::UMOVvi32: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::DUPv4i16lane:
    case AArch64::DUPv8i16lane:
    case AArch64::SMOVvi16to32:
    case AArch64::SMOVvi16to64:
    case AArch64::UMOVvi16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 18;
      break;
    }
    case AArch64::DUPv16i8lane:
    case AArch64::DUPv8i8lane:
    case AArch64::SMOVvi8to32:
    case AArch64::SMOVvi8to64:
    case AArch64::UMOVvi8: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 17;
      break;
    }
    case AArch64::ADDSWri:
    case AArch64::ADDSXri:
    case AArch64::ADDWri:
    case AArch64::ADDXri:
    case AArch64::SUBSWri:
    case AArch64::SUBSXri:
    case AArch64::SUBWri:
    case AArch64::SUBXri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getAddSubImmOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x3fff) << 10;
      break;
    }
    case AArch64::ANDSXri:
    case AArch64::ANDXri:
    case AArch64::EORXri:
    case AArch64::ORRXri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1fff) << 10;
      break;
    }
    case AArch64::SMAXWri:
    case AArch64::SMAXXri:
    case AArch64::SMINWri:
    case AArch64::SMINXri:
    case AArch64::UMAXWri:
    case AArch64::UMAXXri:
    case AArch64::UMINWri:
    case AArch64::UMINXri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff) << 10;
      break;
    }
    case AArch64::ANDSWri:
    case AArch64::ANDWri:
    case AArch64::EORWri:
    case AArch64::ORRWri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xfff) << 10;
      break;
    }
    case AArch64::SHLv4i16_shift:
    case AArch64::SHLv8i16_shift:
    case AArch64::SQSHLUh:
    case AArch64::SQSHLUv4i16_shift:
    case AArch64::SQSHLUv8i16_shift:
    case AArch64::SQSHLh:
    case AArch64::SQSHLv4i16_shift:
    case AArch64::SQSHLv8i16_shift:
    case AArch64::SSHLLv4i16_shift:
    case AArch64::SSHLLv8i16_shift:
    case AArch64::UQSHLh:
    case AArch64::UQSHLv4i16_shift:
    case AArch64::UQSHLv8i16_shift:
    case AArch64::USHLLv4i16_shift:
    case AArch64::USHLLv8i16_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL16OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::SHLv2i32_shift:
    case AArch64::SHLv4i32_shift:
    case AArch64::SQSHLUs:
    case AArch64::SQSHLUv2i32_shift:
    case AArch64::SQSHLUv4i32_shift:
    case AArch64::SQSHLs:
    case AArch64::SQSHLv2i32_shift:
    case AArch64::SQSHLv4i32_shift:
    case AArch64::SSHLLv2i32_shift:
    case AArch64::SSHLLv4i32_shift:
    case AArch64::UQSHLs:
    case AArch64::UQSHLv2i32_shift:
    case AArch64::UQSHLv4i32_shift:
    case AArch64::USHLLv2i32_shift:
    case AArch64::USHLLv4i32_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL32OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SHLd:
    case AArch64::SHLv2i64_shift:
    case AArch64::SQSHLUd:
    case AArch64::SQSHLUv2i64_shift:
    case AArch64::SQSHLd:
    case AArch64::SQSHLv2i64_shift:
    case AArch64::UQSHLd:
    case AArch64::UQSHLv2i64_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL64OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x3f) << 16;
      break;
    }
    case AArch64::SHLv16i8_shift:
    case AArch64::SHLv8i8_shift:
    case AArch64::SQSHLUb:
    case AArch64::SQSHLUv16i8_shift:
    case AArch64::SQSHLUv8i8_shift:
    case AArch64::SQSHLb:
    case AArch64::SQSHLv16i8_shift:
    case AArch64::SQSHLv8i8_shift:
    case AArch64::SSHLLv16i8_shift:
    case AArch64::SSHLLv8i8_shift:
    case AArch64::UQSHLb:
    case AArch64::UQSHLv16i8_shift:
    case AArch64::UQSHLv8i8_shift:
    case AArch64::USHLLv16i8_shift:
    case AArch64::USHLLv8i8_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL8OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::RSHRNv8i8_shift:
    case AArch64::SHRNv8i8_shift:
    case AArch64::SQRSHRNv8i8_shift:
    case AArch64::SQRSHRUNv8i8_shift:
    case AArch64::SQSHRNv8i8_shift:
    case AArch64::SQSHRUNv8i8_shift:
    case AArch64::UQRSHRNv8i8_shift:
    case AArch64::UQSHRNv8i8_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::FCVTZSh:
    case AArch64::FCVTZSv4i16_shift:
    case AArch64::FCVTZSv8i16_shift:
    case AArch64::FCVTZUh:
    case AArch64::FCVTZUv4i16_shift:
    case AArch64::FCVTZUv8i16_shift:
    case AArch64::SCVTFh:
    case AArch64::SCVTFv4i16_shift:
    case AArch64::SCVTFv8i16_shift:
    case AArch64::SQRSHRNh:
    case AArch64::SQRSHRUNh:
    case AArch64::SQSHRNh:
    case AArch64::SQSHRUNh:
    case AArch64::SRSHRv4i16_shift:
    case AArch64::SRSHRv8i16_shift:
    case AArch64::SSHRv4i16_shift:
    case AArch64::SSHRv8i16_shift:
    case AArch64::UCVTFh:
    case AArch64::UCVTFv4i16_shift:
    case AArch64::UCVTFv8i16_shift:
    case AArch64::UQRSHRNh:
    case AArch64::UQSHRNh:
    case AArch64::URSHRv4i16_shift:
    case AArch64::URSHRv8i16_shift:
    case AArch64::USHRv4i16_shift:
    case AArch64::USHRv8i16_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::FCVTZSs:
    case AArch64::FCVTZSv2i32_shift:
    case AArch64::FCVTZSv4i32_shift:
    case AArch64::FCVTZUs:
    case AArch64::FCVTZUv2i32_shift:
    case AArch64::FCVTZUv4i32_shift:
    case AArch64::SCVTFs:
    case AArch64::SCVTFv2i32_shift:
    case AArch64::SCVTFv4i32_shift:
    case AArch64::SQRSHRNs:
    case AArch64::SQRSHRUNs:
    case AArch64::SQSHRNs:
    case AArch64::SQSHRUNs:
    case AArch64::SRSHRv2i32_shift:
    case AArch64::SRSHRv4i32_shift:
    case AArch64::SSHRv2i32_shift:
    case AArch64::SSHRv4i32_shift:
    case AArch64::UCVTFs:
    case AArch64::UCVTFv2i32_shift:
    case AArch64::UCVTFv4i32_shift:
    case AArch64::UQRSHRNs:
    case AArch64::UQSHRNs:
    case AArch64::URSHRv2i32_shift:
    case AArch64::URSHRv4i32_shift:
    case AArch64::USHRv2i32_shift:
    case AArch64::USHRv4i32_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR32OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::RSHRNv4i16_shift:
    case AArch64::SHRNv4i16_shift:
    case AArch64::SQRSHRNv4i16_shift:
    case AArch64::SQRSHRUNv4i16_shift:
    case AArch64::SQSHRNv4i16_shift:
    case AArch64::SQSHRUNv4i16_shift:
    case AArch64::UQRSHRNv4i16_shift:
    case AArch64::UQSHRNv4i16_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR32OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::RSHRNv2i32_shift:
    case AArch64::SHRNv2i32_shift:
    case AArch64::SQRSHRNv2i32_shift:
    case AArch64::SQRSHRUNv2i32_shift:
    case AArch64::SQSHRNv2i32_shift:
    case AArch64::SQSHRUNv2i32_shift:
    case AArch64::UQRSHRNv2i32_shift:
    case AArch64::UQSHRNv2i32_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR64OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::FCVTZSd:
    case AArch64::FCVTZSv2i64_shift:
    case AArch64::FCVTZUd:
    case AArch64::FCVTZUv2i64_shift:
    case AArch64::SCVTFd:
    case AArch64::SCVTFv2i64_shift:
    case AArch64::SRSHRd:
    case AArch64::SRSHRv2i64_shift:
    case AArch64::SSHRd:
    case AArch64::SSHRv2i64_shift:
    case AArch64::UCVTFd:
    case AArch64::UCVTFv2i64_shift:
    case AArch64::URSHRd:
    case AArch64::URSHRv2i64_shift:
    case AArch64::USHRd:
    case AArch64::USHRv2i64_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR64OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x3f) << 16;
      break;
    }
    case AArch64::SQRSHRNb:
    case AArch64::SQRSHRUNb:
    case AArch64::SQSHRNb:
    case AArch64::SQSHRUNb:
    case AArch64::SRSHRv16i8_shift:
    case AArch64::SRSHRv8i8_shift:
    case AArch64::SSHRv16i8_shift:
    case AArch64::SSHRv8i8_shift:
    case AArch64::UQRSHRNb:
    case AArch64::UQSHRNb:
    case AArch64::URSHRv16i8_shift:
    case AArch64::URSHRv8i8_shift:
    case AArch64::USHRv16i8_shift:
    case AArch64::USHRv8i8_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR8OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::ADDG:
    case AArch64::SUBG: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 10;
      break;
    }
    case AArch64::SBFMWri:
    case AArch64::UBFMWri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: immr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imms
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      break;
    }
    case AArch64::SBFMXri:
    case AArch64::UBFMXri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: immr
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      // op: imms
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      break;
    }
    case AArch64::FCVTZSSWDri:
    case AArch64::FCVTZSSWHri:
    case AArch64::FCVTZSSWSri:
    case AArch64::FCVTZUSWDri:
    case AArch64::FCVTZUSWHri:
    case AArch64::FCVTZUSWSri:
    case AArch64::SCVTFSWDri:
    case AArch64::SCVTFSWHri:
    case AArch64::SCVTFSWSri:
    case AArch64::UCVTFSWDri:
    case AArch64::UCVTFSWHri:
    case AArch64::UCVTFSWSri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: scale
      op = getFixedPointScaleOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1f) << 10;
      break;
    }
    case AArch64::FCVTZSSXDri:
    case AArch64::FCVTZSSXHri:
    case AArch64::FCVTZSSXSri:
    case AArch64::FCVTZUSXDri:
    case AArch64::FCVTZUSXHri:
    case AArch64::FCVTZUSXSri:
    case AArch64::SCVTFSXDri:
    case AArch64::SCVTFSXHri:
    case AArch64::SCVTFSXSri:
    case AArch64::UCVTFSXDri:
    case AArch64::UCVTFSXHri:
    case AArch64::UCVTFSXSri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: scale
      op = getFixedPointScaleOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x3f) << 10;
      break;
    }
    case AArch64::BFMWri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: immr
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imms
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      break;
    }
    case AArch64::BFMXri: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: immr
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      // op: imms
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      break;
    }
    case AArch64::FMOVDi:
    case AArch64::FMOVHi:
    case AArch64::FMOVSi: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xff) << 13;
      break;
    }
    case AArch64::MOVNWi:
    case AArch64::MOVNXi: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getMoveWideImmOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff) << 5;
      // op: shift
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x30) << 17;
      break;
    }
    case AArch64::MOVZWi:
    case AArch64::MOVZXi: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getMoveWideImmOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0xffff) << 5;
      // op: shift
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x30) << 17;
      Value = fixMOVZ(MI, Value, STI);
      break;
    }
    case AArch64::MOVKWi:
    case AArch64::MOVKXi: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getMoveWideImmOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xffff) << 5;
      // op: shift
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x30) << 17;
      break;
    }
    case AArch64::CNTB_XPiI:
    case AArch64::CNTD_XPiI:
    case AArch64::CNTH_XPiI:
    case AArch64::CNTW_XPiI: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm4
      op = getSVEIncDecImm(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: pattern
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::RDSVLI_XI:
    case AArch64::RDVLI_XI: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3f) << 5;
      break;
    }
    case AArch64::FMOVv2f32_ns:
    case AArch64::FMOVv2f64_ns:
    case AArch64::FMOVv4f16_ns:
    case AArch64::FMOVv4f32_ns:
    case AArch64::FMOVv8f16_ns:
    case AArch64::MOVID:
    case AArch64::MOVIv16b_ns:
    case AArch64::MOVIv2d_ns:
    case AArch64::MOVIv8b_ns: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xe0) << 11;
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::MOVIv2s_msl:
    case AArch64::MOVIv4s_msl:
    case AArch64::MVNIv2s_msl:
    case AArch64::MVNIv4s_msl: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xe0) << 11;
      Value |= (op & 0x1f) << 5;
      // op: shift
      op = getMoveVecShifterOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1) << 12;
      break;
    }
    case AArch64::MOVIv4i16:
    case AArch64::MOVIv8i16:
    case AArch64::MVNIv4i16:
    case AArch64::MVNIv8i16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xe0) << 11;
      Value |= (op & 0x1f) << 5;
      // op: shift
      op = getVecShifterOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1) << 13;
      break;
    }
    case AArch64::MOVIv2i32:
    case AArch64::MOVIv4i32:
    case AArch64::MVNIv2i32:
    case AArch64::MVNIv4i32: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xe0) << 11;
      Value |= (op & 0x1f) << 5;
      // op: shift
      op = getVecShifterOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      break;
    }
    case AArch64::AUTDZA:
    case AArch64::AUTDZB:
    case AArch64::AUTIZA:
    case AArch64::AUTIZB:
    case AArch64::PACDZA:
    case AArch64::PACDZB:
    case AArch64::PACIZA:
    case AArch64::PACIZB: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::AESDrr:
    case AArch64::AESErr:
    case AArch64::AUTDA:
    case AArch64::AUTDB:
    case AArch64::AUTIA:
    case AArch64::AUTIB:
    case AArch64::BFCVTN2:
    case AArch64::FCVTNv4i32:
    case AArch64::FCVTNv8i16:
    case AArch64::FCVTXNv4f32:
    case AArch64::PACDA:
    case AArch64::PACDB:
    case AArch64::PACIA:
    case AArch64::PACIB:
    case AArch64::SADALPv16i8_v8i16:
    case AArch64::SADALPv2i32_v1i64:
    case AArch64::SADALPv4i16_v2i32:
    case AArch64::SADALPv4i32_v2i64:
    case AArch64::SADALPv8i16_v4i32:
    case AArch64::SADALPv8i8_v4i16:
    case AArch64::SHA1SU1rr:
    case AArch64::SHA256SU0rr:
    case AArch64::SQXTNv16i8:
    case AArch64::SQXTNv4i32:
    case AArch64::SQXTNv8i16:
    case AArch64::SQXTUNv16i8:
    case AArch64::SQXTUNv4i32:
    case AArch64::SQXTUNv8i16:
    case AArch64::SUQADDv16i8:
    case AArch64::SUQADDv1i16:
    case AArch64::SUQADDv1i32:
    case AArch64::SUQADDv1i64:
    case AArch64::SUQADDv1i8:
    case AArch64::SUQADDv2i32:
    case AArch64::SUQADDv2i64:
    case AArch64::SUQADDv4i16:
    case AArch64::SUQADDv4i32:
    case AArch64::SUQADDv8i16:
    case AArch64::SUQADDv8i8:
    case AArch64::UADALPv16i8_v8i16:
    case AArch64::UADALPv2i32_v1i64:
    case AArch64::UADALPv4i16_v2i32:
    case AArch64::UADALPv4i32_v2i64:
    case AArch64::UADALPv8i16_v4i32:
    case AArch64::UADALPv8i8_v4i16:
    case AArch64::UQXTNv16i8:
    case AArch64::UQXTNv4i32:
    case AArch64::UQXTNv8i16:
    case AArch64::USQADDv16i8:
    case AArch64::USQADDv1i16:
    case AArch64::USQADDv1i32:
    case AArch64::USQADDv1i64:
    case AArch64::USQADDv1i8:
    case AArch64::USQADDv2i32:
    case AArch64::USQADDv2i64:
    case AArch64::USQADDv4i16:
    case AArch64::USQADDv4i32:
    case AArch64::USQADDv8i16:
    case AArch64::USQADDv8i8:
    case AArch64::XTNv16i8:
    case AArch64::XTNv4i32:
    case AArch64::XTNv8i16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::ADDHNv2i64_v4i32:
    case AArch64::ADDHNv4i32_v8i16:
    case AArch64::ADDHNv8i16_v16i8:
    case AArch64::BFDOTv4bf16:
    case AArch64::BFDOTv8bf16:
    case AArch64::BFMLALB:
    case AArch64::BFMLALT:
    case AArch64::BFMMLA:
    case AArch64::BIFv16i8:
    case AArch64::BIFv8i8:
    case AArch64::BITv16i8:
    case AArch64::BITv8i8:
    case AArch64::BSLv16i8:
    case AArch64::BSLv8i8:
    case AArch64::FCVTN_F322v16f8:
    case AArch64::FDOTv2f32:
    case AArch64::FDOTv4f16:
    case AArch64::FDOTv4f16_v2f32:
    case AArch64::FDOTv4f32:
    case AArch64::FDOTv8f16:
    case AArch64::FDOTv8f16_v4f32:
    case AArch64::FMLAL2v4f16:
    case AArch64::FMLAL2v8f16:
    case AArch64::FMLALBv16i8_v8f16:
    case AArch64::FMLALLBBv4f32:
    case AArch64::FMLALLBTv4f32:
    case AArch64::FMLALLTBv4f32:
    case AArch64::FMLALLTTv4f32:
    case AArch64::FMLALTv16i8_v8f16:
    case AArch64::FMLALv4f16:
    case AArch64::FMLALv8f16:
    case AArch64::FMLAv2f32:
    case AArch64::FMLAv2f64:
    case AArch64::FMLAv4f16:
    case AArch64::FMLAv4f32:
    case AArch64::FMLAv8f16:
    case AArch64::FMLSL2v4f16:
    case AArch64::FMLSL2v8f16:
    case AArch64::FMLSLv4f16:
    case AArch64::FMLSLv8f16:
    case AArch64::FMLSv2f32:
    case AArch64::FMLSv2f64:
    case AArch64::FMLSv4f16:
    case AArch64::FMLSv4f32:
    case AArch64::FMLSv8f16:
    case AArch64::FMMLAv4f32:
    case AArch64::FMMLAv8f16:
    case AArch64::FMMLAv8f16_v4f32:
    case AArch64::FMMLAv8f16_v8f16:
    case AArch64::MLAv16i8:
    case AArch64::MLAv2i32:
    case AArch64::MLAv4i16:
    case AArch64::MLAv4i32:
    case AArch64::MLAv8i16:
    case AArch64::MLAv8i8:
    case AArch64::MLSv16i8:
    case AArch64::MLSv2i32:
    case AArch64::MLSv4i16:
    case AArch64::MLSv4i32:
    case AArch64::MLSv8i16:
    case AArch64::MLSv8i8:
    case AArch64::RADDHNv2i64_v4i32:
    case AArch64::RADDHNv4i32_v8i16:
    case AArch64::RADDHNv8i16_v16i8:
    case AArch64::RSUBHNv2i64_v4i32:
    case AArch64::RSUBHNv4i32_v8i16:
    case AArch64::RSUBHNv8i16_v16i8:
    case AArch64::SABALv16i8_v8i16:
    case AArch64::SABALv2i32_v2i64:
    case AArch64::SABALv4i16_v4i32:
    case AArch64::SABALv4i32_v2i64:
    case AArch64::SABALv8i16_v4i32:
    case AArch64::SABALv8i8_v8i16:
    case AArch64::SABAv16i8:
    case AArch64::SABAv2i32:
    case AArch64::SABAv4i16:
    case AArch64::SABAv4i32:
    case AArch64::SABAv8i16:
    case AArch64::SABAv8i8:
    case AArch64::SDOTv16i8:
    case AArch64::SDOTv8i8:
    case AArch64::SHA1Crrr:
    case AArch64::SHA1Mrrr:
    case AArch64::SHA1Prrr:
    case AArch64::SHA1SU0rrr:
    case AArch64::SHA256H2rrr:
    case AArch64::SHA256Hrrr:
    case AArch64::SHA256SU1rrr:
    case AArch64::SMLALv16i8_v8i16:
    case AArch64::SMLALv2i32_v2i64:
    case AArch64::SMLALv4i16_v4i32:
    case AArch64::SMLALv4i32_v2i64:
    case AArch64::SMLALv8i16_v4i32:
    case AArch64::SMLALv8i8_v8i16:
    case AArch64::SMLSLv16i8_v8i16:
    case AArch64::SMLSLv2i32_v2i64:
    case AArch64::SMLSLv4i16_v4i32:
    case AArch64::SMLSLv4i32_v2i64:
    case AArch64::SMLSLv8i16_v4i32:
    case AArch64::SMLSLv8i8_v8i16:
    case AArch64::SMMLA:
    case AArch64::SQDMLALi16:
    case AArch64::SQDMLALi32:
    case AArch64::SQDMLALv2i32_v2i64:
    case AArch64::SQDMLALv4i16_v4i32:
    case AArch64::SQDMLALv4i32_v2i64:
    case AArch64::SQDMLALv8i16_v4i32:
    case AArch64::SQDMLSLi16:
    case AArch64::SQDMLSLi32:
    case AArch64::SQDMLSLv2i32_v2i64:
    case AArch64::SQDMLSLv4i16_v4i32:
    case AArch64::SQDMLSLv4i32_v2i64:
    case AArch64::SQDMLSLv8i16_v4i32:
    case AArch64::SQRDMLAHv1i16:
    case AArch64::SQRDMLAHv1i32:
    case AArch64::SQRDMLAHv2i32:
    case AArch64::SQRDMLAHv4i16:
    case AArch64::SQRDMLAHv4i32:
    case AArch64::SQRDMLAHv8i16:
    case AArch64::SQRDMLSHv1i16:
    case AArch64::SQRDMLSHv1i32:
    case AArch64::SQRDMLSHv2i32:
    case AArch64::SQRDMLSHv4i16:
    case AArch64::SQRDMLSHv4i32:
    case AArch64::SQRDMLSHv8i16:
    case AArch64::SUBHNv2i64_v4i32:
    case AArch64::SUBHNv4i32_v8i16:
    case AArch64::SUBHNv8i16_v16i8:
    case AArch64::UABALv16i8_v8i16:
    case AArch64::UABALv2i32_v2i64:
    case AArch64::UABALv4i16_v4i32:
    case AArch64::UABALv4i32_v2i64:
    case AArch64::UABALv8i16_v4i32:
    case AArch64::UABALv8i8_v8i16:
    case AArch64::UABAv16i8:
    case AArch64::UABAv2i32:
    case AArch64::UABAv4i16:
    case AArch64::UABAv4i32:
    case AArch64::UABAv8i16:
    case AArch64::UABAv8i8:
    case AArch64::UDOTv16i8:
    case AArch64::UDOTv8i8:
    case AArch64::UMLALv16i8_v8i16:
    case AArch64::UMLALv2i32_v2i64:
    case AArch64::UMLALv4i16_v4i32:
    case AArch64::UMLALv4i32_v2i64:
    case AArch64::UMLALv8i16_v4i32:
    case AArch64::UMLALv8i8_v8i16:
    case AArch64::UMLSLv16i8_v8i16:
    case AArch64::UMLSLv2i32_v2i64:
    case AArch64::UMLSLv4i16_v4i32:
    case AArch64::UMLSLv4i32_v2i64:
    case AArch64::UMLSLv8i16_v4i32:
    case AArch64::UMLSLv8i8_v8i16:
    case AArch64::UMMLA:
    case AArch64::USDOTv16i8:
    case AArch64::USDOTv8i8:
    case AArch64::USMMLA: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::FMLAv1i64_indexed:
    case AArch64::FMLAv2i64_indexed:
    case AArch64::FMLSv1i64_indexed:
    case AArch64::FMLSv2i64_indexed: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 11;
      break;
    }
    case AArch64::BF16DOTlanev4bf16:
    case AArch64::BF16DOTlanev8bf16:
    case AArch64::FDOTlanev2f32:
    case AArch64::FDOTlanev4f16_v2f32:
    case AArch64::FDOTlanev4f32:
    case AArch64::FDOTlanev8f16_v4f32:
    case AArch64::FMLAv1i32_indexed:
    case AArch64::FMLAv2i32_indexed:
    case AArch64::FMLAv4i32_indexed:
    case AArch64::FMLSv1i32_indexed:
    case AArch64::FMLSv2i32_indexed:
    case AArch64::FMLSv4i32_indexed:
    case AArch64::MLAv2i32_indexed:
    case AArch64::MLAv4i32_indexed:
    case AArch64::MLSv2i32_indexed:
    case AArch64::MLSv4i32_indexed:
    case AArch64::SDOTlanev16i8:
    case AArch64::SDOTlanev8i8:
    case AArch64::SMLALv2i32_indexed:
    case AArch64::SMLALv4i32_indexed:
    case AArch64::SMLSLv2i32_indexed:
    case AArch64::SMLSLv4i32_indexed:
    case AArch64::SQDMLALv1i64_indexed:
    case AArch64::SQDMLALv2i32_indexed:
    case AArch64::SQDMLALv4i32_indexed:
    case AArch64::SQDMLSLv1i64_indexed:
    case AArch64::SQDMLSLv2i32_indexed:
    case AArch64::SQDMLSLv4i32_indexed:
    case AArch64::SQRDMLAHv1i32_indexed:
    case AArch64::SQRDMLAHv2i32_indexed:
    case AArch64::SQRDMLAHv4i32_indexed:
    case AArch64::SQRDMLSHv1i32_indexed:
    case AArch64::SQRDMLSHv2i32_indexed:
    case AArch64::SQRDMLSHv4i32_indexed:
    case AArch64::SUDOTlanev16i8:
    case AArch64::SUDOTlanev8i8:
    case AArch64::UDOTlanev16i8:
    case AArch64::UDOTlanev8i8:
    case AArch64::UMLALv2i32_indexed:
    case AArch64::UMLALv4i32_indexed:
    case AArch64::UMLSLv2i32_indexed:
    case AArch64::UMLSLv4i32_indexed:
    case AArch64::USDOTlanev16i8:
    case AArch64::USDOTlanev8i8: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 21;
      Value |= (op & 0x2) << 10;
      break;
    }
    case AArch64::FCMLAv2f32:
    case AArch64::FCMLAv2f64:
    case AArch64::FCMLAv4f16:
    case AArch64::FCMLAv4f32:
    case AArch64::FCMLAv8f16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 11;
      break;
    }
    case AArch64::FCMLAv4f32_indexed: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 11;
      break;
    }
    case AArch64::FCMLAv4f16_indexed: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 21;
      break;
    }
    case AArch64::FCMLAv8f16_indexed: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 21;
      Value |= (op & 0x2) << 10;
      break;
    }
    case AArch64::FMLALBlanev8f16:
    case AArch64::FMLALLBBlanev4f32:
    case AArch64::FMLALLBTlanev4f32:
    case AArch64::FMLALLTBlanev4f32:
    case AArch64::FMLALLTTlanev4f32:
    case AArch64::FMLALTlanev8f16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 19;
      Value |= (op & 0x8) << 8;
      break;
    }
    case AArch64::BFMLALBIdx:
    case AArch64::BFMLALTIdx:
    case AArch64::FDOTlanev4f16:
    case AArch64::FDOTlanev8f16:
    case AArch64::FMLAL2lanev4f16:
    case AArch64::FMLAL2lanev8f16:
    case AArch64::FMLALlanev4f16:
    case AArch64::FMLALlanev8f16:
    case AArch64::FMLAv1i16_indexed:
    case AArch64::FMLAv4i16_indexed:
    case AArch64::FMLAv8i16_indexed:
    case AArch64::FMLSL2lanev4f16:
    case AArch64::FMLSL2lanev8f16:
    case AArch64::FMLSLlanev4f16:
    case AArch64::FMLSLlanev8f16:
    case AArch64::FMLSv1i16_indexed:
    case AArch64::FMLSv4i16_indexed:
    case AArch64::FMLSv8i16_indexed:
    case AArch64::MLAv4i16_indexed:
    case AArch64::MLAv8i16_indexed:
    case AArch64::MLSv4i16_indexed:
    case AArch64::MLSv8i16_indexed:
    case AArch64::SMLALv4i16_indexed:
    case AArch64::SMLALv8i16_indexed:
    case AArch64::SMLSLv4i16_indexed:
    case AArch64::SMLSLv8i16_indexed:
    case AArch64::SQDMLALv1i32_indexed:
    case AArch64::SQDMLALv4i16_indexed:
    case AArch64::SQDMLALv8i16_indexed:
    case AArch64::SQDMLSLv1i32_indexed:
    case AArch64::SQDMLSLv4i16_indexed:
    case AArch64::SQDMLSLv8i16_indexed:
    case AArch64::SQRDMLAHv1i16_indexed:
    case AArch64::SQRDMLAHv4i16_indexed:
    case AArch64::SQRDMLAHv8i16_indexed:
    case AArch64::SQRDMLSHv1i16_indexed:
    case AArch64::SQRDMLSHv4i16_indexed:
    case AArch64::SQRDMLSHv8i16_indexed:
    case AArch64::UMLALv4i16_indexed:
    case AArch64::UMLALv8i16_indexed:
    case AArch64::UMLSLv4i16_indexed:
    case AArch64::UMLSLv8i16_indexed: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 20;
      Value |= (op & 0x4) << 9;
      break;
    }
    case AArch64::SLIv4i16_shift:
    case AArch64::SLIv8i16_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL16OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::SLIv2i32_shift:
    case AArch64::SLIv4i32_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL32OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SLId:
    case AArch64::SLIv2i64_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL64OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x3f) << 16;
      break;
    }
    case AArch64::SLIv16i8_shift:
    case AArch64::SLIv8i8_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL8OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::RSHRNv16i8_shift:
    case AArch64::SHRNv16i8_shift:
    case AArch64::SQRSHRNv16i8_shift:
    case AArch64::SQRSHRUNv16i8_shift:
    case AArch64::SQSHRNv16i8_shift:
    case AArch64::SQSHRUNv16i8_shift:
    case AArch64::UQRSHRNv16i8_shift:
    case AArch64::UQSHRNv16i8_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::SRIv4i16_shift:
    case AArch64::SRIv8i16_shift:
    case AArch64::SRSRAv4i16_shift:
    case AArch64::SRSRAv8i16_shift:
    case AArch64::SSRAv4i16_shift:
    case AArch64::SSRAv8i16_shift:
    case AArch64::URSRAv4i16_shift:
    case AArch64::URSRAv8i16_shift:
    case AArch64::USRAv4i16_shift:
    case AArch64::USRAv8i16_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::SRIv2i32_shift:
    case AArch64::SRIv4i32_shift:
    case AArch64::SRSRAv2i32_shift:
    case AArch64::SRSRAv4i32_shift:
    case AArch64::SSRAv2i32_shift:
    case AArch64::SSRAv4i32_shift:
    case AArch64::URSRAv2i32_shift:
    case AArch64::URSRAv4i32_shift:
    case AArch64::USRAv2i32_shift:
    case AArch64::USRAv4i32_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::RSHRNv8i16_shift:
    case AArch64::SHRNv8i16_shift:
    case AArch64::SQRSHRNv8i16_shift:
    case AArch64::SQRSHRUNv8i16_shift:
    case AArch64::SQSHRNv8i16_shift:
    case AArch64::SQSHRUNv8i16_shift:
    case AArch64::UQRSHRNv8i16_shift:
    case AArch64::UQSHRNv8i16_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::RSHRNv4i32_shift:
    case AArch64::SHRNv4i32_shift:
    case AArch64::SQRSHRNv4i32_shift:
    case AArch64::SQRSHRUNv4i32_shift:
    case AArch64::SQSHRNv4i32_shift:
    case AArch64::SQSHRUNv4i32_shift:
    case AArch64::UQRSHRNv4i32_shift:
    case AArch64::UQSHRNv4i32_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SRId:
    case AArch64::SRIv2i64_shift:
    case AArch64::SRSRAd:
    case AArch64::SRSRAv2i64_shift:
    case AArch64::SSRAd:
    case AArch64::SSRAv2i64_shift:
    case AArch64::URSRAd:
    case AArch64::URSRAv2i64_shift:
    case AArch64::USRAd:
    case AArch64::USRAv2i64_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x3f) << 16;
      break;
    }
    case AArch64::SRIv16i8_shift:
    case AArch64::SRIv8i8_shift:
    case AArch64::SRSRAv16i8_shift:
    case AArch64::SRSRAv8i8_shift:
    case AArch64::SSRAv16i8_shift:
    case AArch64::SSRAv8i8_shift:
    case AArch64::URSRAv16i8_shift:
    case AArch64::URSRAv8i8_shift:
    case AArch64::USRAv16i8_shift:
    case AArch64::USRAv8i8_shift: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::INSvi64gpr: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 20;
      break;
    }
    case AArch64::INSvi64lane: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 20;
      // op: idx2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 14;
      break;
    }
    case AArch64::INSvi32gpr: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::INSvi32lane: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 19;
      // op: idx2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 13;
      break;
    }
    case AArch64::INSvi16gpr: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 18;
      break;
    }
    case AArch64::INSvi16lane: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: idx2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 12;
      break;
    }
    case AArch64::INSvi8gpr: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 17;
      break;
    }
    case AArch64::INSvi8lane: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 17;
      // op: idx2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0xf) << 11;
      break;
    }
    case AArch64::BICv4i16:
    case AArch64::BICv8i16:
    case AArch64::ORRv4i16:
    case AArch64::ORRv8i16: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xe0) << 11;
      Value |= (op & 0x1f) << 5;
      // op: shift
      op = getVecShifterOpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1) << 13;
      break;
    }
    case AArch64::BICv2i32:
    case AArch64::BICv4i32:
    case AArch64::ORRv2i32:
    case AArch64::ORRv4i32: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xe0) << 11;
      Value |= (op & 0x1f) << 5;
      // op: shift
      op = getVecShifterOpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      break;
    }
    case AArch64::SETGOE:
    case AArch64::SETGOEN:
    case AArch64::SETGOET:
    case AArch64::SETGOETN:
    case AArch64::SETGOM:
    case AArch64::SETGOMN:
    case AArch64::SETGOMT:
    case AArch64::SETGOMTN:
    case AArch64::SETGOP:
    case AArch64::SETGOPN:
    case AArch64::SETGOPT:
    case AArch64::SETGOPTN: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::MOPSSETGE:
    case AArch64::MOPSSETGEN:
    case AArch64::MOPSSETGET:
    case AArch64::MOPSSETGETN:
    case AArch64::SETE:
    case AArch64::SETEN:
    case AArch64::SETET:
    case AArch64::SETETN:
    case AArch64::SETGM:
    case AArch64::SETGMN:
    case AArch64::SETGMT:
    case AArch64::SETGMTN:
    case AArch64::SETGP:
    case AArch64::SETGPN:
    case AArch64::SETGPT:
    case AArch64::SETGPTN:
    case AArch64::SETM:
    case AArch64::SETMN:
    case AArch64::SETMT:
    case AArch64::SETMTN:
    case AArch64::SETP:
    case AArch64::SETPN:
    case AArch64::SETPT:
    case AArch64::SETPTN: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::CPYE:
    case AArch64::CPYEN:
    case AArch64::CPYERN:
    case AArch64::CPYERT:
    case AArch64::CPYERTN:
    case AArch64::CPYERTRN:
    case AArch64::CPYERTWN:
    case AArch64::CPYET:
    case AArch64::CPYETN:
    case AArch64::CPYETRN:
    case AArch64::CPYETWN:
    case AArch64::CPYEWN:
    case AArch64::CPYEWT:
    case AArch64::CPYEWTN:
    case AArch64::CPYEWTRN:
    case AArch64::CPYEWTWN:
    case AArch64::CPYFE:
    case AArch64::CPYFEN:
    case AArch64::CPYFERN:
    case AArch64::CPYFERT:
    case AArch64::CPYFERTN:
    case AArch64::CPYFERTRN:
    case AArch64::CPYFERTWN:
    case AArch64::CPYFET:
    case AArch64::CPYFETN:
    case AArch64::CPYFETRN:
    case AArch64::CPYFETWN:
    case AArch64::CPYFEWN:
    case AArch64::CPYFEWT:
    case AArch64::CPYFEWTN:
    case AArch64::CPYFEWTRN:
    case AArch64::CPYFEWTWN:
    case AArch64::CPYFM:
    case AArch64::CPYFMN:
    case AArch64::CPYFMRN:
    case AArch64::CPYFMRT:
    case AArch64::CPYFMRTN:
    case AArch64::CPYFMRTRN:
    case AArch64::CPYFMRTWN:
    case AArch64::CPYFMT:
    case AArch64::CPYFMTN:
    case AArch64::CPYFMTRN:
    case AArch64::CPYFMTWN:
    case AArch64::CPYFMWN:
    case AArch64::CPYFMWT:
    case AArch64::CPYFMWTN:
    case AArch64::CPYFMWTRN:
    case AArch64::CPYFMWTWN:
    case AArch64::CPYFP:
    case AArch64::CPYFPN:
    case AArch64::CPYFPRN:
    case AArch64::CPYFPRT:
    case AArch64::CPYFPRTN:
    case AArch64::CPYFPRTRN:
    case AArch64::CPYFPRTWN:
    case AArch64::CPYFPT:
    case AArch64::CPYFPTN:
    case AArch64::CPYFPTRN:
    case AArch64::CPYFPTWN:
    case AArch64::CPYFPWN:
    case AArch64::CPYFPWT:
    case AArch64::CPYFPWTN:
    case AArch64::CPYFPWTRN:
    case AArch64::CPYFPWTWN:
    case AArch64::CPYM:
    case AArch64::CPYMN:
    case AArch64::CPYMRN:
    case AArch64::CPYMRT:
    case AArch64::CPYMRTN:
    case AArch64::CPYMRTRN:
    case AArch64::CPYMRTWN:
    case AArch64::CPYMT:
    case AArch64::CPYMTN:
    case AArch64::CPYMTRN:
    case AArch64::CPYMTWN:
    case AArch64::CPYMWN:
    case AArch64::CPYMWT:
    case AArch64::CPYMWTN:
    case AArch64::CPYMWTRN:
    case AArch64::CPYMWTWN:
    case AArch64::CPYP:
    case AArch64::CPYPN:
    case AArch64::CPYPRN:
    case AArch64::CPYPRT:
    case AArch64::CPYPRTN:
    case AArch64::CPYPRTRN:
    case AArch64::CPYPRTWN:
    case AArch64::CPYPT:
    case AArch64::CPYPTN:
    case AArch64::CPYPTRN:
    case AArch64::CPYPTWN:
    case AArch64::CPYPWN:
    case AArch64::CPYPWT:
    case AArch64::CPYPWTN:
    case AArch64::CPYPWTRN:
    case AArch64::CPYPWTWN: {
      // op: Rd
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rs
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::DECP_XP_B:
    case AArch64::DECP_XP_D:
    case AArch64::DECP_XP_H:
    case AArch64::DECP_XP_S:
    case AArch64::INCP_XP_B:
    case AArch64::INCP_XP_D:
    case AArch64::INCP_XP_H:
    case AArch64::INCP_XP_S:
    case AArch64::SQDECP_XPWd_B:
    case AArch64::SQDECP_XPWd_D:
    case AArch64::SQDECP_XPWd_H:
    case AArch64::SQDECP_XPWd_S:
    case AArch64::SQDECP_XP_B:
    case AArch64::SQDECP_XP_D:
    case AArch64::SQDECP_XP_H:
    case AArch64::SQDECP_XP_S:
    case AArch64::SQINCP_XPWd_B:
    case AArch64::SQINCP_XPWd_D:
    case AArch64::SQINCP_XPWd_H:
    case AArch64::SQINCP_XPWd_S:
    case AArch64::SQINCP_XP_B:
    case AArch64::SQINCP_XP_D:
    case AArch64::SQINCP_XP_H:
    case AArch64::SQINCP_XP_S:
    case AArch64::UQDECP_WP_B:
    case AArch64::UQDECP_WP_D:
    case AArch64::UQDECP_WP_H:
    case AArch64::UQDECP_WP_S:
    case AArch64::UQDECP_XP_B:
    case AArch64::UQDECP_XP_D:
    case AArch64::UQDECP_XP_H:
    case AArch64::UQDECP_XP_S:
    case AArch64::UQINCP_WP_B:
    case AArch64::UQINCP_WP_D:
    case AArch64::UQINCP_WP_H:
    case AArch64::UQINCP_WP_S:
    case AArch64::UQINCP_XP_B:
    case AArch64::UQINCP_XP_D:
    case AArch64::UQINCP_XP_H:
    case AArch64::UQINCP_XP_S: {
      // op: Rdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::DECB_XPiI:
    case AArch64::DECD_XPiI:
    case AArch64::DECH_XPiI:
    case AArch64::DECW_XPiI:
    case AArch64::INCB_XPiI:
    case AArch64::INCD_XPiI:
    case AArch64::INCH_XPiI:
    case AArch64::INCW_XPiI:
    case AArch64::SQDECB_XPiI:
    case AArch64::SQDECB_XPiWdI:
    case AArch64::SQDECD_XPiI:
    case AArch64::SQDECD_XPiWdI:
    case AArch64::SQDECH_XPiI:
    case AArch64::SQDECH_XPiWdI:
    case AArch64::SQDECW_XPiI:
    case AArch64::SQDECW_XPiWdI:
    case AArch64::SQINCB_XPiI:
    case AArch64::SQINCB_XPiWdI:
    case AArch64::SQINCD_XPiI:
    case AArch64::SQINCD_XPiWdI:
    case AArch64::SQINCH_XPiI:
    case AArch64::SQINCH_XPiWdI:
    case AArch64::SQINCW_XPiI:
    case AArch64::SQINCW_XPiWdI:
    case AArch64::UQDECB_WPiI:
    case AArch64::UQDECB_XPiI:
    case AArch64::UQDECD_WPiI:
    case AArch64::UQDECD_XPiI:
    case AArch64::UQDECH_WPiI:
    case AArch64::UQDECH_XPiI:
    case AArch64::UQDECW_WPiI:
    case AArch64::UQDECW_XPiI:
    case AArch64::UQINCB_WPiI:
    case AArch64::UQINCB_XPiI:
    case AArch64::UQINCD_WPiI:
    case AArch64::UQINCD_XPiI:
    case AArch64::UQINCH_WPiI:
    case AArch64::UQINCH_XPiI:
    case AArch64::UQINCW_WPiI:
    case AArch64::UQINCW_XPiI: {
      // op: Rdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: pattern
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm4
      op = getSVEIncDecImm(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::RETAASPPCr:
    case AArch64::RETABSPPCr: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::CTERMEQ_WW:
    case AArch64::CTERMEQ_XX:
    case AArch64::CTERMNE_WW:
    case AArch64::CTERMNE_XX:
    case AArch64::FCMPDrr:
    case AArch64::FCMPEDrr:
    case AArch64::FCMPEHrr:
    case AArch64::FCMPESrr:
    case AArch64::FCMPHrr:
    case AArch64::FCMPSrr: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::CBBEQWrr:
    case AArch64::CBBGEWrr:
    case AArch64::CBBGTWrr:
    case AArch64::CBBHIWrr:
    case AArch64::CBBHSWrr:
    case AArch64::CBBNEWrr:
    case AArch64::CBEQWrr:
    case AArch64::CBEQXrr:
    case AArch64::CBGEWrr:
    case AArch64::CBGEXrr:
    case AArch64::CBGTWrr:
    case AArch64::CBGTXrr:
    case AArch64::CBHEQWrr:
    case AArch64::CBHGEWrr:
    case AArch64::CBHGTWrr:
    case AArch64::CBHHIWrr:
    case AArch64::CBHHSWrr:
    case AArch64::CBHIWrr:
    case AArch64::CBHIXrr:
    case AArch64::CBHNEWrr:
    case AArch64::CBHSWrr:
    case AArch64::CBHSXrr:
    case AArch64::CBNEWrr:
    case AArch64::CBNEXrr: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: target
      op = getCondCompBranchTargetOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1ff) << 5;
      break;
    }
    case AArch64::INDEX_IR_B:
    case AArch64::INDEX_IR_D:
    case AArch64::INDEX_IR_H:
    case AArch64::INDEX_IR_S: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::INSR_ZR_B:
    case AArch64::INSR_ZR_D:
    case AArch64::INSR_ZR_H:
    case AArch64::INSR_ZR_S: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::LD1B_2Z_STRIDED:
    case AArch64::LD1D_2Z_STRIDED:
    case AArch64::LD1H_2Z_STRIDED:
    case AArch64::LD1W_2Z_STRIDED:
    case AArch64::LDNT1B_2Z_STRIDED:
    case AArch64::LDNT1D_2Z_STRIDED:
    case AArch64::LDNT1H_2Z_STRIDED:
    case AArch64::LDNT1W_2Z_STRIDED:
    case AArch64::ST1B_2Z_STRIDED:
    case AArch64::ST1D_2Z_STRIDED:
    case AArch64::ST1H_2Z_STRIDED:
    case AArch64::ST1W_2Z_STRIDED:
    case AArch64::STNT1B_2Z_STRIDED:
    case AArch64::STNT1D_2Z_STRIDED:
    case AArch64::STNT1H_2Z_STRIDED:
    case AArch64::STNT1W_2Z_STRIDED: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = EncodeZPR2StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x8) << 1;
      Value |= (op & 0x7);
      break;
    }
    case AArch64::LD1B_4Z_STRIDED:
    case AArch64::LD1D_4Z_STRIDED:
    case AArch64::LD1H_4Z_STRIDED:
    case AArch64::LD1W_4Z_STRIDED:
    case AArch64::LDNT1B_4Z_STRIDED:
    case AArch64::LDNT1D_4Z_STRIDED:
    case AArch64::LDNT1H_4Z_STRIDED:
    case AArch64::LDNT1W_4Z_STRIDED:
    case AArch64::ST1B_4Z_STRIDED:
    case AArch64::ST1D_4Z_STRIDED:
    case AArch64::ST1H_4Z_STRIDED:
    case AArch64::ST1W_4Z_STRIDED:
    case AArch64::STNT1B_4Z_STRIDED:
    case AArch64::STNT1D_4Z_STRIDED:
    case AArch64::STNT1H_4Z_STRIDED:
    case AArch64::STNT1W_4Z_STRIDED: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x4) << 2;
      Value |= (op & 0x3);
      break;
    }
    case AArch64::PRFB_PRR:
    case AArch64::PRFD_PRR:
    case AArch64::PRFH_PRR:
    case AArch64::PRFW_PRR: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: prfop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::LD1_MXIPXX_H_H:
    case AArch64::LD1_MXIPXX_V_H:
    case AArch64::ST1_MXIPXX_H_H:
    case AArch64::ST1_MXIPXX_V_H: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1) << 3;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::LD1_MXIPXX_H_S:
    case AArch64::LD1_MXIPXX_V_S:
    case AArch64::ST1_MXIPXX_H_S:
    case AArch64::ST1_MXIPXX_V_S: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 2;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::LD1_MXIPXX_H_D:
    case AArch64::LD1_MXIPXX_V_D:
    case AArch64::ST1_MXIPXX_H_D:
    case AArch64::ST1_MXIPXX_V_D: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 1;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1);
      break;
    }
    case AArch64::LD1_MXIPXX_H_Q:
    case AArch64::LD1_MXIPXX_V_Q:
    case AArch64::ST1_MXIPXX_H_Q:
    case AArch64::ST1_MXIPXX_V_Q: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::LD1_MXIPXX_H_B:
    case AArch64::LD1_MXIPXX_V_B:
    case AArch64::ST1_MXIPXX_H_B:
    case AArch64::ST1_MXIPXX_V_B: {
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::AUTIASPPCr:
    case AArch64::AUTIBSPPCr:
    case AArch64::BLR:
    case AArch64::BLRAAZ:
    case AArch64::BLRABZ:
    case AArch64::BR:
    case AArch64::BRAAZ:
    case AArch64::BRABZ:
    case AArch64::RET:
    case AArch64::SETF16:
    case AArch64::SETF8: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::CCMNWr:
    case AArch64::CCMNXr:
    case AArch64::CCMPWr:
    case AArch64::CCMPXr:
    case AArch64::FCCMPDrr:
    case AArch64::FCCMPEDrr:
    case AArch64::FCCMPEHrr:
    case AArch64::FCCMPESrr:
    case AArch64::FCCMPHrr:
    case AArch64::FCCMPSrr: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: nzcv
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf);
      // op: cond
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 12;
      break;
    }
    case AArch64::BLRAA:
    case AArch64::BLRAB:
    case AArch64::BRAA:
    case AArch64::BRAB: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::CCMNWi:
    case AArch64::CCMNXi:
    case AArch64::CCMPWi:
    case AArch64::CCMPXi: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: nzcv
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf);
      // op: cond
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 12;
      break;
    }
    case AArch64::RMIF: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3f) << 15;
      // op: mask
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::FCMPDri:
    case AArch64::FCMPEDri:
    case AArch64::FCMPEHri:
    case AArch64::FCMPESri:
    case AArch64::FCMPHri:
    case AArch64::FCMPSri: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      Value = fixOneOperandFPComparison(MI, Value, STI);
      break;
    }
    case AArch64::LDR_TX:
    case AArch64::STR_TX: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::LDAPRB:
    case AArch64::LDAPRH:
    case AArch64::LDAPRW:
    case AArch64::LDAPRX:
    case AArch64::LDGM:
    case AArch64::STGM:
    case AArch64::STZGM: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::ST2Gi:
    case AArch64::STGi:
    case AArch64::STZ2Gi:
    case AArch64::STZGi: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1ff) << 12;
      break;
    }
    case AArch64::DUP_ZR_B:
    case AArch64::DUP_ZR_D:
    case AArch64::DUP_ZR_H:
    case AArch64::DUP_ZR_S: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::INDEX_RI_B:
    case AArch64::INDEX_RI_D:
    case AArch64::INDEX_RI_H:
    case AArch64::INDEX_RI_S: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LDR_ZXI:
    case AArch64::STR_ZXI: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm9
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f8) << 13;
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::PRFB_PRI:
    case AArch64::PRFD_PRI:
    case AArch64::PRFH_PRI:
    case AArch64::PRFW_PRI: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: imm6
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 16;
      // op: prfop
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::LDG:
    case AArch64::ST2GPostIndex:
    case AArch64::ST2GPreIndex:
    case AArch64::STGPostIndex:
    case AArch64::STGPreIndex:
    case AArch64::STZ2GPostIndex:
    case AArch64::STZ2GPreIndex:
    case AArch64::STZGPostIndex:
    case AArch64::STZGPreIndex: {
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1ff) << 12;
      break;
    }
    case AArch64::MOVA_MXI2Z_H_H:
    case AArch64::MOVA_MXI2Z_V_H: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1) << 2;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::MOVA_MXI2Z_H_S:
    case AArch64::MOVA_MXI2Z_V_S: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 1;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      break;
    }
    case AArch64::MOVA_MXI2Z_H_D:
    case AArch64::MOVA_MXI2Z_V_D: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::MOVA_MXI2Z_H_B:
    case AArch64::MOVA_MXI2Z_V_B: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::MOVA_MXI4Z_H_H:
    case AArch64::MOVA_MXI4Z_V_H: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1) << 1;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      break;
    }
    case AArch64::MOVA_MXI4Z_H_S:
    case AArch64::MOVA_MXI4Z_V_S: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::MOVA_MXI4Z_H_D:
    case AArch64::MOVA_MXI4Z_V_D: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::MOVA_MXI4Z_H_B:
    case AArch64::MOVA_MXI4Z_V_B: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::MOVAZ_ZMI_H_H:
    case AArch64::MOVAZ_ZMI_V_H: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1) << 8;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::MOVAZ_ZMI_H_S:
    case AArch64::MOVAZ_ZMI_V_S: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 7;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 5;
      break;
    }
    case AArch64::MOVAZ_ZMI_H_D:
    case AArch64::MOVAZ_ZMI_V_D: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 5;
      break;
    }
    case AArch64::MOVAZ_ZMI_H_Q:
    case AArch64::MOVAZ_ZMI_V_Q: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::MOVAZ_ZMI_H_B:
    case AArch64::MOVAZ_ZMI_V_B: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::MOVA_VG2_2ZMXI: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::MOVA_VG4_4ZMXI: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case AArch64::MOVA_VG2_MXI2Z: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      break;
    }
    case AArch64::MOVA_VG4_MXI4Z: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      break;
    }
    case AArch64::MOVAZ_VG2_2ZMXI: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::MOVAZ_VG4_4ZMXI: {
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case AArch64::STBFADD:
    case AArch64::STBFADDL:
    case AArch64::STBFMAX:
    case AArch64::STBFMAXL:
    case AArch64::STBFMAXNM:
    case AArch64::STBFMAXNML:
    case AArch64::STBFMIN:
    case AArch64::STBFMINL:
    case AArch64::STBFMINNM:
    case AArch64::STBFMINNML:
    case AArch64::STFADDD:
    case AArch64::STFADDH:
    case AArch64::STFADDLD:
    case AArch64::STFADDLH:
    case AArch64::STFADDLS:
    case AArch64::STFADDS:
    case AArch64::STFMAXD:
    case AArch64::STFMAXH:
    case AArch64::STFMAXLD:
    case AArch64::STFMAXLH:
    case AArch64::STFMAXLS:
    case AArch64::STFMAXNMD:
    case AArch64::STFMAXNMH:
    case AArch64::STFMAXNMLD:
    case AArch64::STFMAXNMLH:
    case AArch64::STFMAXNMLS:
    case AArch64::STFMAXNMS:
    case AArch64::STFMAXS:
    case AArch64::STFMIND:
    case AArch64::STFMINH:
    case AArch64::STFMINLD:
    case AArch64::STFMINLH:
    case AArch64::STFMINLS:
    case AArch64::STFMINNMD:
    case AArch64::STFMINNMH:
    case AArch64::STFMINNMLD:
    case AArch64::STFMINNMLH:
    case AArch64::STFMINNMLS:
    case AArch64::STFMINNMS:
    case AArch64::STFMINS: {
      // op: Rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::LDADDAB:
    case AArch64::LDADDAH:
    case AArch64::LDADDALB:
    case AArch64::LDADDALH:
    case AArch64::LDADDALW:
    case AArch64::LDADDALX:
    case AArch64::LDADDAW:
    case AArch64::LDADDAX:
    case AArch64::LDADDB:
    case AArch64::LDADDH:
    case AArch64::LDADDLB:
    case AArch64::LDADDLH:
    case AArch64::LDADDLW:
    case AArch64::LDADDLX:
    case AArch64::LDADDW:
    case AArch64::LDADDX:
    case AArch64::LDCLRAB:
    case AArch64::LDCLRAH:
    case AArch64::LDCLRALB:
    case AArch64::LDCLRALH:
    case AArch64::LDCLRALW:
    case AArch64::LDCLRALX:
    case AArch64::LDCLRAW:
    case AArch64::LDCLRAX:
    case AArch64::LDCLRB:
    case AArch64::LDCLRH:
    case AArch64::LDCLRLB:
    case AArch64::LDCLRLH:
    case AArch64::LDCLRLW:
    case AArch64::LDCLRLX:
    case AArch64::LDCLRW:
    case AArch64::LDCLRX:
    case AArch64::LDEORAB:
    case AArch64::LDEORAH:
    case AArch64::LDEORALB:
    case AArch64::LDEORALH:
    case AArch64::LDEORALW:
    case AArch64::LDEORALX:
    case AArch64::LDEORAW:
    case AArch64::LDEORAX:
    case AArch64::LDEORB:
    case AArch64::LDEORH:
    case AArch64::LDEORLB:
    case AArch64::LDEORLH:
    case AArch64::LDEORLW:
    case AArch64::LDEORLX:
    case AArch64::LDEORW:
    case AArch64::LDEORX:
    case AArch64::LDSETAB:
    case AArch64::LDSETAH:
    case AArch64::LDSETALB:
    case AArch64::LDSETALH:
    case AArch64::LDSETALW:
    case AArch64::LDSETALX:
    case AArch64::LDSETAW:
    case AArch64::LDSETAX:
    case AArch64::LDSETB:
    case AArch64::LDSETH:
    case AArch64::LDSETLB:
    case AArch64::LDSETLH:
    case AArch64::LDSETLW:
    case AArch64::LDSETLX:
    case AArch64::LDSETW:
    case AArch64::LDSETX:
    case AArch64::LDSMAXAB:
    case AArch64::LDSMAXAH:
    case AArch64::LDSMAXALB:
    case AArch64::LDSMAXALH:
    case AArch64::LDSMAXALW:
    case AArch64::LDSMAXALX:
    case AArch64::LDSMAXAW:
    case AArch64::LDSMAXAX:
    case AArch64::LDSMAXB:
    case AArch64::LDSMAXH:
    case AArch64::LDSMAXLB:
    case AArch64::LDSMAXLH:
    case AArch64::LDSMAXLW:
    case AArch64::LDSMAXLX:
    case AArch64::LDSMAXW:
    case AArch64::LDSMAXX:
    case AArch64::LDSMINAB:
    case AArch64::LDSMINAH:
    case AArch64::LDSMINALB:
    case AArch64::LDSMINALH:
    case AArch64::LDSMINALW:
    case AArch64::LDSMINALX:
    case AArch64::LDSMINAW:
    case AArch64::LDSMINAX:
    case AArch64::LDSMINB:
    case AArch64::LDSMINH:
    case AArch64::LDSMINLB:
    case AArch64::LDSMINLH:
    case AArch64::LDSMINLW:
    case AArch64::LDSMINLX:
    case AArch64::LDSMINW:
    case AArch64::LDSMINX:
    case AArch64::LDTADDALW:
    case AArch64::LDTADDALX:
    case AArch64::LDTADDAW:
    case AArch64::LDTADDAX:
    case AArch64::LDTADDLW:
    case AArch64::LDTADDLX:
    case AArch64::LDTADDW:
    case AArch64::LDTADDX:
    case AArch64::LDTCLRALW:
    case AArch64::LDTCLRALX:
    case AArch64::LDTCLRAW:
    case AArch64::LDTCLRAX:
    case AArch64::LDTCLRLW:
    case AArch64::LDTCLRLX:
    case AArch64::LDTCLRW:
    case AArch64::LDTCLRX:
    case AArch64::LDTSETALW:
    case AArch64::LDTSETALX:
    case AArch64::LDTSETAW:
    case AArch64::LDTSETAX:
    case AArch64::LDTSETLW:
    case AArch64::LDTSETLX:
    case AArch64::LDTSETW:
    case AArch64::LDTSETX:
    case AArch64::LDUMAXAB:
    case AArch64::LDUMAXAH:
    case AArch64::LDUMAXALB:
    case AArch64::LDUMAXALH:
    case AArch64::LDUMAXALW:
    case AArch64::LDUMAXALX:
    case AArch64::LDUMAXAW:
    case AArch64::LDUMAXAX:
    case AArch64::LDUMAXB:
    case AArch64::LDUMAXH:
    case AArch64::LDUMAXLB:
    case AArch64::LDUMAXLH:
    case AArch64::LDUMAXLW:
    case AArch64::LDUMAXLX:
    case AArch64::LDUMAXW:
    case AArch64::LDUMAXX:
    case AArch64::LDUMINAB:
    case AArch64::LDUMINAH:
    case AArch64::LDUMINALB:
    case AArch64::LDUMINALH:
    case AArch64::LDUMINALW:
    case AArch64::LDUMINALX:
    case AArch64::LDUMINAW:
    case AArch64::LDUMINAX:
    case AArch64::LDUMINB:
    case AArch64::LDUMINH:
    case AArch64::LDUMINLB:
    case AArch64::LDUMINLH:
    case AArch64::LDUMINLW:
    case AArch64::LDUMINLX:
    case AArch64::LDUMINW:
    case AArch64::LDUMINX:
    case AArch64::RCWCLR:
    case AArch64::RCWCLRA:
    case AArch64::RCWCLRAL:
    case AArch64::RCWCLRL:
    case AArch64::RCWCLRS:
    case AArch64::RCWCLRSA:
    case AArch64::RCWCLRSAL:
    case AArch64::RCWCLRSL:
    case AArch64::RCWSET:
    case AArch64::RCWSETA:
    case AArch64::RCWSETAL:
    case AArch64::RCWSETL:
    case AArch64::RCWSETS:
    case AArch64::RCWSETSA:
    case AArch64::RCWSETSAL:
    case AArch64::RCWSETSL:
    case AArch64::RCWSWP:
    case AArch64::RCWSWPA:
    case AArch64::RCWSWPAL:
    case AArch64::RCWSWPL:
    case AArch64::RCWSWPS:
    case AArch64::RCWSWPSA:
    case AArch64::RCWSWPSAL:
    case AArch64::RCWSWPSL:
    case AArch64::SWPAB:
    case AArch64::SWPAH:
    case AArch64::SWPALB:
    case AArch64::SWPALH:
    case AArch64::SWPALW:
    case AArch64::SWPALX:
    case AArch64::SWPAW:
    case AArch64::SWPAX:
    case AArch64::SWPB:
    case AArch64::SWPH:
    case AArch64::SWPLB:
    case AArch64::SWPLH:
    case AArch64::SWPLW:
    case AArch64::SWPLX:
    case AArch64::SWPTALW:
    case AArch64::SWPTALX:
    case AArch64::SWPTAW:
    case AArch64::SWPTAX:
    case AArch64::SWPTLW:
    case AArch64::SWPTLX:
    case AArch64::SWPTW:
    case AArch64::SWPTX:
    case AArch64::SWPW:
    case AArch64::SWPX: {
      // op: Rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::CASAB:
    case AArch64::CASAH:
    case AArch64::CASALB:
    case AArch64::CASALH:
    case AArch64::CASALTX:
    case AArch64::CASALW:
    case AArch64::CASALX:
    case AArch64::CASATX:
    case AArch64::CASAW:
    case AArch64::CASAX:
    case AArch64::CASB:
    case AArch64::CASH:
    case AArch64::CASLB:
    case AArch64::CASLH:
    case AArch64::CASLTX:
    case AArch64::CASLW:
    case AArch64::CASLX:
    case AArch64::CASPALTX:
    case AArch64::CASPALW:
    case AArch64::CASPALX:
    case AArch64::CASPATX:
    case AArch64::CASPAW:
    case AArch64::CASPAX:
    case AArch64::CASPLTX:
    case AArch64::CASPLW:
    case AArch64::CASPLX:
    case AArch64::CASPTX:
    case AArch64::CASPW:
    case AArch64::CASPX:
    case AArch64::CASTX:
    case AArch64::CASW:
    case AArch64::CASX:
    case AArch64::RCWCAS:
    case AArch64::RCWCASA:
    case AArch64::RCWCASAL:
    case AArch64::RCWCASL:
    case AArch64::RCWCASP:
    case AArch64::RCWCASPA:
    case AArch64::RCWCASPAL:
    case AArch64::RCWCASPL:
    case AArch64::RCWSCAS:
    case AArch64::RCWSCASA:
    case AArch64::RCWSCASAL:
    case AArch64::RCWSCASL:
    case AArch64::RCWSCASP:
    case AArch64::RCWSCASPA:
    case AArch64::RCWSCASPAL:
    case AArch64::RCWSCASPL: {
      // op: Rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::GCSPOPM:
    case AArch64::GCSPUSHM:
    case AArch64::GCSSS1:
    case AArch64::GCSSS2:
    case AArch64::TRCIT:
    case AArch64::WFET:
    case AArch64::WFIT: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::GCSSTR:
    case AArch64::GCSSTTR:
    case AArch64::LD64B:
    case AArch64::ST64B: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::LDRBBroW:
    case AArch64::LDRBBroX:
    case AArch64::LDRBroW:
    case AArch64::LDRBroX:
    case AArch64::LDRDroW:
    case AArch64::LDRDroX:
    case AArch64::LDRHHroW:
    case AArch64::LDRHHroX:
    case AArch64::LDRHroW:
    case AArch64::LDRHroX:
    case AArch64::LDRQroW:
    case AArch64::LDRQroX:
    case AArch64::LDRSBWroW:
    case AArch64::LDRSBWroX:
    case AArch64::LDRSBXroW:
    case AArch64::LDRSBXroX:
    case AArch64::LDRSHWroW:
    case AArch64::LDRSHWroX:
    case AArch64::LDRSHXroW:
    case AArch64::LDRSHXroX:
    case AArch64::LDRSWroW:
    case AArch64::LDRSWroX:
    case AArch64::LDRSroW:
    case AArch64::LDRSroX:
    case AArch64::LDRWroW:
    case AArch64::LDRWroX:
    case AArch64::LDRXroW:
    case AArch64::LDRXroX:
    case AArch64::PRFMroW:
    case AArch64::PRFMroX:
    case AArch64::STRBBroW:
    case AArch64::STRBBroX:
    case AArch64::STRBroW:
    case AArch64::STRBroX:
    case AArch64::STRDroW:
    case AArch64::STRDroX:
    case AArch64::STRHHroW:
    case AArch64::STRHHroX:
    case AArch64::STRHroW:
    case AArch64::STRHroX:
    case AArch64::STRQroW:
    case AArch64::STRQroX:
    case AArch64::STRSroW:
    case AArch64::STRSroX:
    case AArch64::STRWroW:
    case AArch64::STRWroX:
    case AArch64::STRXroW:
    case AArch64::STRXroX: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: extend
      op = getMemExtendOpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x2) << 14;
      Value |= (op & 0x1) << 12;
      break;
    }
    case AArch64::LDRQui:
    case AArch64::STRQui: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale16>(MI, 2, Fixups, STI);
      Value |= (op & 0xfff) << 10;
      break;
    }
    case AArch64::LDRBBui:
    case AArch64::LDRBui:
    case AArch64::LDRSBWui:
    case AArch64::LDRSBXui:
    case AArch64::STRBBui:
    case AArch64::STRBui: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale1>(MI, 2, Fixups, STI);
      Value |= (op & 0xfff) << 10;
      break;
    }
    case AArch64::LDRHHui:
    case AArch64::LDRHui:
    case AArch64::LDRSHWui:
    case AArch64::LDRSHXui:
    case AArch64::STRHHui:
    case AArch64::STRHui: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale2>(MI, 2, Fixups, STI);
      Value |= (op & 0xfff) << 10;
      break;
    }
    case AArch64::LDRSWui:
    case AArch64::LDRSui:
    case AArch64::LDRWui:
    case AArch64::STRSui:
    case AArch64::STRWui: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale4>(MI, 2, Fixups, STI);
      Value |= (op & 0xfff) << 10;
      break;
    }
    case AArch64::LDRDui:
    case AArch64::LDRXui:
    case AArch64::PRFMui:
    case AArch64::STRDui:
    case AArch64::STRXui: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale8>(MI, 2, Fixups, STI);
      Value |= (op & 0xfff) << 10;
      break;
    }
    case AArch64::LDAPURBi:
    case AArch64::LDAPURHi:
    case AArch64::LDAPURSBWi:
    case AArch64::LDAPURSBXi:
    case AArch64::LDAPURSHWi:
    case AArch64::LDAPURSHXi:
    case AArch64::LDAPURSWi:
    case AArch64::LDAPURXi:
    case AArch64::LDAPURi:
    case AArch64::LDTRBi:
    case AArch64::LDTRHi:
    case AArch64::LDTRSBWi:
    case AArch64::LDTRSBXi:
    case AArch64::LDTRSHWi:
    case AArch64::LDTRSHXi:
    case AArch64::LDTRSWi:
    case AArch64::LDTRWi:
    case AArch64::LDTRXi:
    case AArch64::LDURBBi:
    case AArch64::LDURBi:
    case AArch64::LDURDi:
    case AArch64::LDURHHi:
    case AArch64::LDURHi:
    case AArch64::LDURQi:
    case AArch64::LDURSBWi:
    case AArch64::LDURSBXi:
    case AArch64::LDURSHWi:
    case AArch64::LDURSHXi:
    case AArch64::LDURSWi:
    case AArch64::LDURSi:
    case AArch64::LDURWi:
    case AArch64::LDURXi:
    case AArch64::PRFUMi:
    case AArch64::STLURBi:
    case AArch64::STLURHi:
    case AArch64::STLURWi:
    case AArch64::STLURXi:
    case AArch64::STTRBi:
    case AArch64::STTRHi:
    case AArch64::STTRWi:
    case AArch64::STTRXi:
    case AArch64::STURBBi:
    case AArch64::STURBi:
    case AArch64::STURDi:
    case AArch64::STURHHi:
    case AArch64::STURHi:
    case AArch64::STURQi:
    case AArch64::STURSi:
    case AArch64::STURWi:
    case AArch64::STURXi: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1ff) << 12;
      break;
    }
    case AArch64::LDAPURbi:
    case AArch64::LDAPURdi:
    case AArch64::LDAPURhi:
    case AArch64::LDAPURqi:
    case AArch64::LDAPURsi:
    case AArch64::STLURbi:
    case AArch64::STLURdi:
    case AArch64::STLURhi:
    case AArch64::STLURqi:
    case AArch64::STLURsi: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: simm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1ff) << 12;
      break;
    }
    case AArch64::LDARB:
    case AArch64::LDARH:
    case AArch64::LDARW:
    case AArch64::LDARX:
    case AArch64::LDATXRW:
    case AArch64::LDATXRX:
    case AArch64::LDAXRB:
    case AArch64::LDAXRH:
    case AArch64::LDAXRW:
    case AArch64::LDAXRX:
    case AArch64::LDLARB:
    case AArch64::LDLARH:
    case AArch64::LDLARW:
    case AArch64::LDLARX:
    case AArch64::LDTXRWr:
    case AArch64::LDTXRXr:
    case AArch64::LDXRB:
    case AArch64::LDXRH:
    case AArch64::LDXRW:
    case AArch64::LDXRX:
    case AArch64::STLLRB:
    case AArch64::STLLRH:
    case AArch64::STLLRW:
    case AArch64::STLLRX:
    case AArch64::STLRB:
    case AArch64::STLRH:
    case AArch64::STLRW:
    case AArch64::STLRX: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      Value = fixLoadStoreExclusive<0,0>(MI, Value, STI);
      break;
    }
    case AArch64::LDIAPPW:
    case AArch64::LDIAPPX:
    case AArch64::STILPW:
    case AArch64::STILPX: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LDBFADD:
    case AArch64::LDBFADDA:
    case AArch64::LDBFADDAL:
    case AArch64::LDBFADDL:
    case AArch64::LDBFMAX:
    case AArch64::LDBFMAXA:
    case AArch64::LDBFMAXAL:
    case AArch64::LDBFMAXL:
    case AArch64::LDBFMAXNM:
    case AArch64::LDBFMAXNMA:
    case AArch64::LDBFMAXNMAL:
    case AArch64::LDBFMAXNML:
    case AArch64::LDBFMIN:
    case AArch64::LDBFMINA:
    case AArch64::LDBFMINAL:
    case AArch64::LDBFMINL:
    case AArch64::LDBFMINNM:
    case AArch64::LDBFMINNMA:
    case AArch64::LDBFMINNMAL:
    case AArch64::LDBFMINNML:
    case AArch64::LDFADDAD:
    case AArch64::LDFADDAH:
    case AArch64::LDFADDALD:
    case AArch64::LDFADDALH:
    case AArch64::LDFADDALS:
    case AArch64::LDFADDAS:
    case AArch64::LDFADDD:
    case AArch64::LDFADDH:
    case AArch64::LDFADDLD:
    case AArch64::LDFADDLH:
    case AArch64::LDFADDLS:
    case AArch64::LDFADDS:
    case AArch64::LDFMAXAD:
    case AArch64::LDFMAXAH:
    case AArch64::LDFMAXALD:
    case AArch64::LDFMAXALH:
    case AArch64::LDFMAXALS:
    case AArch64::LDFMAXAS:
    case AArch64::LDFMAXD:
    case AArch64::LDFMAXH:
    case AArch64::LDFMAXLD:
    case AArch64::LDFMAXLH:
    case AArch64::LDFMAXLS:
    case AArch64::LDFMAXNMAD:
    case AArch64::LDFMAXNMAH:
    case AArch64::LDFMAXNMALD:
    case AArch64::LDFMAXNMALH:
    case AArch64::LDFMAXNMALS:
    case AArch64::LDFMAXNMAS:
    case AArch64::LDFMAXNMD:
    case AArch64::LDFMAXNMH:
    case AArch64::LDFMAXNMLD:
    case AArch64::LDFMAXNMLH:
    case AArch64::LDFMAXNMLS:
    case AArch64::LDFMAXNMS:
    case AArch64::LDFMAXS:
    case AArch64::LDFMINAD:
    case AArch64::LDFMINAH:
    case AArch64::LDFMINALD:
    case AArch64::LDFMINALH:
    case AArch64::LDFMINALS:
    case AArch64::LDFMINAS:
    case AArch64::LDFMIND:
    case AArch64::LDFMINH:
    case AArch64::LDFMINLD:
    case AArch64::LDFMINLH:
    case AArch64::LDFMINLS:
    case AArch64::LDFMINNMAD:
    case AArch64::LDFMINNMAH:
    case AArch64::LDFMINNMALD:
    case AArch64::LDFMINNMALH:
    case AArch64::LDFMINNMALS:
    case AArch64::LDFMINNMAS:
    case AArch64::LDFMINNMD:
    case AArch64::LDFMINNMH:
    case AArch64::LDFMINNMLD:
    case AArch64::LDFMINNMLH:
    case AArch64::LDFMINNMLS:
    case AArch64::LDFMINNMS:
    case AArch64::LDFMINS: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rs
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::LDNPDi:
    case AArch64::LDNPQi:
    case AArch64::LDNPSi:
    case AArch64::LDNPWi:
    case AArch64::LDNPXi:
    case AArch64::LDPDi:
    case AArch64::LDPQi:
    case AArch64::LDPSWi:
    case AArch64::LDPSi:
    case AArch64::LDPWi:
    case AArch64::LDPXi:
    case AArch64::LDTNPQi:
    case AArch64::LDTNPXi:
    case AArch64::LDTPQi:
    case AArch64::LDTPi:
    case AArch64::STGPi:
    case AArch64::STNPDi:
    case AArch64::STNPQi:
    case AArch64::STNPSi:
    case AArch64::STNPWi:
    case AArch64::STNPXi:
    case AArch64::STPDi:
    case AArch64::STPQi:
    case AArch64::STPSi:
    case AArch64::STPWi:
    case AArch64::STPXi:
    case AArch64::STTNPQi:
    case AArch64::STTNPXi:
    case AArch64::STTPQi:
    case AArch64::STTPi: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7f) << 15;
      break;
    }
    case AArch64::LDAXPW:
    case AArch64::LDAXPX:
    case AArch64::LDXPW:
    case AArch64::LDXPX: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      Value = fixLoadStoreExclusive<0,1>(MI, Value, STI);
      break;
    }
    case AArch64::LDAPPi:
    case AArch64::LDAPi:
    case AArch64::STLPi: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::TBNZW:
    case AArch64::TBNZX:
    case AArch64::TBZW:
    case AArch64::TBZX: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: bit_off
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 19;
      // op: target
      op = getTestBranchTargetOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x3fff) << 5;
      break;
    }
    case AArch64::CBEQWri:
    case AArch64::CBEQXri:
    case AArch64::CBGTWri:
    case AArch64::CBGTXri:
    case AArch64::CBHIWri:
    case AArch64::CBHIXri:
    case AArch64::CBLOWri:
    case AArch64::CBLOXri:
    case AArch64::CBLTWri:
    case AArch64::CBLTXri:
    case AArch64::CBNEWri:
    case AArch64::CBNEXri: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3f) << 15;
      // op: target
      op = getCondCompBranchTargetOpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1ff) << 5;
      break;
    }
    case AArch64::LDRDl:
    case AArch64::LDRQl:
    case AArch64::LDRSWl:
    case AArch64::LDRSl:
    case AArch64::LDRWl:
    case AArch64::LDRXl:
    case AArch64::PRFMl: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: label
      op = getLoadLiteralOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0x7ffff) << 5;
      break;
    }
    case AArch64::SYSLxt: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: Cn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 12;
      // op: Cm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 8;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::MRRS:
    case AArch64::MRS: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: systemreg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xffff) << 5;
      break;
    }
    case AArch64::CBNZW:
    case AArch64::CBNZX:
    case AArch64::CBZW:
    case AArch64::CBZX: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: target
      op = getCondBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0x7ffff) << 5;
      break;
    }
    case AArch64::RPRFM: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x20) << 10;
      Value |= (op & 0x18) << 9;
      Value |= (op & 0x7);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LDAPRWpost:
    case AArch64::LDAPRXpost:
    case AArch64::STLRWpre:
    case AArch64::STLRXpre: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::ST64BV:
    case AArch64::ST64BV0: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rs
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::STTXRWr:
    case AArch64::STTXRXr: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Ws
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      Value = fixLoadStoreExclusive<1,0>(MI, Value, STI);
      break;
    }
    case AArch64::LDRBBpost:
    case AArch64::LDRBBpre:
    case AArch64::LDRBpost:
    case AArch64::LDRBpre:
    case AArch64::LDRDpost:
    case AArch64::LDRDpre:
    case AArch64::LDRHHpost:
    case AArch64::LDRHHpre:
    case AArch64::LDRHpost:
    case AArch64::LDRHpre:
    case AArch64::LDRQpost:
    case AArch64::LDRQpre:
    case AArch64::LDRSBWpost:
    case AArch64::LDRSBWpre:
    case AArch64::LDRSBXpost:
    case AArch64::LDRSBXpre:
    case AArch64::LDRSHWpost:
    case AArch64::LDRSHWpre:
    case AArch64::LDRSHXpost:
    case AArch64::LDRSHXpre:
    case AArch64::LDRSWpost:
    case AArch64::LDRSWpre:
    case AArch64::LDRSpost:
    case AArch64::LDRSpre:
    case AArch64::LDRWpost:
    case AArch64::LDRWpre:
    case AArch64::LDRXpost:
    case AArch64::LDRXpre:
    case AArch64::STRBBpost:
    case AArch64::STRBBpre:
    case AArch64::STRBpost:
    case AArch64::STRBpre:
    case AArch64::STRDpost:
    case AArch64::STRDpre:
    case AArch64::STRHHpost:
    case AArch64::STRHHpre:
    case AArch64::STRHpost:
    case AArch64::STRHpre:
    case AArch64::STRQpost:
    case AArch64::STRQpre:
    case AArch64::STRSpost:
    case AArch64::STRSpre:
    case AArch64::STRWpost:
    case AArch64::STRWpre:
    case AArch64::STRXpost:
    case AArch64::STRXpre: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1ff) << 12;
      break;
    }
    case AArch64::LDIAPPWpost:
    case AArch64::LDIAPPXpost:
    case AArch64::STILPWpre:
    case AArch64::STILPXpre: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LDPDpost:
    case AArch64::LDPDpre:
    case AArch64::LDPQpost:
    case AArch64::LDPQpre:
    case AArch64::LDPSWpost:
    case AArch64::LDPSWpre:
    case AArch64::LDPSpost:
    case AArch64::LDPSpre:
    case AArch64::LDPWpost:
    case AArch64::LDPWpre:
    case AArch64::LDPXpost:
    case AArch64::LDPXpre:
    case AArch64::LDTPQpost:
    case AArch64::LDTPQpre:
    case AArch64::LDTPpost:
    case AArch64::LDTPpre:
    case AArch64::STGPpost:
    case AArch64::STGPpre:
    case AArch64::STPDpost:
    case AArch64::STPDpre:
    case AArch64::STPQpost:
    case AArch64::STPQpre:
    case AArch64::STPSpost:
    case AArch64::STPSpre:
    case AArch64::STPWpost:
    case AArch64::STPWpre:
    case AArch64::STPXpost:
    case AArch64::STPXpre:
    case AArch64::STTPQpost:
    case AArch64::STTPQpre:
    case AArch64::STTPpost:
    case AArch64::STTPpre: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7f) << 15;
      break;
    }
    case AArch64::MSR:
    case AArch64::MSRR: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: systemreg
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xffff) << 5;
      break;
    }
    case AArch64::LDCLRP:
    case AArch64::LDCLRPA:
    case AArch64::LDCLRPAL:
    case AArch64::LDCLRPL:
    case AArch64::LDSETP:
    case AArch64::LDSETPA:
    case AArch64::LDSETPAL:
    case AArch64::LDSETPL:
    case AArch64::SWPP:
    case AArch64::SWPPA:
    case AArch64::SWPPAL:
    case AArch64::SWPPL: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::SYSPxt:
    case AArch64::SYSxt: {
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f);
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: Cn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 12;
      // op: Cm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 8;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::RCWCLRP:
    case AArch64::RCWCLRPA:
    case AArch64::RCWCLRPAL:
    case AArch64::RCWCLRPL:
    case AArch64::RCWCLRSP:
    case AArch64::RCWCLRSPA:
    case AArch64::RCWCLRSPAL:
    case AArch64::RCWCLRSPL:
    case AArch64::RCWSETP:
    case AArch64::RCWSETPA:
    case AArch64::RCWSETPAL:
    case AArch64::RCWSETPL:
    case AArch64::RCWSETSP:
    case AArch64::RCWSETSPA:
    case AArch64::RCWSETSPAL:
    case AArch64::RCWSETSPL:
    case AArch64::RCWSWPP:
    case AArch64::RCWSWPPA:
    case AArch64::RCWSWPPAL:
    case AArch64::RCWSWPPL:
    case AArch64::RCWSWPSP:
    case AArch64::RCWSWPSPA:
    case AArch64::RCWSWPSPAL:
    case AArch64::RCWSWPSPL: {
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::LDR_ZA:
    case AArch64::STR_ZA: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 1, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::INSERT_MXIPZ_H_H:
    case AArch64::INSERT_MXIPZ_V_H: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1) << 3;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::INSERT_MXIPZ_H_S:
    case AArch64::INSERT_MXIPZ_V_S: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3) << 2;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::INSERT_MXIPZ_H_D:
    case AArch64::INSERT_MXIPZ_V_D: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 1;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      break;
    }
    case AArch64::INSERT_MXIPZ_H_Q:
    case AArch64::INSERT_MXIPZ_V_Q: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::INSERT_MXIPZ_H_B:
    case AArch64::INSERT_MXIPZ_V_B: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf);
      break;
    }
    case AArch64::PSEL_PPPRI_D: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 16;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 23;
      break;
    }
    case AArch64::PSEL_PPPRI_S: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 16;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 22;
      break;
    }
    case AArch64::PSEL_PPPRI_H: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 16;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x6) << 21;
      Value |= (op & 0x1) << 20;
      break;
    }
    case AArch64::PSEL_PPPRI_B: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 16;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 10;
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: Pd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0xc) << 20;
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_H:
    case AArch64::EXTRACT_ZPMXI_V_H: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 8;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_S:
    case AArch64::EXTRACT_ZPMXI_V_S: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 7;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 5;
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_D:
    case AArch64::EXTRACT_ZPMXI_V_D: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1) << 5;
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_Q:
    case AArch64::EXTRACT_ZPMXI_V_Q: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_B:
    case AArch64::EXTRACT_ZPMXI_V_B: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 4, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::BFMLAL_VG2_M2Z2Z_HtoS:
    case AArch64::BFMLSL_VG2_M2Z2Z_HtoS:
    case AArch64::FMLAL_VG2_M2Z2Z_BtoH:
    case AArch64::FMLAL_VG2_M2Z2Z_HtoS:
    case AArch64::FMLSL_VG2_M2Z2Z_HtoS:
    case AArch64::SMLAL_VG2_M2Z2Z_HtoS:
    case AArch64::SMLSL_VG2_M2Z2Z_HtoS:
    case AArch64::UMLAL_VG2_M2Z2Z_HtoS:
    case AArch64::UMLSL_VG2_M2Z2Z_HtoS: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zm
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 5, Fixups, STI);
      Value |= (op & 0xf) << 17;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::BFMLAL_VG4_M4Z4Z_HtoS:
    case AArch64::BFMLSL_VG4_M4Z4Z_HtoS:
    case AArch64::FMLAL_VG4_M4Z4Z_BtoH:
    case AArch64::FMLAL_VG4_M4Z4Z_HtoS:
    case AArch64::FMLSL_VG4_M4Z4Z_HtoS:
    case AArch64::SMLAL_VG4_M4Z4Z_HtoS:
    case AArch64::SMLSL_VG4_M4Z4Z_HtoS:
    case AArch64::UMLAL_VG4_M4Z4Z_HtoS:
    case AArch64::UMLSL_VG4_M4Z4Z_HtoS: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zm
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 5, Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::BFMLAL_VG2_M2ZZ_HtoS:
    case AArch64::BFMLAL_VG4_M4ZZ_HtoS:
    case AArch64::BFMLSL_VG2_M2ZZ_HtoS:
    case AArch64::BFMLSL_VG4_M4ZZ_HtoS:
    case AArch64::FMLAL_VG2_M2ZZ_BtoH:
    case AArch64::FMLAL_VG2_M2ZZ_HtoS:
    case AArch64::FMLAL_VG4_M4ZZ_BtoH:
    case AArch64::FMLAL_VG4_M4ZZ_HtoS:
    case AArch64::FMLSL_VG2_M2ZZ_HtoS:
    case AArch64::FMLSL_VG4_M4ZZ_HtoS:
    case AArch64::SMLAL_VG2_M2ZZ_HtoS:
    case AArch64::SMLAL_VG4_M4ZZ_HtoS:
    case AArch64::SMLSL_VG2_M2ZZ_HtoS:
    case AArch64::SMLSL_VG4_M4ZZ_HtoS:
    case AArch64::UMLAL_VG2_M2ZZ_HtoS:
    case AArch64::UMLAL_VG4_M4ZZ_HtoS:
    case AArch64::UMLSL_VG2_M2ZZ_HtoS:
    case AArch64::UMLSL_VG4_M4ZZ_HtoS: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::BFMLAL_MZZ_HtoS:
    case AArch64::BFMLSL_MZZ_HtoS:
    case AArch64::FMLAL_MZZ_HtoS:
    case AArch64::FMLAL_VG2_MZZ_BtoH:
    case AArch64::FMLSL_MZZ_HtoS:
    case AArch64::SMLAL_MZZ_HtoS:
    case AArch64::SMLSL_MZZ_HtoS:
    case AArch64::UMLAL_MZZ_HtoS:
    case AArch64::UMLSL_MZZ_HtoS: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::ZERO_MXI_VG2_4Z:
    case AArch64::ZERO_MXI_VG4_4Z: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      break;
    }
    case AArch64::ZERO_MXI_4Z:
    case AArch64::ZERO_MXI_VG2_2Z:
    case AArch64::ZERO_MXI_VG4_2Z: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::ZERO_MXI_2Z:
    case AArch64::ZERO_MXI_VG2_Z:
    case AArch64::ZERO_MXI_VG4_Z: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::ADD_VG2_M2Z_D:
    case AArch64::ADD_VG2_M2Z_S:
    case AArch64::BFADD_VG2_M2Z_H:
    case AArch64::BFSUB_VG2_M2Z_H:
    case AArch64::FADD_VG2_M2Z_D:
    case AArch64::FADD_VG2_M2Z_H:
    case AArch64::FADD_VG2_M2Z_S:
    case AArch64::FSUB_VG2_M2Z_D:
    case AArch64::FSUB_VG2_M2Z_H:
    case AArch64::FSUB_VG2_M2Z_S:
    case AArch64::SUB_VG2_M2Z_D:
    case AArch64::SUB_VG2_M2Z_S: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      // op: Zm
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      break;
    }
    case AArch64::ADD_VG4_M4Z_D:
    case AArch64::ADD_VG4_M4Z_S:
    case AArch64::BFADD_VG4_M4Z_H:
    case AArch64::BFSUB_VG4_M4Z_H:
    case AArch64::FADD_VG4_M4Z_D:
    case AArch64::FADD_VG4_M4Z_H:
    case AArch64::FADD_VG4_M4Z_S:
    case AArch64::FSUB_VG4_M4Z_D:
    case AArch64::FSUB_VG4_M4Z_H:
    case AArch64::FSUB_VG4_M4Z_S:
    case AArch64::SUB_VG4_M4Z_D:
    case AArch64::SUB_VG4_M4Z_S: {
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      // op: Zm
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      break;
    }
    case AArch64::RAX1:
    case AArch64::SM4ENCKEY:
    case AArch64::TBLv16i8Four:
    case AArch64::TBLv16i8One:
    case AArch64::TBLv16i8Three:
    case AArch64::TBLv16i8Two:
    case AArch64::TBLv8i8Four:
    case AArch64::TBLv8i8One:
    case AArch64::TBLv8i8Three:
    case AArch64::TBLv8i8Two: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::BCAX:
    case AArch64::EOR3:
    case AArch64::SM3SS1: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Va
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      break;
    }
    case AArch64::XAR: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3f) << 10;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::ADDQV_VPZ_B:
    case AArch64::ADDQV_VPZ_D:
    case AArch64::ADDQV_VPZ_H:
    case AArch64::ADDQV_VPZ_S:
    case AArch64::ANDQV_VPZ_B:
    case AArch64::ANDQV_VPZ_D:
    case AArch64::ANDQV_VPZ_H:
    case AArch64::ANDQV_VPZ_S:
    case AArch64::EORQV_VPZ_B:
    case AArch64::EORQV_VPZ_D:
    case AArch64::EORQV_VPZ_H:
    case AArch64::EORQV_VPZ_S:
    case AArch64::FADDQV_D:
    case AArch64::FADDQV_H:
    case AArch64::FADDQV_S:
    case AArch64::FMAXNMQV_D:
    case AArch64::FMAXNMQV_H:
    case AArch64::FMAXNMQV_S:
    case AArch64::FMAXQV_D:
    case AArch64::FMAXQV_H:
    case AArch64::FMAXQV_S:
    case AArch64::FMINNMQV_D:
    case AArch64::FMINNMQV_H:
    case AArch64::FMINNMQV_S:
    case AArch64::FMINQV_D:
    case AArch64::FMINQV_H:
    case AArch64::FMINQV_S:
    case AArch64::ORQV_VPZ_B:
    case AArch64::ORQV_VPZ_D:
    case AArch64::ORQV_VPZ_H:
    case AArch64::ORQV_VPZ_S:
    case AArch64::SMAXQV_VPZ_B:
    case AArch64::SMAXQV_VPZ_D:
    case AArch64::SMAXQV_VPZ_H:
    case AArch64::SMAXQV_VPZ_S:
    case AArch64::SMINQV_VPZ_B:
    case AArch64::SMINQV_VPZ_D:
    case AArch64::SMINQV_VPZ_H:
    case AArch64::SMINQV_VPZ_S:
    case AArch64::UMAXQV_VPZ_B:
    case AArch64::UMAXQV_VPZ_D:
    case AArch64::UMAXQV_VPZ_H:
    case AArch64::UMAXQV_VPZ_S:
    case AArch64::UMINQV_VPZ_B:
    case AArch64::UMINQV_VPZ_D:
    case AArch64::UMINQV_VPZ_H:
    case AArch64::UMINQV_VPZ_S: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::SHA512SU0:
    case AArch64::SM4E: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::SHA512H:
    case AArch64::SHA512H2:
    case AArch64::SHA512SU1:
    case AArch64::SM3PARTW1:
    case AArch64::SM3PARTW2:
    case AArch64::TBXv16i8Four:
    case AArch64::TBXv16i8One:
    case AArch64::TBXv16i8Three:
    case AArch64::TBXv16i8Two:
    case AArch64::TBXv8i8Four:
    case AArch64::TBXv8i8One:
    case AArch64::TBXv8i8Three:
    case AArch64::TBXv8i8Two: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SM3TT1A:
    case AArch64::SM3TT1B:
    case AArch64::SM3TT2A:
    case AArch64::SM3TT2B: {
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Vn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 12;
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::INSR_ZV_B:
    case AArch64::INSR_ZV_D:
    case AArch64::INSR_ZV_H:
    case AArch64::INSR_ZV_S: {
      // op: Vm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::LD1Fourv16b:
    case AArch64::LD1Fourv1d:
    case AArch64::LD1Fourv2d:
    case AArch64::LD1Fourv2s:
    case AArch64::LD1Fourv4h:
    case AArch64::LD1Fourv4s:
    case AArch64::LD1Fourv8b:
    case AArch64::LD1Fourv8h:
    case AArch64::LD1Onev16b:
    case AArch64::LD1Onev1d:
    case AArch64::LD1Onev2d:
    case AArch64::LD1Onev2s:
    case AArch64::LD1Onev4h:
    case AArch64::LD1Onev4s:
    case AArch64::LD1Onev8b:
    case AArch64::LD1Onev8h:
    case AArch64::LD1Rv16b:
    case AArch64::LD1Rv1d:
    case AArch64::LD1Rv2d:
    case AArch64::LD1Rv2s:
    case AArch64::LD1Rv4h:
    case AArch64::LD1Rv4s:
    case AArch64::LD1Rv8b:
    case AArch64::LD1Rv8h:
    case AArch64::LD1Threev16b:
    case AArch64::LD1Threev1d:
    case AArch64::LD1Threev2d:
    case AArch64::LD1Threev2s:
    case AArch64::LD1Threev4h:
    case AArch64::LD1Threev4s:
    case AArch64::LD1Threev8b:
    case AArch64::LD1Threev8h:
    case AArch64::LD1Twov16b:
    case AArch64::LD1Twov1d:
    case AArch64::LD1Twov2d:
    case AArch64::LD1Twov2s:
    case AArch64::LD1Twov4h:
    case AArch64::LD1Twov4s:
    case AArch64::LD1Twov8b:
    case AArch64::LD1Twov8h:
    case AArch64::LD2Rv16b:
    case AArch64::LD2Rv1d:
    case AArch64::LD2Rv2d:
    case AArch64::LD2Rv2s:
    case AArch64::LD2Rv4h:
    case AArch64::LD2Rv4s:
    case AArch64::LD2Rv8b:
    case AArch64::LD2Rv8h:
    case AArch64::LD2Twov16b:
    case AArch64::LD2Twov2d:
    case AArch64::LD2Twov2s:
    case AArch64::LD2Twov4h:
    case AArch64::LD2Twov4s:
    case AArch64::LD2Twov8b:
    case AArch64::LD2Twov8h:
    case AArch64::LD3Rv16b:
    case AArch64::LD3Rv1d:
    case AArch64::LD3Rv2d:
    case AArch64::LD3Rv2s:
    case AArch64::LD3Rv4h:
    case AArch64::LD3Rv4s:
    case AArch64::LD3Rv8b:
    case AArch64::LD3Rv8h:
    case AArch64::LD3Threev16b:
    case AArch64::LD3Threev2d:
    case AArch64::LD3Threev2s:
    case AArch64::LD3Threev4h:
    case AArch64::LD3Threev4s:
    case AArch64::LD3Threev8b:
    case AArch64::LD3Threev8h:
    case AArch64::LD4Fourv16b:
    case AArch64::LD4Fourv2d:
    case AArch64::LD4Fourv2s:
    case AArch64::LD4Fourv4h:
    case AArch64::LD4Fourv4s:
    case AArch64::LD4Fourv8b:
    case AArch64::LD4Fourv8h:
    case AArch64::LD4Rv16b:
    case AArch64::LD4Rv1d:
    case AArch64::LD4Rv2d:
    case AArch64::LD4Rv2s:
    case AArch64::LD4Rv4h:
    case AArch64::LD4Rv4s:
    case AArch64::LD4Rv8b:
    case AArch64::LD4Rv8h:
    case AArch64::ST1Fourv16b:
    case AArch64::ST1Fourv1d:
    case AArch64::ST1Fourv2d:
    case AArch64::ST1Fourv2s:
    case AArch64::ST1Fourv4h:
    case AArch64::ST1Fourv4s:
    case AArch64::ST1Fourv8b:
    case AArch64::ST1Fourv8h:
    case AArch64::ST1Onev16b:
    case AArch64::ST1Onev1d:
    case AArch64::ST1Onev2d:
    case AArch64::ST1Onev2s:
    case AArch64::ST1Onev4h:
    case AArch64::ST1Onev4s:
    case AArch64::ST1Onev8b:
    case AArch64::ST1Onev8h:
    case AArch64::ST1Threev16b:
    case AArch64::ST1Threev1d:
    case AArch64::ST1Threev2d:
    case AArch64::ST1Threev2s:
    case AArch64::ST1Threev4h:
    case AArch64::ST1Threev4s:
    case AArch64::ST1Threev8b:
    case AArch64::ST1Threev8h:
    case AArch64::ST1Twov16b:
    case AArch64::ST1Twov1d:
    case AArch64::ST1Twov2d:
    case AArch64::ST1Twov2s:
    case AArch64::ST1Twov4h:
    case AArch64::ST1Twov4s:
    case AArch64::ST1Twov8b:
    case AArch64::ST1Twov8h:
    case AArch64::ST2Twov16b:
    case AArch64::ST2Twov2d:
    case AArch64::ST2Twov2s:
    case AArch64::ST2Twov4h:
    case AArch64::ST2Twov4s:
    case AArch64::ST2Twov8b:
    case AArch64::ST2Twov8h:
    case AArch64::ST3Threev16b:
    case AArch64::ST3Threev2d:
    case AArch64::ST3Threev2s:
    case AArch64::ST3Threev4h:
    case AArch64::ST3Threev4s:
    case AArch64::ST3Threev8b:
    case AArch64::ST3Threev8h:
    case AArch64::ST4Fourv16b:
    case AArch64::ST4Fourv2d:
    case AArch64::ST4Fourv2s:
    case AArch64::ST4Fourv4h:
    case AArch64::ST4Fourv4s:
    case AArch64::ST4Fourv8b:
    case AArch64::ST4Fourv8h: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::STL1: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Q
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1) << 30;
      break;
    }
    case AArch64::ST1i64:
    case AArch64::ST2i64:
    case AArch64::ST3i64:
    case AArch64::ST4i64: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1) << 30;
      break;
    }
    case AArch64::ST1i32:
    case AArch64::ST2i32:
    case AArch64::ST3i32:
    case AArch64::ST4i32: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x2) << 29;
      Value |= (op & 0x1) << 12;
      break;
    }
    case AArch64::ST1i16:
    case AArch64::ST2i16:
    case AArch64::ST3i16:
    case AArch64::ST4i16: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x4) << 28;
      Value |= (op & 0x3) << 11;
      break;
    }
    case AArch64::ST1i8:
    case AArch64::ST2i8:
    case AArch64::ST3i8:
    case AArch64::ST4i8: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x8) << 27;
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::LD1Fourv16b_POST:
    case AArch64::LD1Fourv1d_POST:
    case AArch64::LD1Fourv2d_POST:
    case AArch64::LD1Fourv2s_POST:
    case AArch64::LD1Fourv4h_POST:
    case AArch64::LD1Fourv4s_POST:
    case AArch64::LD1Fourv8b_POST:
    case AArch64::LD1Fourv8h_POST:
    case AArch64::LD1Onev16b_POST:
    case AArch64::LD1Onev1d_POST:
    case AArch64::LD1Onev2d_POST:
    case AArch64::LD1Onev2s_POST:
    case AArch64::LD1Onev4h_POST:
    case AArch64::LD1Onev4s_POST:
    case AArch64::LD1Onev8b_POST:
    case AArch64::LD1Onev8h_POST:
    case AArch64::LD1Rv16b_POST:
    case AArch64::LD1Rv1d_POST:
    case AArch64::LD1Rv2d_POST:
    case AArch64::LD1Rv2s_POST:
    case AArch64::LD1Rv4h_POST:
    case AArch64::LD1Rv4s_POST:
    case AArch64::LD1Rv8b_POST:
    case AArch64::LD1Rv8h_POST:
    case AArch64::LD1Threev16b_POST:
    case AArch64::LD1Threev1d_POST:
    case AArch64::LD1Threev2d_POST:
    case AArch64::LD1Threev2s_POST:
    case AArch64::LD1Threev4h_POST:
    case AArch64::LD1Threev4s_POST:
    case AArch64::LD1Threev8b_POST:
    case AArch64::LD1Threev8h_POST:
    case AArch64::LD1Twov16b_POST:
    case AArch64::LD1Twov1d_POST:
    case AArch64::LD1Twov2d_POST:
    case AArch64::LD1Twov2s_POST:
    case AArch64::LD1Twov4h_POST:
    case AArch64::LD1Twov4s_POST:
    case AArch64::LD1Twov8b_POST:
    case AArch64::LD1Twov8h_POST:
    case AArch64::LD2Rv16b_POST:
    case AArch64::LD2Rv1d_POST:
    case AArch64::LD2Rv2d_POST:
    case AArch64::LD2Rv2s_POST:
    case AArch64::LD2Rv4h_POST:
    case AArch64::LD2Rv4s_POST:
    case AArch64::LD2Rv8b_POST:
    case AArch64::LD2Rv8h_POST:
    case AArch64::LD2Twov16b_POST:
    case AArch64::LD2Twov2d_POST:
    case AArch64::LD2Twov2s_POST:
    case AArch64::LD2Twov4h_POST:
    case AArch64::LD2Twov4s_POST:
    case AArch64::LD2Twov8b_POST:
    case AArch64::LD2Twov8h_POST:
    case AArch64::LD3Rv16b_POST:
    case AArch64::LD3Rv1d_POST:
    case AArch64::LD3Rv2d_POST:
    case AArch64::LD3Rv2s_POST:
    case AArch64::LD3Rv4h_POST:
    case AArch64::LD3Rv4s_POST:
    case AArch64::LD3Rv8b_POST:
    case AArch64::LD3Rv8h_POST:
    case AArch64::LD3Threev16b_POST:
    case AArch64::LD3Threev2d_POST:
    case AArch64::LD3Threev2s_POST:
    case AArch64::LD3Threev4h_POST:
    case AArch64::LD3Threev4s_POST:
    case AArch64::LD3Threev8b_POST:
    case AArch64::LD3Threev8h_POST:
    case AArch64::LD4Fourv16b_POST:
    case AArch64::LD4Fourv2d_POST:
    case AArch64::LD4Fourv2s_POST:
    case AArch64::LD4Fourv4h_POST:
    case AArch64::LD4Fourv4s_POST:
    case AArch64::LD4Fourv8b_POST:
    case AArch64::LD4Fourv8h_POST:
    case AArch64::LD4Rv16b_POST:
    case AArch64::LD4Rv1d_POST:
    case AArch64::LD4Rv2d_POST:
    case AArch64::LD4Rv2s_POST:
    case AArch64::LD4Rv4h_POST:
    case AArch64::LD4Rv4s_POST:
    case AArch64::LD4Rv8b_POST:
    case AArch64::LD4Rv8h_POST:
    case AArch64::ST1Fourv16b_POST:
    case AArch64::ST1Fourv1d_POST:
    case AArch64::ST1Fourv2d_POST:
    case AArch64::ST1Fourv2s_POST:
    case AArch64::ST1Fourv4h_POST:
    case AArch64::ST1Fourv4s_POST:
    case AArch64::ST1Fourv8b_POST:
    case AArch64::ST1Fourv8h_POST:
    case AArch64::ST1Onev16b_POST:
    case AArch64::ST1Onev1d_POST:
    case AArch64::ST1Onev2d_POST:
    case AArch64::ST1Onev2s_POST:
    case AArch64::ST1Onev4h_POST:
    case AArch64::ST1Onev4s_POST:
    case AArch64::ST1Onev8b_POST:
    case AArch64::ST1Onev8h_POST:
    case AArch64::ST1Threev16b_POST:
    case AArch64::ST1Threev1d_POST:
    case AArch64::ST1Threev2d_POST:
    case AArch64::ST1Threev2s_POST:
    case AArch64::ST1Threev4h_POST:
    case AArch64::ST1Threev4s_POST:
    case AArch64::ST1Threev8b_POST:
    case AArch64::ST1Threev8h_POST:
    case AArch64::ST1Twov16b_POST:
    case AArch64::ST1Twov1d_POST:
    case AArch64::ST1Twov2d_POST:
    case AArch64::ST1Twov2s_POST:
    case AArch64::ST1Twov4h_POST:
    case AArch64::ST1Twov4s_POST:
    case AArch64::ST1Twov8b_POST:
    case AArch64::ST1Twov8h_POST:
    case AArch64::ST2Twov16b_POST:
    case AArch64::ST2Twov2d_POST:
    case AArch64::ST2Twov2s_POST:
    case AArch64::ST2Twov4h_POST:
    case AArch64::ST2Twov4s_POST:
    case AArch64::ST2Twov8b_POST:
    case AArch64::ST2Twov8h_POST:
    case AArch64::ST3Threev16b_POST:
    case AArch64::ST3Threev2d_POST:
    case AArch64::ST3Threev2s_POST:
    case AArch64::ST3Threev4h_POST:
    case AArch64::ST3Threev4s_POST:
    case AArch64::ST3Threev8b_POST:
    case AArch64::ST3Threev8h_POST:
    case AArch64::ST4Fourv16b_POST:
    case AArch64::ST4Fourv2d_POST:
    case AArch64::ST4Fourv2s_POST:
    case AArch64::ST4Fourv4h_POST:
    case AArch64::ST4Fourv4s_POST:
    case AArch64::ST4Fourv8b_POST:
    case AArch64::ST4Fourv8h_POST: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Xm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LDAP1: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Q
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 30;
      break;
    }
    case AArch64::LD1i64:
    case AArch64::LD2i64:
    case AArch64::LD3i64:
    case AArch64::LD4i64: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 30;
      break;
    }
    case AArch64::ST1i64_POST:
    case AArch64::ST2i64_POST:
    case AArch64::ST3i64_POST:
    case AArch64::ST4i64_POST: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 30;
      // op: Xm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LD1i32:
    case AArch64::LD2i32:
    case AArch64::LD3i32:
    case AArch64::LD4i32: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x2) << 29;
      Value |= (op & 0x1) << 12;
      break;
    }
    case AArch64::ST1i32_POST:
    case AArch64::ST2i32_POST:
    case AArch64::ST3i32_POST:
    case AArch64::ST4i32_POST: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x2) << 29;
      Value |= (op & 0x1) << 12;
      // op: Xm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LD1i16:
    case AArch64::LD2i16:
    case AArch64::LD3i16:
    case AArch64::LD4i16: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x4) << 28;
      Value |= (op & 0x3) << 11;
      break;
    }
    case AArch64::ST1i16_POST:
    case AArch64::ST2i16_POST:
    case AArch64::ST3i16_POST:
    case AArch64::ST4i16_POST: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x4) << 28;
      Value |= (op & 0x3) << 11;
      // op: Xm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LD1i8:
    case AArch64::LD2i8:
    case AArch64::LD3i8:
    case AArch64::LD4i8: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x8) << 27;
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::ST1i8_POST:
    case AArch64::ST2i8_POST:
    case AArch64::ST3i8_POST:
    case AArch64::ST4i8_POST: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x8) << 27;
      Value |= (op & 0x7) << 10;
      // op: Xm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LD1i64_POST:
    case AArch64::LD2i64_POST:
    case AArch64::LD3i64_POST:
    case AArch64::LD4i64_POST: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 30;
      // op: Xm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LD1i32_POST:
    case AArch64::LD2i32_POST:
    case AArch64::LD3i32_POST:
    case AArch64::LD4i32_POST: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x2) << 29;
      Value |= (op & 0x1) << 12;
      // op: Xm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LD1i16_POST:
    case AArch64::LD2i16_POST:
    case AArch64::LD3i16_POST:
    case AArch64::LD4i16_POST: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x4) << 28;
      Value |= (op & 0x3) << 11;
      // op: Xm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LD1i8_POST:
    case AArch64::LD2i8_POST:
    case AArch64::LD3i8_POST:
    case AArch64::LD4i8_POST: {
      // op: Vt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x8) << 27;
      Value |= (op & 0x7) << 10;
      // op: Xm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::STLTXRW:
    case AArch64::STLTXRX:
    case AArch64::STLXRB:
    case AArch64::STLXRH:
    case AArch64::STLXRW:
    case AArch64::STLXRX:
    case AArch64::STXRB:
    case AArch64::STXRH:
    case AArch64::STXRW:
    case AArch64::STXRX: {
      // op: Ws
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      Value = fixLoadStoreExclusive<1,0>(MI, Value, STI);
      break;
    }
    case AArch64::STLXPW:
    case AArch64::STLXPX:
    case AArch64::STXPW:
    case AArch64::STXPX: {
      // op: Ws
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rt2
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::TCHANGEBrr:
    case AArch64::TCHANGEFrr: {
      // op: Xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Xn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: nb
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 17;
      break;
    }
    case AArch64::TCHANGEBri:
    case AArch64::TCHANGEFri: {
      // op: Xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7f) << 5;
      // op: nb
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 17;
      break;
    }
    case AArch64::ADR:
    case AArch64::ADRP: {
      // op: Xd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: label
      op = getAdrLabelOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0x3) << 29;
      Value |= (op & 0x1ffffc) << 3;
      break;
    }
    case AArch64::APAS: {
      // op: Xt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::BFMOP4A_M2Z2Z_H:
    case AArch64::BFMOP4S_M2Z2Z_H:
    case AArch64::FMOP4A_M2Z2Z_BtoH:
    case AArch64::FMOP4A_M2Z2Z_H:
    case AArch64::FMOP4S_M2Z2Z_H: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2, 16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::BFMOP4A_M2ZZ_H:
    case AArch64::BFMOP4S_M2ZZ_H:
    case AArch64::FMOP4A_M2ZZ_BtoH:
    case AArch64::FMOP4A_M2ZZ_H:
    case AArch64::FMOP4S_M2ZZ_H: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2,16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::BFTMOPA_M2ZZZI_HtoH:
    case AArch64::FTMOPA_M2ZZZI_BtoH:
    case AArch64::FTMOPA_M2ZZZI_HtoH: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zk
      op = EncodeZK(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 4;
      break;
    }
    case AArch64::BFMOP4A_MZ2Z_H:
    case AArch64::BFMOP4S_MZ2Z_H:
    case AArch64::FMOP4A_MZ2Z_BtoH:
    case AArch64::FMOP4A_MZ2Z_H:
    case AArch64::FMOP4S_MZ2Z_H: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1);
      // op: Zn
      op = EncodeRegMul_MinMax<2,0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2, 16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::BFMOP4A_MZZ_H:
    case AArch64::BFMOP4S_MZZ_H:
    case AArch64::FMOP4A_MZZ_BtoH:
    case AArch64::FMOP4A_MZZ_H:
    case AArch64::FMOP4S_MZZ_H: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1);
      // op: Zn
      op = EncodeRegMul_MinMax<2,0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2,16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::BFMOP4A_M2Z2Z_S:
    case AArch64::BFMOP4S_M2Z2Z_S:
    case AArch64::FMOP4A_M2Z2Z_BtoS:
    case AArch64::FMOP4A_M2Z2Z_HtoS:
    case AArch64::FMOP4A_M2Z2Z_S:
    case AArch64::FMOP4S_M2Z2Z_HtoS:
    case AArch64::FMOP4S_M2Z2Z_S:
    case AArch64::SMOP4A_M2Z2Z_BToS:
    case AArch64::SMOP4A_M2Z2Z_HToS:
    case AArch64::SMOP4S_M2Z2Z_BToS:
    case AArch64::SMOP4S_M2Z2Z_HToS:
    case AArch64::SUMOP4A_M2Z2Z_BToS:
    case AArch64::SUMOP4S_M2Z2Z_BToS:
    case AArch64::UMOP4A_M2Z2Z_BToS:
    case AArch64::UMOP4A_M2Z2Z_HToS:
    case AArch64::UMOP4S_M2Z2Z_BToS:
    case AArch64::UMOP4S_M2Z2Z_HToS:
    case AArch64::USMOP4A_M2Z2Z_BToS:
    case AArch64::USMOP4S_M2Z2Z_BToS: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2, 16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::BFMOP4A_M2ZZ_S:
    case AArch64::BFMOP4S_M2ZZ_S:
    case AArch64::FMOP4A_M2ZZ_BtoS:
    case AArch64::FMOP4A_M2ZZ_HtoS:
    case AArch64::FMOP4A_M2ZZ_S:
    case AArch64::FMOP4S_M2ZZ_HtoS:
    case AArch64::FMOP4S_M2ZZ_S:
    case AArch64::SMOP4A_M2ZZ_BToS:
    case AArch64::SMOP4A_M2ZZ_HToS:
    case AArch64::SMOP4S_M2ZZ_BToS:
    case AArch64::SMOP4S_M2ZZ_HToS:
    case AArch64::SUMOP4A_M2ZZ_BToS:
    case AArch64::SUMOP4S_M2ZZ_BToS:
    case AArch64::UMOP4A_M2ZZ_BToS:
    case AArch64::UMOP4A_M2ZZ_HToS:
    case AArch64::UMOP4S_M2ZZ_BToS:
    case AArch64::UMOP4S_M2ZZ_HToS:
    case AArch64::USMOP4A_M2ZZ_BToS:
    case AArch64::USMOP4S_M2ZZ_BToS: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2,16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::BFTMOPA_M2ZZZI_HtoS:
    case AArch64::FTMOPA_M2ZZZI_BtoS:
    case AArch64::FTMOPA_M2ZZZI_HtoS:
    case AArch64::FTMOPA_M2ZZZI_StoS:
    case AArch64::STMOPA_M2ZZZI_BtoS:
    case AArch64::STMOPA_M2ZZZI_HtoS:
    case AArch64::SUTMOPA_M2ZZZI_BtoS:
    case AArch64::USTMOPA_M2ZZZI_BtoS:
    case AArch64::UTMOPA_M2ZZZI_BtoS:
    case AArch64::UTMOPA_M2ZZZI_HtoS: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zk
      op = EncodeZK(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 4;
      break;
    }
    case AArch64::BFMOP4A_MZ2Z_S:
    case AArch64::BFMOP4S_MZ2Z_S:
    case AArch64::FMOP4A_MZ2Z_BtoS:
    case AArch64::FMOP4A_MZ2Z_HtoS:
    case AArch64::FMOP4A_MZ2Z_S:
    case AArch64::FMOP4S_MZ2Z_HtoS:
    case AArch64::FMOP4S_MZ2Z_S:
    case AArch64::SMOP4A_MZ2Z_BToS:
    case AArch64::SMOP4A_MZ2Z_HToS:
    case AArch64::SMOP4S_MZ2Z_BToS:
    case AArch64::SMOP4S_MZ2Z_HToS:
    case AArch64::SUMOP4A_MZ2Z_BToS:
    case AArch64::SUMOP4S_MZ2Z_BToS:
    case AArch64::UMOP4A_MZ2Z_BToS:
    case AArch64::UMOP4A_MZ2Z_HToS:
    case AArch64::UMOP4S_MZ2Z_BToS:
    case AArch64::UMOP4S_MZ2Z_HToS:
    case AArch64::USMOP4A_MZ2Z_BToS:
    case AArch64::USMOP4S_MZ2Z_BToS: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3);
      // op: Zn
      op = EncodeRegMul_MinMax<2,0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2, 16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::BFMOP4A_MZZ_S:
    case AArch64::BFMOP4S_MZZ_S:
    case AArch64::FMOP4A_MZZ_BtoS:
    case AArch64::FMOP4A_MZZ_HtoS:
    case AArch64::FMOP4A_MZZ_S:
    case AArch64::FMOP4S_MZZ_HtoS:
    case AArch64::FMOP4S_MZZ_S:
    case AArch64::SMOP4A_MZZ_BToS:
    case AArch64::SMOP4A_MZZ_HToS:
    case AArch64::SMOP4S_MZZ_BToS:
    case AArch64::SMOP4S_MZZ_HToS:
    case AArch64::SUMOP4A_MZZ_BToS:
    case AArch64::SUMOP4S_MZZ_BToS:
    case AArch64::UMOP4A_MZZ_BToS:
    case AArch64::UMOP4A_MZZ_HToS:
    case AArch64::UMOP4S_MZZ_BToS:
    case AArch64::UMOP4S_MZZ_HToS:
    case AArch64::USMOP4A_MZZ_BToS:
    case AArch64::USMOP4S_MZZ_BToS: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3);
      // op: Zn
      op = EncodeRegMul_MinMax<2,0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2,16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::FMOP4A_M2Z2Z_D:
    case AArch64::FMOP4S_M2Z2Z_D:
    case AArch64::SMOP4A_M2Z2Z_HtoD:
    case AArch64::SMOP4S_M2Z2Z_HtoD:
    case AArch64::SUMOP4A_M2Z2Z_HtoD:
    case AArch64::SUMOP4S_M2Z2Z_HtoD:
    case AArch64::UMOP4A_M2Z2Z_HtoD:
    case AArch64::UMOP4S_M2Z2Z_HtoD:
    case AArch64::USMOP4A_M2Z2Z_HtoD:
    case AArch64::USMOP4S_M2Z2Z_HtoD: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2, 16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::FMOP4A_M2ZZ_D:
    case AArch64::FMOP4S_M2ZZ_D:
    case AArch64::SMOP4A_M2ZZ_HtoD:
    case AArch64::SMOP4S_M2ZZ_HtoD:
    case AArch64::SUMOP4A_M2ZZ_HtoD:
    case AArch64::SUMOP4S_M2ZZ_HtoD:
    case AArch64::UMOP4A_M2ZZ_HtoD:
    case AArch64::UMOP4S_M2ZZ_HtoD:
    case AArch64::USMOP4A_M2ZZ_HtoD:
    case AArch64::USMOP4S_M2ZZ_HtoD: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2,16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::FMOP4A_MZ2Z_D:
    case AArch64::FMOP4S_MZ2Z_D:
    case AArch64::SMOP4A_MZ2Z_HtoD:
    case AArch64::SMOP4S_MZ2Z_HtoD:
    case AArch64::SUMOP4A_MZ2Z_HtoD:
    case AArch64::SUMOP4S_MZ2Z_HtoD:
    case AArch64::UMOP4A_MZ2Z_HtoD:
    case AArch64::UMOP4S_MZ2Z_HtoD:
    case AArch64::USMOP4A_MZ2Z_HtoD:
    case AArch64::USMOP4S_MZ2Z_HtoD: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      // op: Zn
      op = EncodeRegMul_MinMax<2,0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2, 16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::FMOP4A_MZZ_D:
    case AArch64::FMOP4S_MZZ_D:
    case AArch64::SMOP4A_MZZ_HtoD:
    case AArch64::SMOP4S_MZZ_HtoD:
    case AArch64::SUMOP4A_MZZ_HtoD:
    case AArch64::SUMOP4S_MZZ_HtoD:
    case AArch64::UMOP4A_MZZ_HtoD:
    case AArch64::UMOP4S_MZZ_HtoD:
    case AArch64::USMOP4A_MZZ_HtoD:
    case AArch64::USMOP4S_MZZ_HtoD: {
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      // op: Zn
      op = EncodeRegMul_MinMax<2,0, 14>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2,16, 30>(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 17;
      break;
    }
    case AArch64::MOVA_2ZMXI_H_H:
    case AArch64::MOVA_2ZMXI_V_H: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1) << 7;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 5;
      break;
    }
    case AArch64::MOVA_2ZMXI_H_S:
    case AArch64::MOVA_2ZMXI_V_S: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 5;
      break;
    }
    case AArch64::MOVA_2ZMXI_H_D:
    case AArch64::MOVA_2ZMXI_V_D: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::MOVA_2ZMXI_H_B:
    case AArch64::MOVA_2ZMXI_V_B: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::MOVAZ_2ZMI_H_H:
    case AArch64::MOVAZ_2ZMI_V_H: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 7;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 5;
      break;
    }
    case AArch64::MOVAZ_2ZMI_H_S:
    case AArch64::MOVAZ_2ZMI_V_S: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 5;
      break;
    }
    case AArch64::MOVAZ_2ZMI_H_D:
    case AArch64::MOVAZ_2ZMI_V_D: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::MOVAZ_2ZMI_H_B:
    case AArch64::MOVAZ_2ZMI_V_B: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::UZP_VG2_2ZZZ_B:
    case AArch64::UZP_VG2_2ZZZ_D:
    case AArch64::UZP_VG2_2ZZZ_H:
    case AArch64::UZP_VG2_2ZZZ_Q:
    case AArch64::UZP_VG2_2ZZZ_S:
    case AArch64::ZIP_VG2_2ZZZ_B:
    case AArch64::ZIP_VG2_2ZZZ_D:
    case AArch64::ZIP_VG2_2ZZZ_H:
    case AArch64::ZIP_VG2_2ZZZ_Q:
    case AArch64::ZIP_VG2_2ZZZ_S: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::BFMUL_2Z2Z:
    case AArch64::FMUL_2Z2Z_D:
    case AArch64::FMUL_2Z2Z_H:
    case AArch64::FMUL_2Z2Z_S: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zm
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 17;
      break;
    }
    case AArch64::BFMUL_2ZZ:
    case AArch64::FMUL_2ZZ_D:
    case AArch64::FMUL_2ZZ_H:
    case AArch64::FMUL_2ZZ_S: {
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 17;
      break;
    }
    case AArch64::MOVA_4ZMXI_H_H:
    case AArch64::MOVA_4ZMXI_V_H: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 5;
      break;
    }
    case AArch64::MOVA_4ZMXI_H_S:
    case AArch64::MOVA_4ZMXI_V_S: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 5;
      break;
    }
    case AArch64::MOVA_4ZMXI_H_D:
    case AArch64::MOVA_4ZMXI_V_D: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::MOVA_4ZMXI_H_B:
    case AArch64::MOVA_4ZMXI_V_B: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 5;
      break;
    }
    case AArch64::MOVAZ_4ZMI_H_H:
    case AArch64::MOVAZ_4ZMI_V_H: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 5;
      break;
    }
    case AArch64::MOVAZ_4ZMI_H_S:
    case AArch64::MOVAZ_4ZMI_V_S: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 5;
      break;
    }
    case AArch64::MOVAZ_4ZMI_H_D:
    case AArch64::MOVAZ_4ZMI_V_D: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: ZAn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::MOVAZ_4ZMI_H_B:
    case AArch64::MOVAZ_4ZMI_V_B: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rs
      op = encodeMatrixIndexGPR32<AArch64::W12>(MI, 3, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 5;
      break;
    }
    case AArch64::BFMUL_4Z4Z:
    case AArch64::FMUL_4Z4Z_D:
    case AArch64::FMUL_4Z4Z_H:
    case AArch64::FMUL_4Z4Z_S: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: Zm
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 18;
      break;
    }
    case AArch64::BFMUL_4ZZ:
    case AArch64::FMUL_4ZZ_D:
    case AArch64::FMUL_4ZZ_H:
    case AArch64::FMUL_4ZZ_S: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 17;
      break;
    }
    case AArch64::LUTI6_4Z2Z2ZI: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: i1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 22;
      break;
    }
    case AArch64::LUTI6_4ZT3Z: {
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 7;
      break;
    }
    case AArch64::LUTI6_S_4Z2Z2ZI: {
      // op: Zd
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x4) << 2;
      Value |= (op & 0x3);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: i1
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 22;
      break;
    }
    case AArch64::LUTI6_S_4ZT3Z: {
      // op: Zd
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x4) << 2;
      Value |= (op & 0x3);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 7;
      break;
    }
    case AArch64::RBIT_ZPzZ_B:
    case AArch64::RBIT_ZPzZ_D:
    case AArch64::RBIT_ZPzZ_H:
    case AArch64::RBIT_ZPzZ_S:
    case AArch64::REVB_ZPzZ_D:
    case AArch64::REVB_ZPzZ_H:
    case AArch64::REVB_ZPzZ_S:
    case AArch64::REVD_ZPzZ:
    case AArch64::REVH_ZPzZ_D:
    case AArch64::REVH_ZPzZ_S:
    case AArch64::REVW_ZPzZ_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::CPY_ZPzI_B:
    case AArch64::CPY_ZPzI_D:
    case AArch64::CPY_ZPzI_H:
    case AArch64::CPY_ZPzI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: imm
      op = getImm8OptLsl(MI, 2, Fixups, STI);
      Value |= (op & 0x1ff) << 5;
      break;
    }
    case AArch64::RBIT_ZPmZ_B:
    case AArch64::RBIT_ZPmZ_D:
    case AArch64::RBIT_ZPmZ_H:
    case AArch64::RBIT_ZPmZ_S:
    case AArch64::REVB_ZPmZ_D:
    case AArch64::REVB_ZPmZ_H:
    case AArch64::REVB_ZPmZ_S:
    case AArch64::REVD_ZPmZ:
    case AArch64::REVH_ZPmZ_D:
    case AArch64::REVH_ZPmZ_S:
    case AArch64::REVW_ZPmZ_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::CPY_ZPmI_B:
    case AArch64::CPY_ZPmI_D:
    case AArch64::CPY_ZPmI_H:
    case AArch64::CPY_ZPmI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: imm
      op = getImm8OptLsl(MI, 3, Fixups, STI);
      Value |= (op & 0x1ff) << 5;
      break;
    }
    case AArch64::PMOV_ZIP_B: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 5;
      break;
    }
    case AArch64::PMOV_ZIP_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 17;
      break;
    }
    case AArch64::PMOV_ZIP_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 17;
      break;
    }
    case AArch64::PMOV_ZIP_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x4) << 20;
      Value |= (op & 0x3) << 17;
      break;
    }
    case AArch64::INDEX_RR_B:
    case AArch64::INDEX_RR_D:
    case AArch64::INDEX_RR_H:
    case AArch64::INDEX_RR_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::ADDQP_ZZZ_B:
    case AArch64::ADDQP_ZZZ_D:
    case AArch64::ADDQP_ZZZ_H:
    case AArch64::ADDQP_ZZZ_S:
    case AArch64::ADDSUBP_ZZZ_B:
    case AArch64::ADDSUBP_ZZZ_D:
    case AArch64::ADDSUBP_ZZZ_H:
    case AArch64::ADDSUBP_ZZZ_S:
    case AArch64::ADD_ZZZ_B:
    case AArch64::ADD_ZZZ_CPA:
    case AArch64::ADD_ZZZ_D:
    case AArch64::ADD_ZZZ_H:
    case AArch64::ADD_ZZZ_S:
    case AArch64::AND_ZZZ:
    case AArch64::ASR_WIDE_ZZZ_B:
    case AArch64::ASR_WIDE_ZZZ_H:
    case AArch64::ASR_WIDE_ZZZ_S:
    case AArch64::BFADD_ZZZ:
    case AArch64::BFMUL_ZZZ:
    case AArch64::BFSUB_ZZZ:
    case AArch64::BIC_ZZZ:
    case AArch64::EOR_ZZZ:
    case AArch64::FADD_ZZZ_D:
    case AArch64::FADD_ZZZ_H:
    case AArch64::FADD_ZZZ_S:
    case AArch64::FMUL_ZZZ_D:
    case AArch64::FMUL_ZZZ_H:
    case AArch64::FMUL_ZZZ_S:
    case AArch64::FRECPS_ZZZ_D:
    case AArch64::FRECPS_ZZZ_H:
    case AArch64::FRECPS_ZZZ_S:
    case AArch64::FRSQRTS_ZZZ_D:
    case AArch64::FRSQRTS_ZZZ_H:
    case AArch64::FRSQRTS_ZZZ_S:
    case AArch64::FSUB_ZZZ_D:
    case AArch64::FSUB_ZZZ_H:
    case AArch64::FSUB_ZZZ_S:
    case AArch64::FTSMUL_ZZZ_D:
    case AArch64::FTSMUL_ZZZ_H:
    case AArch64::FTSMUL_ZZZ_S:
    case AArch64::FTSSEL_ZZZ_D:
    case AArch64::FTSSEL_ZZZ_H:
    case AArch64::FTSSEL_ZZZ_S:
    case AArch64::LSL_WIDE_ZZZ_B:
    case AArch64::LSL_WIDE_ZZZ_H:
    case AArch64::LSL_WIDE_ZZZ_S:
    case AArch64::LSR_WIDE_ZZZ_B:
    case AArch64::LSR_WIDE_ZZZ_H:
    case AArch64::LSR_WIDE_ZZZ_S:
    case AArch64::MUL_ZZZ_B:
    case AArch64::MUL_ZZZ_D:
    case AArch64::MUL_ZZZ_H:
    case AArch64::MUL_ZZZ_S:
    case AArch64::ORR_ZZZ:
    case AArch64::PMUL_ZZZ_B:
    case AArch64::SMULH_ZZZ_B:
    case AArch64::SMULH_ZZZ_D:
    case AArch64::SMULH_ZZZ_H:
    case AArch64::SMULH_ZZZ_S:
    case AArch64::SQADD_ZZZ_B:
    case AArch64::SQADD_ZZZ_D:
    case AArch64::SQADD_ZZZ_H:
    case AArch64::SQADD_ZZZ_S:
    case AArch64::SQDMULH_ZZZ_B:
    case AArch64::SQDMULH_ZZZ_D:
    case AArch64::SQDMULH_ZZZ_H:
    case AArch64::SQDMULH_ZZZ_S:
    case AArch64::SQRDMULH_ZZZ_B:
    case AArch64::SQRDMULH_ZZZ_D:
    case AArch64::SQRDMULH_ZZZ_H:
    case AArch64::SQRDMULH_ZZZ_S:
    case AArch64::SQSUB_ZZZ_B:
    case AArch64::SQSUB_ZZZ_D:
    case AArch64::SQSUB_ZZZ_H:
    case AArch64::SQSUB_ZZZ_S:
    case AArch64::SUB_ZZZ_B:
    case AArch64::SUB_ZZZ_CPA:
    case AArch64::SUB_ZZZ_D:
    case AArch64::SUB_ZZZ_H:
    case AArch64::SUB_ZZZ_S:
    case AArch64::TBL_ZZZZ_B:
    case AArch64::TBL_ZZZZ_D:
    case AArch64::TBL_ZZZZ_H:
    case AArch64::TBL_ZZZZ_S:
    case AArch64::TBL_ZZZ_B:
    case AArch64::TBL_ZZZ_D:
    case AArch64::TBL_ZZZ_H:
    case AArch64::TBL_ZZZ_S:
    case AArch64::TRN1_ZZZ_B:
    case AArch64::TRN1_ZZZ_D:
    case AArch64::TRN1_ZZZ_H:
    case AArch64::TRN1_ZZZ_Q:
    case AArch64::TRN1_ZZZ_S:
    case AArch64::TRN2_ZZZ_B:
    case AArch64::TRN2_ZZZ_D:
    case AArch64::TRN2_ZZZ_H:
    case AArch64::TRN2_ZZZ_Q:
    case AArch64::TRN2_ZZZ_S:
    case AArch64::UMULH_ZZZ_B:
    case AArch64::UMULH_ZZZ_D:
    case AArch64::UMULH_ZZZ_H:
    case AArch64::UMULH_ZZZ_S:
    case AArch64::UQADD_ZZZ_B:
    case AArch64::UQADD_ZZZ_D:
    case AArch64::UQADD_ZZZ_H:
    case AArch64::UQADD_ZZZ_S:
    case AArch64::UQSUB_ZZZ_B:
    case AArch64::UQSUB_ZZZ_D:
    case AArch64::UQSUB_ZZZ_H:
    case AArch64::UQSUB_ZZZ_S:
    case AArch64::UZP1_ZZZ_B:
    case AArch64::UZP1_ZZZ_D:
    case AArch64::UZP1_ZZZ_H:
    case AArch64::UZP1_ZZZ_Q:
    case AArch64::UZP1_ZZZ_S:
    case AArch64::UZP2_ZZZ_B:
    case AArch64::UZP2_ZZZ_D:
    case AArch64::UZP2_ZZZ_H:
    case AArch64::UZP2_ZZZ_Q:
    case AArch64::UZP2_ZZZ_S:
    case AArch64::ZIP1_ZZZ_B:
    case AArch64::ZIP1_ZZZ_D:
    case AArch64::ZIP1_ZZZ_H:
    case AArch64::ZIP1_ZZZ_Q:
    case AArch64::ZIP1_ZZZ_S:
    case AArch64::ZIP2_ZZZ_B:
    case AArch64::ZIP2_ZZZ_D:
    case AArch64::ZIP2_ZZZ_H:
    case AArch64::ZIP2_ZZZ_Q:
    case AArch64::ZIP2_ZZZ_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::TBXQ_ZZZ_B:
    case AArch64::TBXQ_ZZZ_D:
    case AArch64::TBXQ_ZZZ_H:
    case AArch64::TBXQ_ZZZ_S:
    case AArch64::TBX_ZZZ_B:
    case AArch64::TBX_ZZZ_D:
    case AArch64::TBX_ZZZ_H:
    case AArch64::TBX_ZZZ_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::BFCVTN_Z2Z_HtoB:
    case AArch64::FCVTNB_Z2Z_StoB:
    case AArch64::FCVTN_Z2Z_HtoB:
    case AArch64::FCVTZSN_Z2Z_DtoS:
    case AArch64::FCVTZSN_Z2Z_HtoB:
    case AArch64::FCVTZSN_Z2Z_StoH:
    case AArch64::FCVTZUN_Z2Z_DtoS:
    case AArch64::FCVTZUN_Z2Z_HtoB:
    case AArch64::FCVTZUN_Z2Z_StoH:
    case AArch64::SQCVTN_Z2Z_StoH:
    case AArch64::SQCVTUN_Z2Z_StoH:
    case AArch64::UQCVTN_Z2Z_StoH: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 6;
      break;
    }
    case AArch64::SQRSHRN_Z2ZI_StoH:
    case AArch64::SQRSHRUN_Z2ZI_StoH:
    case AArch64::SQSHRN_Z2ZI_StoH:
    case AArch64::SQSHRUN_Z2ZI_StoH:
    case AArch64::UQRSHRN_Z2ZI_StoH:
    case AArch64::UQSHRN_Z2ZI_StoH: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::SQRSHRN_Z2ZI_HtoB:
    case AArch64::SQRSHRUN_Z2ZI_HtoB:
    case AArch64::SQSHRN_Z2ZI_HtoB:
    case AArch64::SQSHRUN_Z2ZI_HtoB:
    case AArch64::UQRSHRN_Z2ZI_HtoB:
    case AArch64::UQSHRN_Z2ZI_HtoB: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm
      op = getVecShiftR8OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::FCVTNT_Z2Z_StoB: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 6;
      break;
    }
    case AArch64::BF1CVTLT_ZZ_BtoH:
    case AArch64::BF1CVT_ZZ_BtoH:
    case AArch64::BF2CVTLT_ZZ_BtoH:
    case AArch64::BF2CVT_ZZ_BtoH:
    case AArch64::F1CVTLT_ZZ_BtoH:
    case AArch64::F1CVT_ZZ_BtoH:
    case AArch64::F2CVTLT_ZZ_BtoH:
    case AArch64::F2CVT_ZZ_BtoH:
    case AArch64::FEXPA_ZZ_D:
    case AArch64::FEXPA_ZZ_H:
    case AArch64::FEXPA_ZZ_S:
    case AArch64::FRECPE_ZZ_D:
    case AArch64::FRECPE_ZZ_H:
    case AArch64::FRECPE_ZZ_S:
    case AArch64::FRSQRTE_ZZ_D:
    case AArch64::FRSQRTE_ZZ_H:
    case AArch64::FRSQRTE_ZZ_S:
    case AArch64::MOVPRFX_ZZ:
    case AArch64::REV_ZZ_B:
    case AArch64::REV_ZZ_D:
    case AArch64::REV_ZZ_H:
    case AArch64::REV_ZZ_S:
    case AArch64::SCVTFLT_ZZ_BtoH:
    case AArch64::SCVTFLT_ZZ_HtoS:
    case AArch64::SCVTFLT_ZZ_StoD:
    case AArch64::SCVTF_ZZ_BtoH:
    case AArch64::SCVTF_ZZ_HtoS:
    case AArch64::SCVTF_ZZ_StoD:
    case AArch64::SQXTNB_ZZ_B:
    case AArch64::SQXTNB_ZZ_H:
    case AArch64::SQXTNB_ZZ_S:
    case AArch64::SQXTUNB_ZZ_B:
    case AArch64::SQXTUNB_ZZ_H:
    case AArch64::SQXTUNB_ZZ_S:
    case AArch64::SUNPKHI_ZZ_D:
    case AArch64::SUNPKHI_ZZ_H:
    case AArch64::SUNPKHI_ZZ_S:
    case AArch64::SUNPKLO_ZZ_D:
    case AArch64::SUNPKLO_ZZ_H:
    case AArch64::SUNPKLO_ZZ_S:
    case AArch64::UCVTFLT_ZZ_BtoH:
    case AArch64::UCVTFLT_ZZ_HtoS:
    case AArch64::UCVTFLT_ZZ_StoD:
    case AArch64::UCVTF_ZZ_BtoH:
    case AArch64::UCVTF_ZZ_HtoS:
    case AArch64::UCVTF_ZZ_StoD:
    case AArch64::UQXTNB_ZZ_B:
    case AArch64::UQXTNB_ZZ_H:
    case AArch64::UQXTNB_ZZ_S:
    case AArch64::UUNPKHI_ZZ_D:
    case AArch64::UUNPKHI_ZZ_H:
    case AArch64::UUNPKHI_ZZ_S:
    case AArch64::UUNPKLO_ZZ_D:
    case AArch64::UUNPKLO_ZZ_H:
    case AArch64::UUNPKLO_ZZ_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::ADDHNB_ZZZ_B:
    case AArch64::ADDHNB_ZZZ_H:
    case AArch64::ADDHNB_ZZZ_S:
    case AArch64::ADR_LSL_ZZZ_D_0:
    case AArch64::ADR_LSL_ZZZ_D_1:
    case AArch64::ADR_LSL_ZZZ_D_2:
    case AArch64::ADR_LSL_ZZZ_D_3:
    case AArch64::ADR_LSL_ZZZ_S_0:
    case AArch64::ADR_LSL_ZZZ_S_1:
    case AArch64::ADR_LSL_ZZZ_S_2:
    case AArch64::ADR_LSL_ZZZ_S_3:
    case AArch64::ADR_SXTW_ZZZ_D_0:
    case AArch64::ADR_SXTW_ZZZ_D_1:
    case AArch64::ADR_SXTW_ZZZ_D_2:
    case AArch64::ADR_SXTW_ZZZ_D_3:
    case AArch64::ADR_UXTW_ZZZ_D_0:
    case AArch64::ADR_UXTW_ZZZ_D_1:
    case AArch64::ADR_UXTW_ZZZ_D_2:
    case AArch64::ADR_UXTW_ZZZ_D_3:
    case AArch64::BDEP_ZZZ_B:
    case AArch64::BDEP_ZZZ_D:
    case AArch64::BDEP_ZZZ_H:
    case AArch64::BDEP_ZZZ_S:
    case AArch64::BEXT_ZZZ_B:
    case AArch64::BEXT_ZZZ_D:
    case AArch64::BEXT_ZZZ_H:
    case AArch64::BEXT_ZZZ_S:
    case AArch64::BGRP_ZZZ_B:
    case AArch64::BGRP_ZZZ_D:
    case AArch64::BGRP_ZZZ_H:
    case AArch64::BGRP_ZZZ_S:
    case AArch64::HISTSEG_ZZZ:
    case AArch64::LUTI6_Z2ZZ:
    case AArch64::PMULLB_ZZZ_D:
    case AArch64::PMULLB_ZZZ_H:
    case AArch64::PMULLB_ZZZ_Q:
    case AArch64::PMULLT_ZZZ_D:
    case AArch64::PMULLT_ZZZ_H:
    case AArch64::PMULLT_ZZZ_Q:
    case AArch64::RADDHNB_ZZZ_B:
    case AArch64::RADDHNB_ZZZ_H:
    case AArch64::RADDHNB_ZZZ_S:
    case AArch64::RAX1_ZZZ_D:
    case AArch64::RSUBHNB_ZZZ_B:
    case AArch64::RSUBHNB_ZZZ_H:
    case AArch64::RSUBHNB_ZZZ_S:
    case AArch64::SABDLB_ZZZ_D:
    case AArch64::SABDLB_ZZZ_H:
    case AArch64::SABDLB_ZZZ_S:
    case AArch64::SABDLT_ZZZ_D:
    case AArch64::SABDLT_ZZZ_H:
    case AArch64::SABDLT_ZZZ_S:
    case AArch64::SADDLBT_ZZZ_D:
    case AArch64::SADDLBT_ZZZ_H:
    case AArch64::SADDLBT_ZZZ_S:
    case AArch64::SADDLB_ZZZ_D:
    case AArch64::SADDLB_ZZZ_H:
    case AArch64::SADDLB_ZZZ_S:
    case AArch64::SADDLT_ZZZ_D:
    case AArch64::SADDLT_ZZZ_H:
    case AArch64::SADDLT_ZZZ_S:
    case AArch64::SADDWB_ZZZ_D:
    case AArch64::SADDWB_ZZZ_H:
    case AArch64::SADDWB_ZZZ_S:
    case AArch64::SADDWT_ZZZ_D:
    case AArch64::SADDWT_ZZZ_H:
    case AArch64::SADDWT_ZZZ_S:
    case AArch64::SM4EKEY_ZZZ_S:
    case AArch64::SMULLB_ZZZ_D:
    case AArch64::SMULLB_ZZZ_H:
    case AArch64::SMULLB_ZZZ_S:
    case AArch64::SMULLT_ZZZ_D:
    case AArch64::SMULLT_ZZZ_H:
    case AArch64::SMULLT_ZZZ_S:
    case AArch64::SQDMULLB_ZZZ_D:
    case AArch64::SQDMULLB_ZZZ_H:
    case AArch64::SQDMULLB_ZZZ_S:
    case AArch64::SQDMULLT_ZZZ_D:
    case AArch64::SQDMULLT_ZZZ_H:
    case AArch64::SQDMULLT_ZZZ_S:
    case AArch64::SSUBLBT_ZZZ_D:
    case AArch64::SSUBLBT_ZZZ_H:
    case AArch64::SSUBLBT_ZZZ_S:
    case AArch64::SSUBLB_ZZZ_D:
    case AArch64::SSUBLB_ZZZ_H:
    case AArch64::SSUBLB_ZZZ_S:
    case AArch64::SSUBLTB_ZZZ_D:
    case AArch64::SSUBLTB_ZZZ_H:
    case AArch64::SSUBLTB_ZZZ_S:
    case AArch64::SSUBLT_ZZZ_D:
    case AArch64::SSUBLT_ZZZ_H:
    case AArch64::SSUBLT_ZZZ_S:
    case AArch64::SSUBWB_ZZZ_D:
    case AArch64::SSUBWB_ZZZ_H:
    case AArch64::SSUBWB_ZZZ_S:
    case AArch64::SSUBWT_ZZZ_D:
    case AArch64::SSUBWT_ZZZ_H:
    case AArch64::SSUBWT_ZZZ_S:
    case AArch64::SUBHNB_ZZZ_B:
    case AArch64::SUBHNB_ZZZ_H:
    case AArch64::SUBHNB_ZZZ_S:
    case AArch64::TBLQ_ZZZ_B:
    case AArch64::TBLQ_ZZZ_D:
    case AArch64::TBLQ_ZZZ_H:
    case AArch64::TBLQ_ZZZ_S:
    case AArch64::UABDLB_ZZZ_D:
    case AArch64::UABDLB_ZZZ_H:
    case AArch64::UABDLB_ZZZ_S:
    case AArch64::UABDLT_ZZZ_D:
    case AArch64::UABDLT_ZZZ_H:
    case AArch64::UABDLT_ZZZ_S:
    case AArch64::UADDLB_ZZZ_D:
    case AArch64::UADDLB_ZZZ_H:
    case AArch64::UADDLB_ZZZ_S:
    case AArch64::UADDLT_ZZZ_D:
    case AArch64::UADDLT_ZZZ_H:
    case AArch64::UADDLT_ZZZ_S:
    case AArch64::UADDWB_ZZZ_D:
    case AArch64::UADDWB_ZZZ_H:
    case AArch64::UADDWB_ZZZ_S:
    case AArch64::UADDWT_ZZZ_D:
    case AArch64::UADDWT_ZZZ_H:
    case AArch64::UADDWT_ZZZ_S:
    case AArch64::UMULLB_ZZZ_D:
    case AArch64::UMULLB_ZZZ_H:
    case AArch64::UMULLB_ZZZ_S:
    case AArch64::UMULLT_ZZZ_D:
    case AArch64::UMULLT_ZZZ_H:
    case AArch64::UMULLT_ZZZ_S:
    case AArch64::USUBLB_ZZZ_D:
    case AArch64::USUBLB_ZZZ_H:
    case AArch64::USUBLB_ZZZ_S:
    case AArch64::USUBLT_ZZZ_D:
    case AArch64::USUBLT_ZZZ_H:
    case AArch64::USUBLT_ZZZ_S:
    case AArch64::USUBWB_ZZZ_D:
    case AArch64::USUBWB_ZZZ_H:
    case AArch64::USUBWB_ZZZ_S:
    case AArch64::USUBWT_ZZZ_D:
    case AArch64::USUBWT_ZZZ_H:
    case AArch64::USUBWT_ZZZ_S:
    case AArch64::UZPQ1_ZZZ_B:
    case AArch64::UZPQ1_ZZZ_D:
    case AArch64::UZPQ1_ZZZ_H:
    case AArch64::UZPQ1_ZZZ_S:
    case AArch64::UZPQ2_ZZZ_B:
    case AArch64::UZPQ2_ZZZ_D:
    case AArch64::UZPQ2_ZZZ_H:
    case AArch64::UZPQ2_ZZZ_S:
    case AArch64::ZIPQ1_ZZZ_B:
    case AArch64::ZIPQ1_ZZZ_D:
    case AArch64::ZIPQ1_ZZZ_H:
    case AArch64::ZIPQ1_ZZZ_S:
    case AArch64::ZIPQ2_ZZZ_B:
    case AArch64::ZIPQ2_ZZZ_D:
    case AArch64::ZIPQ2_ZZZ_H:
    case AArch64::ZIPQ2_ZZZ_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LUTI4_ZZZI_B:
    case AArch64::LUTI6_Z2ZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 23;
      break;
    }
    case AArch64::LUTI2_ZZZI_B:
    case AArch64::LUTI4_Z2ZZI:
    case AArch64::LUTI4_ZZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 22;
      break;
    }
    case AArch64::LUTI2_ZZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x6) << 21;
      Value |= (op & 0x1) << 12;
      break;
    }
    case AArch64::FMUL_ZZZI_S:
    case AArch64::MUL_ZZZI_S:
    case AArch64::SQDMULH_ZZZI_S:
    case AArch64::SQRDMULH_ZZZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::BFMUL_ZZZI:
    case AArch64::FMUL_ZZZI_H:
    case AArch64::MUL_ZZZI_H:
    case AArch64::SQDMULH_ZZZI_H:
    case AArch64::SQRDMULH_ZZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x4) << 20;
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::SMULLB_ZZZI_S:
    case AArch64::SMULLT_ZZZI_S:
    case AArch64::SQDMULLB_ZZZI_S:
    case AArch64::SQDMULLT_ZZZI_S:
    case AArch64::UMULLB_ZZZI_S:
    case AArch64::UMULLT_ZZZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x6) << 18;
      Value |= (op & 0x1) << 11;
      break;
    }
    case AArch64::FMUL_ZZZI_D:
    case AArch64::MUL_ZZZI_D:
    case AArch64::SQDMULH_ZZZI_D:
    case AArch64::SQRDMULH_ZZZI_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 20;
      break;
    }
    case AArch64::SMULLB_ZZZI_D:
    case AArch64::SMULLT_ZZZI_D:
    case AArch64::SQDMULLB_ZZZI_D:
    case AArch64::SQDMULLT_ZZZI_D:
    case AArch64::UMULLB_ZZZI_D:
    case AArch64::UMULLT_ZZZI_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x2) << 19;
      Value |= (op & 0x1) << 11;
      break;
    }
    case AArch64::DUP_ZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x18) << 19;
      Value |= (op & 0x7) << 18;
      break;
    }
    case AArch64::DUP_ZZI_Q: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 22;
      break;
    }
    case AArch64::DUP_ZZI_B: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x30) << 18;
      Value |= (op & 0xf) << 17;
      break;
    }
    case AArch64::DUP_ZZI_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x6) << 21;
      Value |= (op & 0x1) << 20;
      break;
    }
    case AArch64::DUP_ZZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xc) << 20;
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::LSL_ZZI_H:
    case AArch64::SSHLLB_ZZI_S:
    case AArch64::SSHLLT_ZZI_S:
    case AArch64::USHLLB_ZZI_S:
    case AArch64::USHLLT_ZZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL16OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::LSL_ZZI_S:
    case AArch64::SSHLLB_ZZI_D:
    case AArch64::SSHLLT_ZZI_D:
    case AArch64::USHLLB_ZZI_D:
    case AArch64::USHLLT_ZZI_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL32OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LSL_ZZI_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL64OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x20) << 17;
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LSL_ZZI_B:
    case AArch64::SSHLLB_ZZI_H:
    case AArch64::SSHLLT_ZZI_H:
    case AArch64::USHLLB_ZZI_H:
    case AArch64::USHLLT_ZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL8OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::ASR_ZZI_H:
    case AArch64::LSR_ZZI_H:
    case AArch64::RSHRNB_ZZI_H:
    case AArch64::SHRNB_ZZI_H:
    case AArch64::SQRSHRNB_ZZI_H:
    case AArch64::SQRSHRUNB_ZZI_H:
    case AArch64::SQSHRNB_ZZI_H:
    case AArch64::SQSHRUNB_ZZI_H:
    case AArch64::UQRSHRNB_ZZI_H:
    case AArch64::UQSHRNB_ZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::ASR_ZZI_S:
    case AArch64::LSR_ZZI_S:
    case AArch64::RSHRNB_ZZI_S:
    case AArch64::SHRNB_ZZI_S:
    case AArch64::SQRSHRNB_ZZI_S:
    case AArch64::SQRSHRUNB_ZZI_S:
    case AArch64::SQSHRNB_ZZI_S:
    case AArch64::SQSHRUNB_ZZI_S:
    case AArch64::UQRSHRNB_ZZI_S:
    case AArch64::UQSHRNB_ZZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR32OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::ASR_ZZI_D:
    case AArch64::LSR_ZZI_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR64OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x20) << 17;
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::ASR_ZZI_B:
    case AArch64::LSR_ZZI_B:
    case AArch64::RSHRNB_ZZI_B:
    case AArch64::SHRNB_ZZI_B:
    case AArch64::SQRSHRNB_ZZI_B:
    case AArch64::SQRSHRUNB_ZZI_B:
    case AArch64::SQSHRNB_ZZI_B:
    case AArch64::SQSHRUNB_ZZI_B:
    case AArch64::UQRSHRNB_ZZI_B:
    case AArch64::UQSHRNB_ZZI_B: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR8OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::EXT_ZZI_B: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf8) << 13;
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::DUPQ_ZZI_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 20;
      break;
    }
    case AArch64::DUPQ_ZZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::DUPQ_ZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 18;
      break;
    }
    case AArch64::DUPQ_ZZI_B: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: index
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 17;
      break;
    }
    case AArch64::LUTI6_ZTZ:
    case AArch64::SQXTNT_ZZ_B:
    case AArch64::SQXTNT_ZZ_H:
    case AArch64::SQXTNT_ZZ_S:
    case AArch64::SQXTUNT_ZZ_B:
    case AArch64::SQXTUNT_ZZ_H:
    case AArch64::SQXTUNT_ZZ_S:
    case AArch64::UQXTNT_ZZ_B:
    case AArch64::UQXTNT_ZZ_H:
    case AArch64::UQXTNT_ZZ_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::FCVTLT_ZPzZ_HtoS:
    case AArch64::FCVTLT_ZPzZ_StoD: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::HISTCNT_ZPzZZ_D:
    case AArch64::HISTCNT_ZPzZZ_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::ADDHNT_ZZZ_B:
    case AArch64::ADDHNT_ZZZ_H:
    case AArch64::ADDHNT_ZZZ_S:
    case AArch64::EORBT_ZZZ_B:
    case AArch64::EORBT_ZZZ_D:
    case AArch64::EORBT_ZZZ_H:
    case AArch64::EORBT_ZZZ_S:
    case AArch64::EORTB_ZZZ_B:
    case AArch64::EORTB_ZZZ_D:
    case AArch64::EORTB_ZZZ_H:
    case AArch64::EORTB_ZZZ_S:
    case AArch64::RADDHNT_ZZZ_B:
    case AArch64::RADDHNT_ZZZ_H:
    case AArch64::RADDHNT_ZZZ_S:
    case AArch64::RSUBHNT_ZZZ_B:
    case AArch64::RSUBHNT_ZZZ_H:
    case AArch64::RSUBHNT_ZZZ_S:
    case AArch64::SUBHNT_ZZZ_B:
    case AArch64::SUBHNT_ZZZ_H:
    case AArch64::SUBHNT_ZZZ_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SLI_ZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL16OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::SLI_ZZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL32OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SLI_ZZI_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL64OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x20) << 17;
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SLI_ZZI_B: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftL8OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::RSHRNT_ZZI_H:
    case AArch64::SHRNT_ZZI_H:
    case AArch64::SQRSHRNT_ZZI_H:
    case AArch64::SQRSHRUNT_ZZI_H:
    case AArch64::SQSHRNT_ZZI_H:
    case AArch64::SQSHRUNT_ZZI_H:
    case AArch64::SRI_ZZI_H:
    case AArch64::UQRSHRNT_ZZI_H:
    case AArch64::UQSHRNT_ZZI_H: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::RSHRNT_ZZI_S:
    case AArch64::SHRNT_ZZI_S:
    case AArch64::SQRSHRNT_ZZI_S:
    case AArch64::SQRSHRUNT_ZZI_S:
    case AArch64::SQSHRNT_ZZI_S:
    case AArch64::SQSHRUNT_ZZI_S:
    case AArch64::SRI_ZZI_S:
    case AArch64::UQRSHRNT_ZZI_S:
    case AArch64::UQSHRNT_ZZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SRI_ZZI_D: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x20) << 17;
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::RSHRNT_ZZI_B:
    case AArch64::SHRNT_ZZI_B:
    case AArch64::SQRSHRNT_ZZI_B:
    case AArch64::SQRSHRUNT_ZZI_B:
    case AArch64::SQSHRNT_ZZI_B:
    case AArch64::SQSHRUNT_ZZI_B:
    case AArch64::SRI_ZZI_B:
    case AArch64::UQRSHRNT_ZZI_B:
    case AArch64::UQSHRNT_ZZI_B: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::BFCVTNT_ZPmZ:
    case AArch64::BFCVTNT_ZPzZ_StoH:
    case AArch64::FCVTLT_ZPmZ_HtoS:
    case AArch64::FCVTLT_ZPmZ_StoD:
    case AArch64::FCVTNT_ZPmZ_DtoS:
    case AArch64::FCVTNT_ZPmZ_StoH:
    case AArch64::FCVTNT_ZPzZ_DtoS:
    case AArch64::FCVTNT_ZPzZ_StoH:
    case AArch64::FCVTXNT_ZPmZ_DtoS:
    case AArch64::FCVTXNT_ZPzZ_StoD: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::DUP_ZI_B:
    case AArch64::DUP_ZI_D:
    case AArch64::DUP_ZI_H:
    case AArch64::DUP_ZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getImm8OptLsl(MI, 1, Fixups, STI);
      Value |= (op & 0x1ff) << 5;
      break;
    }
    case AArch64::INDEX_II_B:
    case AArch64::INDEX_II_D:
    case AArch64::INDEX_II_H:
    case AArch64::INDEX_II_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm5
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm5b
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::FDUP_ZI_D:
    case AArch64::FDUP_ZI_H:
    case AArch64::FDUP_ZI_S: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xff) << 5;
      break;
    }
    case AArch64::DUPM_ZI: {
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imms
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1fff) << 5;
      break;
    }
    case AArch64::FCMLA_ZPmZZ_D:
    case AArch64::FCMLA_ZPmZZ_H:
    case AArch64::FCMLA_ZPmZZ_S: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 13;
      break;
    }
    case AArch64::ADCLB_ZZZ_D:
    case AArch64::ADCLB_ZZZ_S:
    case AArch64::ADCLT_ZZZ_D:
    case AArch64::ADCLT_ZZZ_S:
    case AArch64::BFDOT_ZZZ:
    case AArch64::BFMLALB_ZZZ:
    case AArch64::BFMLALT_ZZZ:
    case AArch64::BFMLSLB_ZZZ_S:
    case AArch64::BFMLSLT_ZZZ_S:
    case AArch64::BFMMLA_ZZZ_H:
    case AArch64::BFMMLA_ZZZ_HtoS:
    case AArch64::FDOT_ZZZ_BtoH:
    case AArch64::FDOT_ZZZ_BtoS:
    case AArch64::FDOT_ZZZ_S:
    case AArch64::FMLALB_ZZZ:
    case AArch64::FMLALB_ZZZ_SHH:
    case AArch64::FMLALLBB_ZZZ:
    case AArch64::FMLALLBT_ZZZ:
    case AArch64::FMLALLTB_ZZZ:
    case AArch64::FMLALLTT_ZZZ:
    case AArch64::FMLALT_ZZZ:
    case AArch64::FMLALT_ZZZ_SHH:
    case AArch64::FMLLA_ZZZ_HtoS:
    case AArch64::FMLSLB_ZZZ_SHH:
    case AArch64::FMLSLT_ZZZ_SHH:
    case AArch64::FMMLA_ZZZ_BtoH:
    case AArch64::FMMLA_ZZZ_BtoS:
    case AArch64::FMMLA_ZZZ_D:
    case AArch64::FMMLA_ZZZ_H:
    case AArch64::FMMLA_ZZZ_S:
    case AArch64::MLA_CPA:
    case AArch64::SABALB_ZZZ_D:
    case AArch64::SABALB_ZZZ_H:
    case AArch64::SABALB_ZZZ_S:
    case AArch64::SABALT_ZZZ_D:
    case AArch64::SABALT_ZZZ_H:
    case AArch64::SABALT_ZZZ_S:
    case AArch64::SABAL_ZZZ_BtoH:
    case AArch64::SABAL_ZZZ_HtoS:
    case AArch64::SABAL_ZZZ_StoD:
    case AArch64::SABA_ZZZ_B:
    case AArch64::SABA_ZZZ_D:
    case AArch64::SABA_ZZZ_H:
    case AArch64::SABA_ZZZ_S:
    case AArch64::SBCLB_ZZZ_D:
    case AArch64::SBCLB_ZZZ_S:
    case AArch64::SBCLT_ZZZ_D:
    case AArch64::SBCLT_ZZZ_S:
    case AArch64::SDOT_ZZZ_BtoH:
    case AArch64::SDOT_ZZZ_BtoS:
    case AArch64::SDOT_ZZZ_HtoD:
    case AArch64::SDOT_ZZZ_HtoS:
    case AArch64::SMLALB_ZZZ_D:
    case AArch64::SMLALB_ZZZ_H:
    case AArch64::SMLALB_ZZZ_S:
    case AArch64::SMLALT_ZZZ_D:
    case AArch64::SMLALT_ZZZ_H:
    case AArch64::SMLALT_ZZZ_S:
    case AArch64::SMLSLB_ZZZ_D:
    case AArch64::SMLSLB_ZZZ_H:
    case AArch64::SMLSLB_ZZZ_S:
    case AArch64::SMLSLT_ZZZ_D:
    case AArch64::SMLSLT_ZZZ_H:
    case AArch64::SMLSLT_ZZZ_S:
    case AArch64::SMMLA_ZZZ:
    case AArch64::SQDMLALBT_ZZZ_D:
    case AArch64::SQDMLALBT_ZZZ_H:
    case AArch64::SQDMLALBT_ZZZ_S:
    case AArch64::SQDMLALB_ZZZ_D:
    case AArch64::SQDMLALB_ZZZ_H:
    case AArch64::SQDMLALB_ZZZ_S:
    case AArch64::SQDMLALT_ZZZ_D:
    case AArch64::SQDMLALT_ZZZ_H:
    case AArch64::SQDMLALT_ZZZ_S:
    case AArch64::SQDMLSLBT_ZZZ_D:
    case AArch64::SQDMLSLBT_ZZZ_H:
    case AArch64::SQDMLSLBT_ZZZ_S:
    case AArch64::SQDMLSLB_ZZZ_D:
    case AArch64::SQDMLSLB_ZZZ_H:
    case AArch64::SQDMLSLB_ZZZ_S:
    case AArch64::SQDMLSLT_ZZZ_D:
    case AArch64::SQDMLSLT_ZZZ_H:
    case AArch64::SQDMLSLT_ZZZ_S:
    case AArch64::SQRDMLAH_ZZZ_B:
    case AArch64::SQRDMLAH_ZZZ_D:
    case AArch64::SQRDMLAH_ZZZ_H:
    case AArch64::SQRDMLAH_ZZZ_S:
    case AArch64::SQRDMLSH_ZZZ_B:
    case AArch64::SQRDMLSH_ZZZ_D:
    case AArch64::SQRDMLSH_ZZZ_H:
    case AArch64::SQRDMLSH_ZZZ_S:
    case AArch64::UABALB_ZZZ_D:
    case AArch64::UABALB_ZZZ_H:
    case AArch64::UABALB_ZZZ_S:
    case AArch64::UABALT_ZZZ_D:
    case AArch64::UABALT_ZZZ_H:
    case AArch64::UABALT_ZZZ_S:
    case AArch64::UABAL_ZZZ_BtoH:
    case AArch64::UABAL_ZZZ_HtoS:
    case AArch64::UABAL_ZZZ_StoD:
    case AArch64::UABA_ZZZ_B:
    case AArch64::UABA_ZZZ_D:
    case AArch64::UABA_ZZZ_H:
    case AArch64::UABA_ZZZ_S:
    case AArch64::UDOT_ZZZ_BtoH:
    case AArch64::UDOT_ZZZ_BtoS:
    case AArch64::UDOT_ZZZ_HtoD:
    case AArch64::UDOT_ZZZ_HtoS:
    case AArch64::UMLALB_ZZZ_D:
    case AArch64::UMLALB_ZZZ_H:
    case AArch64::UMLALB_ZZZ_S:
    case AArch64::UMLALT_ZZZ_D:
    case AArch64::UMLALT_ZZZ_H:
    case AArch64::UMLALT_ZZZ_S:
    case AArch64::UMLSLB_ZZZ_D:
    case AArch64::UMLSLB_ZZZ_H:
    case AArch64::UMLSLB_ZZZ_S:
    case AArch64::UMLSLT_ZZZ_D:
    case AArch64::UMLSLT_ZZZ_H:
    case AArch64::UMLSLT_ZZZ_S:
    case AArch64::UMMLA_ZZZ:
    case AArch64::USDOT_ZZZ:
    case AArch64::USMMLA_ZZZ: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::CDOT_ZZZ_D:
    case AArch64::CDOT_ZZZ_S:
    case AArch64::CMLA_ZZZ_B:
    case AArch64::CMLA_ZZZ_D:
    case AArch64::CMLA_ZZZ_H:
    case AArch64::CMLA_ZZZ_S:
    case AArch64::SQRDCMLAH_ZZZ_B:
    case AArch64::SQRDCMLAH_ZZZ_D:
    case AArch64::SQRDCMLAH_ZZZ_H:
    case AArch64::SQRDCMLAH_ZZZ_S: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 10;
      break;
    }
    case AArch64::SDOT_ZZZI_HtoS:
    case AArch64::UDOT_ZZZI_HtoS: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: i2
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::SUDOT_ZZZI:
    case AArch64::USDOT_ZZZI: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::FMLALB_ZZZI:
    case AArch64::FMLALLBB_ZZZI:
    case AArch64::FMLALLBT_ZZZI:
    case AArch64::FMLALLTB_ZZZI:
    case AArch64::FMLALLTT_ZZZI:
    case AArch64::FMLALT_ZZZI: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0xc) << 17;
      Value |= (op & 0x3) << 10;
      break;
    }
    case AArch64::BFDOT_ZZI:
    case AArch64::FDOT_ZZZI_BtoS:
    case AArch64::FDOT_ZZZI_S:
    case AArch64::FMLA_ZZZI_S:
    case AArch64::FMLS_ZZZI_S:
    case AArch64::MLA_ZZZI_S:
    case AArch64::MLS_ZZZI_S:
    case AArch64::SQRDMLAH_ZZZI_S:
    case AArch64::SQRDMLSH_ZZZI_S: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::BFMLA_ZZZI:
    case AArch64::BFMLS_ZZZI:
    case AArch64::FMLA_ZZZI_H:
    case AArch64::FMLS_ZZZI_H:
    case AArch64::MLA_ZZZI_H:
    case AArch64::MLS_ZZZI_H:
    case AArch64::SQRDMLAH_ZZZI_H:
    case AArch64::SQRDMLSH_ZZZI_H: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x4) << 20;
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::BFMLALB_ZZZI:
    case AArch64::BFMLALT_ZZZI:
    case AArch64::BFMLSLB_ZZZI_S:
    case AArch64::BFMLSLT_ZZZI_S:
    case AArch64::FDOT_ZZZI_BtoH:
    case AArch64::FMLALB_ZZZI_SHH:
    case AArch64::FMLALT_ZZZI_SHH:
    case AArch64::FMLSLB_ZZZI_SHH:
    case AArch64::FMLSLT_ZZZI_SHH:
    case AArch64::SMLALB_ZZZI_S:
    case AArch64::SMLALT_ZZZI_S:
    case AArch64::SMLSLB_ZZZI_S:
    case AArch64::SMLSLT_ZZZI_S:
    case AArch64::SQDMLALB_ZZZI_S:
    case AArch64::SQDMLALT_ZZZI_S:
    case AArch64::SQDMLSLB_ZZZI_S:
    case AArch64::SQDMLSLT_ZZZI_S:
    case AArch64::UMLALB_ZZZI_S:
    case AArch64::UMLALT_ZZZI_S:
    case AArch64::UMLSLB_ZZZI_S:
    case AArch64::UMLSLT_ZZZI_S: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x6) << 18;
      Value |= (op & 0x1) << 11;
      break;
    }
    case AArch64::FMLA_ZZZI_D:
    case AArch64::FMLS_ZZZI_D:
    case AArch64::MLA_ZZZI_D:
    case AArch64::MLS_ZZZI_D:
    case AArch64::SQRDMLAH_ZZZI_D:
    case AArch64::SQRDMLSH_ZZZI_D: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 20;
      break;
    }
    case AArch64::SMLALB_ZZZI_D:
    case AArch64::SMLALT_ZZZI_D:
    case AArch64::SMLSLB_ZZZI_D:
    case AArch64::SMLSLT_ZZZI_D:
    case AArch64::SQDMLALB_ZZZI_D:
    case AArch64::SQDMLALT_ZZZI_D:
    case AArch64::SQDMLSLB_ZZZI_D:
    case AArch64::SQDMLSLT_ZZZI_D:
    case AArch64::UMLALB_ZZZI_D:
    case AArch64::UMLALT_ZZZI_D:
    case AArch64::UMLSLB_ZZZI_D:
    case AArch64::UMLSLT_ZZZI_D: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x2) << 19;
      Value |= (op & 0x1) << 11;
      break;
    }
    case AArch64::FCMLA_ZZZI_H: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::FCMLA_ZZZI_S: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 20;
      break;
    }
    case AArch64::SRSRA_ZZI_H:
    case AArch64::SSRA_ZZI_H:
    case AArch64::URSRA_ZZI_H:
    case AArch64::USRA_ZZI_H: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::SRSRA_ZZI_S:
    case AArch64::SSRA_ZZI_S:
    case AArch64::URSRA_ZZI_S:
    case AArch64::USRA_ZZI_S: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SRSRA_ZZI_D:
    case AArch64::SSRA_ZZI_D:
    case AArch64::URSRA_ZZI_D:
    case AArch64::USRA_ZZI_D: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x20) << 17;
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SRSRA_ZZI_B:
    case AArch64::SSRA_ZZI_B:
    case AArch64::URSRA_ZZI_B:
    case AArch64::USRA_ZZI_B: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::SDOT_ZZZI_HtoD:
    case AArch64::UDOT_ZZZI_HtoD: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 20;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::SDOT_ZZZI_BtoS:
    case AArch64::UDOT_ZZZI_BtoS: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 19;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::SDOT_ZZZI_BtoH:
    case AArch64::UDOT_ZZZI_BtoH: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x4) << 20;
      Value |= (op & 0x3) << 19;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::CDOT_ZZZI_D:
    case AArch64::CMLA_ZZZI_S:
    case AArch64::SQRDCMLAH_ZZZI_S: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 20;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::CDOT_ZZZI_S:
    case AArch64::CMLA_ZZZI_H:
    case AArch64::SQRDCMLAH_ZZZI_H: {
      // op: Zda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x3) << 10;
      // op: iop
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x3) << 19;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::AESIMC_ZZ_B:
    case AArch64::AESMC_ZZ_B: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::BCAX_ZZZZ:
    case AArch64::BSL1N_ZZZZ:
    case AArch64::BSL2N_ZZZZ:
    case AArch64::BSL_ZZZZ:
    case AArch64::EOR3_ZZZZ:
    case AArch64::NBSL_ZZZZ: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zk
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::MAD_CPA: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Za
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::AESD_ZZZ_B:
    case AArch64::AESE_ZZZ_B:
    case AArch64::SM4E_ZZZ_S: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::XAR_ZZZI_H: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR16OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::XAR_ZZZI_S: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR32OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::XAR_ZZZI_D: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR64OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x20) << 17;
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::XAR_ZZZI_B: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getVecShiftR8OpValue(MI, 3, Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::FTMAD_ZZI_D:
    case AArch64::FTMAD_ZZI_H:
    case AArch64::FTMAD_ZZI_S: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 16;
      break;
    }
    case AArch64::EXTQ_ZZI: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::EXT_ZZI: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm8
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf8) << 13;
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::CADD_ZZI_B:
    case AArch64::CADD_ZZI_D:
    case AArch64::CADD_ZZI_H:
    case AArch64::CADD_ZZI_S:
    case AArch64::SQCADD_ZZI_B:
    case AArch64::SQCADD_ZZI_D:
    case AArch64::SQCADD_ZZI_H:
    case AArch64::SQCADD_ZZI_S: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: rot
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 10;
      break;
    }
    case AArch64::FCADD_ZPmZ_D:
    case AArch64::FCADD_ZPmZ_H:
    case AArch64::FCADD_ZPmZ_S: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1) << 16;
      break;
    }
    case AArch64::ADD_ZI_B:
    case AArch64::ADD_ZI_D:
    case AArch64::ADD_ZI_H:
    case AArch64::ADD_ZI_S:
    case AArch64::SQADD_ZI_B:
    case AArch64::SQADD_ZI_D:
    case AArch64::SQADD_ZI_H:
    case AArch64::SQADD_ZI_S:
    case AArch64::SQSUB_ZI_B:
    case AArch64::SQSUB_ZI_D:
    case AArch64::SQSUB_ZI_H:
    case AArch64::SQSUB_ZI_S:
    case AArch64::SUBR_ZI_B:
    case AArch64::SUBR_ZI_D:
    case AArch64::SUBR_ZI_H:
    case AArch64::SUBR_ZI_S:
    case AArch64::SUB_ZI_B:
    case AArch64::SUB_ZI_D:
    case AArch64::SUB_ZI_H:
    case AArch64::SUB_ZI_S:
    case AArch64::UQADD_ZI_B:
    case AArch64::UQADD_ZI_D:
    case AArch64::UQADD_ZI_H:
    case AArch64::UQADD_ZI_S:
    case AArch64::UQSUB_ZI_B:
    case AArch64::UQSUB_ZI_D:
    case AArch64::UQSUB_ZI_H:
    case AArch64::UQSUB_ZI_S: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getImm8OptLsl(MI, 2, Fixups, STI);
      Value |= (op & 0x1ff) << 5;
      break;
    }
    case AArch64::MUL_ZI_B:
    case AArch64::MUL_ZI_D:
    case AArch64::MUL_ZI_H:
    case AArch64::MUL_ZI_S:
    case AArch64::SMAX_ZI_B:
    case AArch64::SMAX_ZI_D:
    case AArch64::SMAX_ZI_H:
    case AArch64::SMAX_ZI_S:
    case AArch64::SMIN_ZI_B:
    case AArch64::SMIN_ZI_D:
    case AArch64::SMIN_ZI_H:
    case AArch64::SMIN_ZI_S:
    case AArch64::UMAX_ZI_B:
    case AArch64::UMAX_ZI_D:
    case AArch64::UMAX_ZI_H:
    case AArch64::UMAX_ZI_S:
    case AArch64::UMIN_ZI_B:
    case AArch64::UMIN_ZI_D:
    case AArch64::UMIN_ZI_H:
    case AArch64::UMIN_ZI_S: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xff) << 5;
      break;
    }
    case AArch64::AND_ZI:
    case AArch64::EOR_ZI:
    case AArch64::ORR_ZI: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imms13
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1fff) << 5;
      break;
    }
    case AArch64::DECD_ZPiI:
    case AArch64::DECH_ZPiI:
    case AArch64::DECW_ZPiI:
    case AArch64::INCD_ZPiI:
    case AArch64::INCH_ZPiI:
    case AArch64::INCW_ZPiI:
    case AArch64::SQDECD_ZPiI:
    case AArch64::SQDECH_ZPiI:
    case AArch64::SQDECW_ZPiI:
    case AArch64::SQINCD_ZPiI:
    case AArch64::SQINCH_ZPiI:
    case AArch64::SQINCW_ZPiI:
    case AArch64::UQDECD_ZPiI:
    case AArch64::UQDECH_ZPiI:
    case AArch64::UQDECW_ZPiI:
    case AArch64::UQINCD_ZPiI:
    case AArch64::UQINCH_ZPiI:
    case AArch64::UQINCW_ZPiI: {
      // op: Zdn
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: pattern
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm4
      op = getSVEIncDecImm(MI, 3, Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::BFMAXNM_VG2_2Z2Z_H:
    case AArch64::BFMAX_VG2_2Z2Z_H:
    case AArch64::BFMINNM_VG2_2Z2Z_H:
    case AArch64::BFMIN_VG2_2Z2Z_H:
    case AArch64::BFSCALE_2Z2Z:
    case AArch64::FAMAX_2Z2Z_D:
    case AArch64::FAMAX_2Z2Z_H:
    case AArch64::FAMAX_2Z2Z_S:
    case AArch64::FAMIN_2Z2Z_D:
    case AArch64::FAMIN_2Z2Z_H:
    case AArch64::FAMIN_2Z2Z_S:
    case AArch64::FMAXNM_VG2_2Z2Z_D:
    case AArch64::FMAXNM_VG2_2Z2Z_H:
    case AArch64::FMAXNM_VG2_2Z2Z_S:
    case AArch64::FMAX_VG2_2Z2Z_D:
    case AArch64::FMAX_VG2_2Z2Z_H:
    case AArch64::FMAX_VG2_2Z2Z_S:
    case AArch64::FMINNM_VG2_2Z2Z_D:
    case AArch64::FMINNM_VG2_2Z2Z_H:
    case AArch64::FMINNM_VG2_2Z2Z_S:
    case AArch64::FMIN_VG2_2Z2Z_D:
    case AArch64::FMIN_VG2_2Z2Z_H:
    case AArch64::FMIN_VG2_2Z2Z_S:
    case AArch64::FSCALE_2Z2Z_D:
    case AArch64::FSCALE_2Z2Z_H:
    case AArch64::FSCALE_2Z2Z_S:
    case AArch64::SMAX_VG2_2Z2Z_B:
    case AArch64::SMAX_VG2_2Z2Z_D:
    case AArch64::SMAX_VG2_2Z2Z_H:
    case AArch64::SMAX_VG2_2Z2Z_S:
    case AArch64::SMIN_VG2_2Z2Z_B:
    case AArch64::SMIN_VG2_2Z2Z_D:
    case AArch64::SMIN_VG2_2Z2Z_H:
    case AArch64::SMIN_VG2_2Z2Z_S:
    case AArch64::SQDMULH_VG2_2Z2Z_B:
    case AArch64::SQDMULH_VG2_2Z2Z_D:
    case AArch64::SQDMULH_VG2_2Z2Z_H:
    case AArch64::SQDMULH_VG2_2Z2Z_S:
    case AArch64::SRSHL_VG2_2Z2Z_B:
    case AArch64::SRSHL_VG2_2Z2Z_D:
    case AArch64::SRSHL_VG2_2Z2Z_H:
    case AArch64::SRSHL_VG2_2Z2Z_S:
    case AArch64::UMAX_VG2_2Z2Z_B:
    case AArch64::UMAX_VG2_2Z2Z_D:
    case AArch64::UMAX_VG2_2Z2Z_H:
    case AArch64::UMAX_VG2_2Z2Z_S:
    case AArch64::UMIN_VG2_2Z2Z_B:
    case AArch64::UMIN_VG2_2Z2Z_D:
    case AArch64::UMIN_VG2_2Z2Z_H:
    case AArch64::UMIN_VG2_2Z2Z_S:
    case AArch64::URSHL_VG2_2Z2Z_B:
    case AArch64::URSHL_VG2_2Z2Z_D:
    case AArch64::URSHL_VG2_2Z2Z_H:
    case AArch64::URSHL_VG2_2Z2Z_S: {
      // op: Zm
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 17;
      // op: Zdn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::FMLALL_VG2_M2Z2Z_BtoS:
    case AArch64::SMLALL_VG2_M2Z2Z_BtoS:
    case AArch64::SMLALL_VG2_M2Z2Z_HtoD:
    case AArch64::SMLSLL_VG2_M2Z2Z_BtoS:
    case AArch64::SMLSLL_VG2_M2Z2Z_HtoD:
    case AArch64::UMLALL_VG2_M2Z2Z_BtoS:
    case AArch64::UMLALL_VG2_M2Z2Z_HtoD:
    case AArch64::UMLSLL_VG2_M2Z2Z_BtoS:
    case AArch64::UMLSLL_VG2_M2Z2Z_HtoD:
    case AArch64::USMLALL_VG2_M2Z2Z_BtoS: {
      // op: Zm
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 5, Fixups, STI);
      Value |= (op & 0xf) << 17;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      break;
    }
    case AArch64::ADD_VG2_M2Z2Z_D:
    case AArch64::ADD_VG2_M2Z2Z_S:
    case AArch64::BFDOT_VG2_M2Z2Z_HtoS:
    case AArch64::BFMLA_VG2_M2Z2Z:
    case AArch64::BFMLS_VG2_M2Z2Z:
    case AArch64::FDOT_VG2_M2Z2Z_BtoH:
    case AArch64::FDOT_VG2_M2Z2Z_BtoS:
    case AArch64::FDOT_VG2_M2Z2Z_HtoS:
    case AArch64::FMLA_VG2_M2Z2Z_D:
    case AArch64::FMLA_VG2_M2Z2Z_H:
    case AArch64::FMLA_VG2_M2Z2Z_S:
    case AArch64::FMLS_VG2_M2Z2Z_D:
    case AArch64::FMLS_VG2_M2Z2Z_H:
    case AArch64::FMLS_VG2_M2Z2Z_S:
    case AArch64::SDOT_VG2_M2Z2Z_BtoS:
    case AArch64::SDOT_VG2_M2Z2Z_HtoD:
    case AArch64::SDOT_VG2_M2Z2Z_HtoS:
    case AArch64::SUB_VG2_M2Z2Z_D:
    case AArch64::SUB_VG2_M2Z2Z_S:
    case AArch64::UDOT_VG2_M2Z2Z_BtoS:
    case AArch64::UDOT_VG2_M2Z2Z_HtoD:
    case AArch64::UDOT_VG2_M2Z2Z_HtoS:
    case AArch64::USDOT_VG2_M2Z2Z_BToS: {
      // op: Zm
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 5, Fixups, STI);
      Value |= (op & 0xf) << 17;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::BFMAXNM_VG4_4Z2Z_H:
    case AArch64::BFMAX_VG4_4Z2Z_H:
    case AArch64::BFMINNM_VG4_4Z2Z_H:
    case AArch64::BFMIN_VG4_4Z2Z_H:
    case AArch64::BFSCALE_4Z4Z:
    case AArch64::FAMAX_4Z4Z_D:
    case AArch64::FAMAX_4Z4Z_H:
    case AArch64::FAMAX_4Z4Z_S:
    case AArch64::FAMIN_4Z4Z_D:
    case AArch64::FAMIN_4Z4Z_H:
    case AArch64::FAMIN_4Z4Z_S:
    case AArch64::FMAXNM_VG4_4Z4Z_D:
    case AArch64::FMAXNM_VG4_4Z4Z_H:
    case AArch64::FMAXNM_VG4_4Z4Z_S:
    case AArch64::FMAX_VG4_4Z4Z_D:
    case AArch64::FMAX_VG4_4Z4Z_H:
    case AArch64::FMAX_VG4_4Z4Z_S:
    case AArch64::FMINNM_VG4_4Z4Z_D:
    case AArch64::FMINNM_VG4_4Z4Z_H:
    case AArch64::FMINNM_VG4_4Z4Z_S:
    case AArch64::FMIN_VG4_4Z4Z_D:
    case AArch64::FMIN_VG4_4Z4Z_H:
    case AArch64::FMIN_VG4_4Z4Z_S:
    case AArch64::FSCALE_4Z4Z_D:
    case AArch64::FSCALE_4Z4Z_H:
    case AArch64::FSCALE_4Z4Z_S:
    case AArch64::SMAX_VG4_4Z4Z_B:
    case AArch64::SMAX_VG4_4Z4Z_D:
    case AArch64::SMAX_VG4_4Z4Z_H:
    case AArch64::SMAX_VG4_4Z4Z_S:
    case AArch64::SMIN_VG4_4Z4Z_B:
    case AArch64::SMIN_VG4_4Z4Z_D:
    case AArch64::SMIN_VG4_4Z4Z_H:
    case AArch64::SMIN_VG4_4Z4Z_S:
    case AArch64::SQDMULH_VG4_4Z4Z_B:
    case AArch64::SQDMULH_VG4_4Z4Z_D:
    case AArch64::SQDMULH_VG4_4Z4Z_H:
    case AArch64::SQDMULH_VG4_4Z4Z_S:
    case AArch64::SRSHL_VG4_4Z4Z_B:
    case AArch64::SRSHL_VG4_4Z4Z_D:
    case AArch64::SRSHL_VG4_4Z4Z_H:
    case AArch64::SRSHL_VG4_4Z4Z_S:
    case AArch64::UMAX_VG4_4Z4Z_B:
    case AArch64::UMAX_VG4_4Z4Z_D:
    case AArch64::UMAX_VG4_4Z4Z_H:
    case AArch64::UMAX_VG4_4Z4Z_S:
    case AArch64::UMIN_VG4_4Z4Z_B:
    case AArch64::UMIN_VG4_4Z4Z_D:
    case AArch64::UMIN_VG4_4Z4Z_H:
    case AArch64::UMIN_VG4_4Z4Z_S:
    case AArch64::URSHL_VG4_4Z4Z_B:
    case AArch64::URSHL_VG4_4Z4Z_D:
    case AArch64::URSHL_VG4_4Z4Z_H:
    case AArch64::URSHL_VG4_4Z4Z_S: {
      // op: Zm
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 2, Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: Zdn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case AArch64::FMLALL_VG4_M4Z4Z_BtoS:
    case AArch64::SMLALL_VG4_M4Z4Z_BtoS:
    case AArch64::SMLALL_VG4_M4Z4Z_HtoD:
    case AArch64::SMLSLL_VG4_M4Z4Z_BtoS:
    case AArch64::SMLSLL_VG4_M4Z4Z_HtoD:
    case AArch64::UMLALL_VG4_M4Z4Z_BtoS:
    case AArch64::UMLALL_VG4_M4Z4Z_HtoD:
    case AArch64::UMLSLL_VG4_M4Z4Z_BtoS:
    case AArch64::UMLSLL_VG4_M4Z4Z_HtoD:
    case AArch64::USMLALL_VG4_M4Z4Z_BtoS: {
      // op: Zm
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 5, Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      break;
    }
    case AArch64::ADD_VG4_M4Z4Z_D:
    case AArch64::ADD_VG4_M4Z4Z_S:
    case AArch64::BFDOT_VG4_M4Z4Z_HtoS:
    case AArch64::BFMLA_VG4_M4Z4Z:
    case AArch64::BFMLS_VG4_M4Z4Z:
    case AArch64::FDOT_VG4_M4Z4Z_BtoH:
    case AArch64::FDOT_VG4_M4Z4Z_BtoS:
    case AArch64::FDOT_VG4_M4Z4Z_HtoS:
    case AArch64::FMLA_VG4_M4Z4Z_D:
    case AArch64::FMLA_VG4_M4Z4Z_H:
    case AArch64::FMLA_VG4_M4Z4Z_S:
    case AArch64::FMLS_VG4_M4Z4Z_D:
    case AArch64::FMLS_VG4_M4Z4Z_H:
    case AArch64::FMLS_VG4_M4Z4Z_S:
    case AArch64::SDOT_VG4_M4Z4Z_BtoS:
    case AArch64::SDOT_VG4_M4Z4Z_HtoD:
    case AArch64::SDOT_VG4_M4Z4Z_HtoS:
    case AArch64::SUB_VG4_M4Z4Z_D:
    case AArch64::SUB_VG4_M4Z4Z_S:
    case AArch64::UDOT_VG4_M4Z4Z_BtoS:
    case AArch64::UDOT_VG4_M4Z4Z_HtoD:
    case AArch64::UDOT_VG4_M4Z4Z_HtoS:
    case AArch64::USDOT_VG4_M4Z4Z_BToS: {
      // op: Zm
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 5, Fixups, STI);
      Value |= (op & 0x7) << 18;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::PMULL_2ZZZ_Q: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::AESDIMC_2ZZI_B:
    case AArch64::AESD_2ZZI_B:
    case AArch64::AESEMC_2ZZI_B:
    case AArch64::AESE_2ZZI_B: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zdn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::AESDIMC_4ZZI_B:
    case AArch64::AESD_4ZZI_B:
    case AArch64::AESEMC_4ZZI_B:
    case AArch64::AESE_4ZZI_B: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zdn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::ADD_VG2_2ZZ_B:
    case AArch64::ADD_VG2_2ZZ_D:
    case AArch64::ADD_VG2_2ZZ_H:
    case AArch64::ADD_VG2_2ZZ_S:
    case AArch64::BFMAXNM_VG2_2ZZ_H:
    case AArch64::BFMAX_VG2_2ZZ_H:
    case AArch64::BFMINNM_VG2_2ZZ_H:
    case AArch64::BFMIN_VG2_2ZZ_H:
    case AArch64::BFSCALE_2ZZ:
    case AArch64::FMAXNM_VG2_2ZZ_D:
    case AArch64::FMAXNM_VG2_2ZZ_H:
    case AArch64::FMAXNM_VG2_2ZZ_S:
    case AArch64::FMAX_VG2_2ZZ_D:
    case AArch64::FMAX_VG2_2ZZ_H:
    case AArch64::FMAX_VG2_2ZZ_S:
    case AArch64::FMINNM_VG2_2ZZ_D:
    case AArch64::FMINNM_VG2_2ZZ_H:
    case AArch64::FMINNM_VG2_2ZZ_S:
    case AArch64::FMIN_VG2_2ZZ_D:
    case AArch64::FMIN_VG2_2ZZ_H:
    case AArch64::FMIN_VG2_2ZZ_S:
    case AArch64::FSCALE_2ZZ_D:
    case AArch64::FSCALE_2ZZ_H:
    case AArch64::FSCALE_2ZZ_S:
    case AArch64::SMAX_VG2_2ZZ_B:
    case AArch64::SMAX_VG2_2ZZ_D:
    case AArch64::SMAX_VG2_2ZZ_H:
    case AArch64::SMAX_VG2_2ZZ_S:
    case AArch64::SMIN_VG2_2ZZ_B:
    case AArch64::SMIN_VG2_2ZZ_D:
    case AArch64::SMIN_VG2_2ZZ_H:
    case AArch64::SMIN_VG2_2ZZ_S:
    case AArch64::SQDMULH_VG2_2ZZ_B:
    case AArch64::SQDMULH_VG2_2ZZ_D:
    case AArch64::SQDMULH_VG2_2ZZ_H:
    case AArch64::SQDMULH_VG2_2ZZ_S:
    case AArch64::SRSHL_VG2_2ZZ_B:
    case AArch64::SRSHL_VG2_2ZZ_D:
    case AArch64::SRSHL_VG2_2ZZ_H:
    case AArch64::SRSHL_VG2_2ZZ_S:
    case AArch64::UMAX_VG2_2ZZ_B:
    case AArch64::UMAX_VG2_2ZZ_D:
    case AArch64::UMAX_VG2_2ZZ_H:
    case AArch64::UMAX_VG2_2ZZ_S:
    case AArch64::UMIN_VG2_2ZZ_B:
    case AArch64::UMIN_VG2_2ZZ_D:
    case AArch64::UMIN_VG2_2ZZ_H:
    case AArch64::UMIN_VG2_2ZZ_S:
    case AArch64::URSHL_VG2_2ZZ_B:
    case AArch64::URSHL_VG2_2ZZ_D:
    case AArch64::URSHL_VG2_2ZZ_H:
    case AArch64::URSHL_VG2_2ZZ_S: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Zdn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::ADD_VG4_4ZZ_B:
    case AArch64::ADD_VG4_4ZZ_D:
    case AArch64::ADD_VG4_4ZZ_H:
    case AArch64::ADD_VG4_4ZZ_S:
    case AArch64::BFMAXNM_VG4_4ZZ_H:
    case AArch64::BFMAX_VG4_4ZZ_H:
    case AArch64::BFMINNM_VG4_4ZZ_H:
    case AArch64::BFMIN_VG4_4ZZ_H:
    case AArch64::BFSCALE_4ZZ:
    case AArch64::FMAXNM_VG4_4ZZ_D:
    case AArch64::FMAXNM_VG4_4ZZ_H:
    case AArch64::FMAXNM_VG4_4ZZ_S:
    case AArch64::FMAX_VG4_4ZZ_D:
    case AArch64::FMAX_VG4_4ZZ_H:
    case AArch64::FMAX_VG4_4ZZ_S:
    case AArch64::FMINNM_VG4_4ZZ_D:
    case AArch64::FMINNM_VG4_4ZZ_H:
    case AArch64::FMINNM_VG4_4ZZ_S:
    case AArch64::FMIN_VG4_4ZZ_D:
    case AArch64::FMIN_VG4_4ZZ_H:
    case AArch64::FMIN_VG4_4ZZ_S:
    case AArch64::FSCALE_4ZZ_D:
    case AArch64::FSCALE_4ZZ_H:
    case AArch64::FSCALE_4ZZ_S:
    case AArch64::SMAX_VG4_4ZZ_B:
    case AArch64::SMAX_VG4_4ZZ_D:
    case AArch64::SMAX_VG4_4ZZ_H:
    case AArch64::SMAX_VG4_4ZZ_S:
    case AArch64::SMIN_VG4_4ZZ_B:
    case AArch64::SMIN_VG4_4ZZ_D:
    case AArch64::SMIN_VG4_4ZZ_H:
    case AArch64::SMIN_VG4_4ZZ_S:
    case AArch64::SQDMULH_VG4_4ZZ_B:
    case AArch64::SQDMULH_VG4_4ZZ_D:
    case AArch64::SQDMULH_VG4_4ZZ_H:
    case AArch64::SQDMULH_VG4_4ZZ_S:
    case AArch64::SRSHL_VG4_4ZZ_B:
    case AArch64::SRSHL_VG4_4ZZ_D:
    case AArch64::SRSHL_VG4_4ZZ_H:
    case AArch64::SRSHL_VG4_4ZZ_S:
    case AArch64::UMAX_VG4_4ZZ_B:
    case AArch64::UMAX_VG4_4ZZ_D:
    case AArch64::UMAX_VG4_4ZZ_H:
    case AArch64::UMAX_VG4_4ZZ_S:
    case AArch64::UMIN_VG4_4ZZ_B:
    case AArch64::UMIN_VG4_4ZZ_D:
    case AArch64::UMIN_VG4_4ZZ_H:
    case AArch64::UMIN_VG4_4ZZ_S:
    case AArch64::URSHL_VG4_4ZZ_B:
    case AArch64::URSHL_VG4_4ZZ_D:
    case AArch64::URSHL_VG4_4ZZ_H:
    case AArch64::URSHL_VG4_4ZZ_S: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Zdn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case AArch64::BFCLAMP_VG2_2ZZZ_H:
    case AArch64::FCLAMP_VG2_2Z2Z_D:
    case AArch64::FCLAMP_VG2_2Z2Z_H:
    case AArch64::FCLAMP_VG2_2Z2Z_S:
    case AArch64::SCLAMP_VG2_2Z2Z_B:
    case AArch64::SCLAMP_VG2_2Z2Z_D:
    case AArch64::SCLAMP_VG2_2Z2Z_H:
    case AArch64::SCLAMP_VG2_2Z2Z_S:
    case AArch64::UCLAMP_VG2_2Z2Z_B:
    case AArch64::UCLAMP_VG2_2Z2Z_D:
    case AArch64::UCLAMP_VG2_2Z2Z_H:
    case AArch64::UCLAMP_VG2_2Z2Z_S: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::BFCLAMP_VG4_4ZZZ_H:
    case AArch64::FCLAMP_VG4_4Z4Z_D:
    case AArch64::FCLAMP_VG4_4Z4Z_H:
    case AArch64::FCLAMP_VG4_4Z4Z_S:
    case AArch64::SCLAMP_VG4_4Z4Z_B:
    case AArch64::SCLAMP_VG4_4Z4Z_D:
    case AArch64::SCLAMP_VG4_4Z4Z_H:
    case AArch64::SCLAMP_VG4_4Z4Z_S:
    case AArch64::UCLAMP_VG4_4Z4Z_B:
    case AArch64::UCLAMP_VG4_4Z4Z_D:
    case AArch64::UCLAMP_VG4_4Z4Z_H:
    case AArch64::UCLAMP_VG4_4Z4Z_S: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case AArch64::BFCLAMP_ZZZ:
    case AArch64::FCLAMP_ZZZ_D:
    case AArch64::FCLAMP_ZZZ_H:
    case AArch64::FCLAMP_ZZZ_S:
    case AArch64::SCLAMP_ZZZ_B:
    case AArch64::SCLAMP_ZZZ_D:
    case AArch64::SCLAMP_ZZZ_H:
    case AArch64::SCLAMP_ZZZ_S:
    case AArch64::UCLAMP_ZZZ_B:
    case AArch64::UCLAMP_ZZZ_D:
    case AArch64::UCLAMP_ZZZ_H:
    case AArch64::UCLAMP_ZZZ_S: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::PMLAL_2ZZZ_Q: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zda
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::BFMOPA_MPPZZ_H:
    case AArch64::BFMOPS_MPPZZ_H:
    case AArch64::FMOPA_MPPZZ_BtoH:
    case AArch64::FMOPA_MPPZZ_H:
    case AArch64::FMOPS_MPPZZ_H: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 13;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1);
      break;
    }
    case AArch64::BFMOPA_MPPZZ:
    case AArch64::BFMOPS_MPPZZ:
    case AArch64::BMOPA_MPPZZ_S:
    case AArch64::BMOPS_MPPZZ_S:
    case AArch64::FMOPAL_MPPZZ:
    case AArch64::FMOPA_MPPZZ_BtoS:
    case AArch64::FMOPA_MPPZZ_S:
    case AArch64::FMOPSL_MPPZZ:
    case AArch64::FMOPS_MPPZZ_S:
    case AArch64::SMOPA_MPPZZ_HtoS:
    case AArch64::SMOPA_MPPZZ_S:
    case AArch64::SMOPS_MPPZZ_HtoS:
    case AArch64::SMOPS_MPPZZ_S:
    case AArch64::SUMOPA_MPPZZ_S:
    case AArch64::SUMOPS_MPPZZ_S:
    case AArch64::UMOPA_MPPZZ_HtoS:
    case AArch64::UMOPA_MPPZZ_S:
    case AArch64::UMOPS_MPPZZ_HtoS:
    case AArch64::UMOPS_MPPZZ_S:
    case AArch64::USMOPA_MPPZZ_S:
    case AArch64::USMOPS_MPPZZ_S: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 13;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::FMOPA_MPPZZ_D:
    case AArch64::FMOPS_MPPZZ_D:
    case AArch64::SMOPA_MPPZZ_D:
    case AArch64::SMOPS_MPPZZ_D:
    case AArch64::SUMOPA_MPPZZ_D:
    case AArch64::SUMOPS_MPPZZ_D:
    case AArch64::UMOPA_MPPZZ_D:
    case AArch64::UMOPS_MPPZZ_D:
    case AArch64::USMOPA_MPPZZ_D:
    case AArch64::USMOPS_MPPZZ_D: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Pm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 13;
      // op: Pn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: ZAda
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::FVDOTB_VG4_M2ZZI_BtoS:
    case AArch64::FVDOTT_VG4_M2ZZI_BtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x2) << 9;
      Value |= (op & 0x1) << 3;
      break;
    }
    case AArch64::BFDOT_VG2_M2ZZI_HtoS:
    case AArch64::BFVDOT_VG2_M2ZZI_HtoS:
    case AArch64::FDOT_VG2_M2ZZI_BtoS:
    case AArch64::FDOT_VG2_M2ZZI_HtoS:
    case AArch64::FMLA_VG2_M2ZZI_S:
    case AArch64::FMLS_VG2_M2ZZI_S:
    case AArch64::FVDOT_VG2_M2ZZI_HtoS:
    case AArch64::SDOT_VG2_M2ZZI_BToS:
    case AArch64::SDOT_VG2_M2ZZI_HToS:
    case AArch64::SUDOT_VG2_M2ZZI_BToS:
    case AArch64::SVDOT_VG2_M2ZZI_HtoS:
    case AArch64::UDOT_VG2_M2ZZI_BToS:
    case AArch64::UDOT_VG2_M2ZZI_HToS:
    case AArch64::USDOT_VG2_M2ZZI_BToS:
    case AArch64::UVDOT_VG2_M2ZZI_HtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x3) << 10;
      break;
    }
    case AArch64::BFMLA_VG2_M2ZZI:
    case AArch64::BFMLS_VG2_M2ZZI:
    case AArch64::FDOT_VG2_M2ZZI_BtoH:
    case AArch64::FMLA_VG2_M2ZZI_H:
    case AArch64::FMLS_VG2_M2ZZI_H:
    case AArch64::FVDOT_VG2_M2ZZI_BtoH: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x6) << 9;
      Value |= (op & 0x1) << 3;
      break;
    }
    case AArch64::BFDOT_VG4_M4ZZI_HtoS:
    case AArch64::FDOT_VG4_M4ZZI_BtoS:
    case AArch64::FDOT_VG4_M4ZZI_HtoS:
    case AArch64::FMLA_VG4_M4ZZI_S:
    case AArch64::FMLS_VG4_M4ZZI_S:
    case AArch64::SDOT_VG4_M4ZZI_BToS:
    case AArch64::SDOT_VG4_M4ZZI_HToS:
    case AArch64::SUDOT_VG4_M4ZZI_BToS:
    case AArch64::SUVDOT_VG4_M4ZZI_BToS:
    case AArch64::SVDOT_VG4_M4ZZI_BtoS:
    case AArch64::UDOT_VG4_M4ZZI_BtoS:
    case AArch64::UDOT_VG4_M4ZZI_HToS:
    case AArch64::USDOT_VG4_M4ZZI_BToS:
    case AArch64::USVDOT_VG4_M4ZZI_BToS:
    case AArch64::UVDOT_VG4_M4ZZI_BtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x3) << 10;
      break;
    }
    case AArch64::BFMLA_VG4_M4ZZI:
    case AArch64::BFMLS_VG4_M4ZZI:
    case AArch64::FDOT_VG4_M4ZZI_BtoH:
    case AArch64::FMLA_VG4_M4ZZI_H:
    case AArch64::FMLS_VG4_M4ZZI_H: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x6) << 9;
      Value |= (op & 0x1) << 3;
      break;
    }
    case AArch64::FMLALL_VG2_M2ZZ_BtoS:
    case AArch64::FMLALL_VG4_M4ZZ_BtoS:
    case AArch64::SMLALL_VG2_M2ZZ_BtoS:
    case AArch64::SMLALL_VG2_M2ZZ_HtoD:
    case AArch64::SMLALL_VG4_M4ZZ_BtoS:
    case AArch64::SMLALL_VG4_M4ZZ_HtoD:
    case AArch64::SMLSLL_VG2_M2ZZ_BtoS:
    case AArch64::SMLSLL_VG2_M2ZZ_HtoD:
    case AArch64::SMLSLL_VG4_M4ZZ_BtoS:
    case AArch64::SMLSLL_VG4_M4ZZ_HtoD:
    case AArch64::SUMLALL_VG2_M2ZZ_BtoS:
    case AArch64::SUMLALL_VG4_M4ZZ_BtoS:
    case AArch64::UMLALL_VG2_M2ZZ_BtoS:
    case AArch64::UMLALL_VG2_M2ZZ_HtoD:
    case AArch64::UMLALL_VG4_M4ZZ_BtoS:
    case AArch64::UMLALL_VG4_M4ZZ_HtoD:
    case AArch64::UMLSLL_VG2_M2ZZ_BtoS:
    case AArch64::UMLSLL_VG2_M2ZZ_HtoD:
    case AArch64::UMLSLL_VG4_M4ZZ_BtoS:
    case AArch64::UMLSLL_VG4_M4ZZ_HtoD:
    case AArch64::USMLALL_VG2_M2ZZ_BtoS:
    case AArch64::USMLALL_VG4_M4ZZ_BtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      break;
    }
    case AArch64::FMLALL_MZZ_BtoS:
    case AArch64::SMLALL_MZZ_BtoS:
    case AArch64::SMLALL_MZZ_HtoD:
    case AArch64::SMLSLL_MZZ_BtoS:
    case AArch64::SMLSLL_MZZ_HtoD:
    case AArch64::UMLALL_MZZ_BtoS:
    case AArch64::UMLALL_MZZ_HtoD:
    case AArch64::UMLSLL_MZZ_BtoS:
    case AArch64::UMLSLL_MZZ_HtoD:
    case AArch64::USMLALL_MZZ_BtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::SMLALL_MZZI_HtoD:
    case AArch64::SMLSLL_MZZI_HtoD:
    case AArch64::UMLALL_MZZI_HtoD:
    case AArch64::UMLSLL_MZZI_HtoD: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x4) << 13;
      Value |= (op & 0x3) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::SMLALL_VG2_M2ZZI_HtoD:
    case AArch64::SMLSLL_VG2_M2ZZI_HtoD:
    case AArch64::UMLALL_VG2_M2ZZI_HtoD:
    case AArch64::UMLSLL_VG2_M2ZZI_HtoD: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x4) << 8;
      Value |= (op & 0x3) << 1;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      break;
    }
    case AArch64::SMLALL_VG4_M4ZZI_HtoD:
    case AArch64::SMLSLL_VG4_M4ZZI_HtoD:
    case AArch64::UMLALL_VG4_M4ZZI_HtoD:
    case AArch64::UMLSLL_VG4_M4ZZI_HtoD: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x4) << 8;
      Value |= (op & 0x3) << 1;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      break;
    }
    case AArch64::FMLAL_MZZI_BtoH: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x8) << 12;
      Value |= (op & 0x6) << 9;
      Value |= (op & 0x1) << 3;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::FMLALL_MZZI_BtoS:
    case AArch64::SMLALL_MZZI_BtoS:
    case AArch64::SMLSLL_MZZI_BtoS:
    case AArch64::SUMLALL_MZZI_BtoS:
    case AArch64::UMLALL_MZZI_BtoS:
    case AArch64::UMLSLL_MZZI_BtoS:
    case AArch64::USMLALL_MZZI_BtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x8) << 12;
      Value |= (op & 0x7) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::FMLALL_VG2_M2ZZI_BtoS:
    case AArch64::SMLALL_VG2_M2ZZI_BtoS:
    case AArch64::SMLSLL_VG2_M2ZZI_BtoS:
    case AArch64::SUMLALL_VG2_M2ZZI_BtoS:
    case AArch64::UMLALL_VG2_M2ZZI_BtoS:
    case AArch64::UMLSLL_VG2_M2ZZI_BtoS:
    case AArch64::USMLALL_VG2_M2ZZI_BtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0xc) << 8;
      Value |= (op & 0x3) << 1;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      break;
    }
    case AArch64::FMLALL_VG4_M4ZZI_BtoS:
    case AArch64::SMLALL_VG4_M4ZZI_BtoS:
    case AArch64::SMLSLL_VG4_M4ZZI_BtoS:
    case AArch64::SUMLALL_VG4_M4ZZI_BtoS:
    case AArch64::UMLALL_VG4_M4ZZI_BtoS:
    case AArch64::UMLSLL_VG4_M4ZZI_BtoS:
    case AArch64::USMLALL_VG4_M4ZZI_BtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0xc) << 8;
      Value |= (op & 0x3) << 1;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1);
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      break;
    }
    case AArch64::FMLAL_VG2_M2ZZI_BtoH: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0xc) << 8;
      Value |= (op & 0x3) << 2;
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      break;
    }
    case AArch64::FMLAL_VG4_M4ZZI_BtoH: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0xc) << 8;
      Value |= (op & 0x3) << 2;
      // op: imm2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      break;
    }
    case AArch64::FMLA_VG2_M2ZZI_D:
    case AArch64::FMLS_VG2_M2ZZI_D:
    case AArch64::SDOT_VG2_M2ZZI_HtoD:
    case AArch64::UDOT_VG2_M2ZZI_HtoD: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i1
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x1) << 10;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::FMLA_VG4_M4ZZI_D:
    case AArch64::FMLS_VG4_M4ZZI_D:
    case AArch64::SDOT_VG4_M4ZZI_HtoD:
    case AArch64::SVDOT_VG4_M4ZZI_HtoD:
    case AArch64::UDOT_VG4_M4ZZI_HtoD:
    case AArch64::UVDOT_VG4_M4ZZI_HtoD: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i1
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x1) << 10;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::BFMLAL_MZZI_HtoS:
    case AArch64::BFMLSL_MZZI_HtoS:
    case AArch64::FMLAL_MZZI_HtoS:
    case AArch64::FMLSL_MZZI_HtoS:
    case AArch64::SMLAL_MZZI_HtoS:
    case AArch64::SMLSL_MZZI_HtoS:
    case AArch64::UMLAL_MZZI_HtoS:
    case AArch64::UMLSL_MZZI_HtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i3
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x4) << 13;
      Value |= (op & 0x3) << 10;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::BFMLAL_VG2_M2ZZI_HtoS:
    case AArch64::BFMLSL_VG2_M2ZZI_HtoS:
    case AArch64::FMLAL_VG2_M2ZZI_HtoS:
    case AArch64::FMLSL_VG2_M2ZZI_HtoS:
    case AArch64::SMLAL_VG2_M2ZZI_S:
    case AArch64::SMLSL_VG2_M2ZZI_S:
    case AArch64::UMLAL_VG2_M2ZZI_S:
    case AArch64::UMLSL_VG2_M2ZZI_S: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i3
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x6) << 9;
      Value |= (op & 0x1) << 2;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 4, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::BFMLAL_VG4_M4ZZI_HtoS:
    case AArch64::BFMLSL_VG4_M4ZZI_HtoS:
    case AArch64::FMLAL_VG4_M4ZZI_HtoS:
    case AArch64::FMLSL_VG4_M4ZZI_HtoS:
    case AArch64::SMLAL_VG4_M4ZZI_HtoS:
    case AArch64::SMLSL_VG4_M4ZZI_HtoS:
    case AArch64::UMLAL_VG4_M4ZZI_HtoS:
    case AArch64::UMLSL_VG4_M4ZZI_HtoS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: i3
      op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI);
      Value |= (op & 0x6) << 9;
      Value |= (op & 0x1) << 2;
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 4, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3);
      break;
    }
    case AArch64::ADD_VG2_M2ZZ_D:
    case AArch64::ADD_VG2_M2ZZ_S:
    case AArch64::ADD_VG4_M4ZZ_D:
    case AArch64::ADD_VG4_M4ZZ_S:
    case AArch64::BFDOT_VG2_M2ZZ_HtoS:
    case AArch64::BFDOT_VG4_M4ZZ_HtoS:
    case AArch64::BFMLA_VG2_M2ZZ:
    case AArch64::BFMLA_VG4_M4ZZ:
    case AArch64::BFMLS_VG2_M2ZZ:
    case AArch64::BFMLS_VG4_M4ZZ:
    case AArch64::FDOT_VG2_M2ZZ_BtoH:
    case AArch64::FDOT_VG2_M2ZZ_BtoS:
    case AArch64::FDOT_VG2_M2ZZ_HtoS:
    case AArch64::FDOT_VG4_M4ZZ_BtoH:
    case AArch64::FDOT_VG4_M4ZZ_BtoS:
    case AArch64::FDOT_VG4_M4ZZ_HtoS:
    case AArch64::FMLA_VG2_M2ZZ_D:
    case AArch64::FMLA_VG2_M2ZZ_H:
    case AArch64::FMLA_VG2_M2ZZ_S:
    case AArch64::FMLA_VG4_M4ZZ_D:
    case AArch64::FMLA_VG4_M4ZZ_H:
    case AArch64::FMLA_VG4_M4ZZ_S:
    case AArch64::FMLS_VG2_M2ZZ_D:
    case AArch64::FMLS_VG2_M2ZZ_H:
    case AArch64::FMLS_VG2_M2ZZ_S:
    case AArch64::FMLS_VG4_M4ZZ_D:
    case AArch64::FMLS_VG4_M4ZZ_H:
    case AArch64::FMLS_VG4_M4ZZ_S:
    case AArch64::SDOT_VG2_M2ZZ_BtoS:
    case AArch64::SDOT_VG2_M2ZZ_HtoD:
    case AArch64::SDOT_VG2_M2ZZ_HtoS:
    case AArch64::SDOT_VG4_M4ZZ_BtoS:
    case AArch64::SDOT_VG4_M4ZZ_HtoD:
    case AArch64::SDOT_VG4_M4ZZ_HtoS:
    case AArch64::SUB_VG2_M2ZZ_D:
    case AArch64::SUB_VG2_M2ZZ_S:
    case AArch64::SUB_VG4_M4ZZ_D:
    case AArch64::SUB_VG4_M4ZZ_S:
    case AArch64::SUDOT_VG2_M2ZZ_BToS:
    case AArch64::SUDOT_VG4_M4ZZ_BToS:
    case AArch64::UDOT_VG2_M2ZZ_BtoS:
    case AArch64::UDOT_VG2_M2ZZ_HtoD:
    case AArch64::UDOT_VG2_M2ZZ_HtoS:
    case AArch64::UDOT_VG4_M4ZZ_BtoS:
    case AArch64::UDOT_VG4_M4ZZ_HtoD:
    case AArch64::UDOT_VG4_M4ZZ_HtoS:
    case AArch64::USDOT_VG2_M2ZZ_BToS:
    case AArch64::USDOT_VG4_M4ZZ_BToS: {
      // op: Zm
      op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rv
      op = encodeMatrixIndexGPR32<AArch64::W8>(MI, 2, Fixups, STI);
      Value |= (op & 0x3) << 13;
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7);
      break;
    }
    case AArch64::FCVTZS_2Z2Z_StoS:
    case AArch64::FCVTZU_2Z2Z_StoS:
    case AArch64::FRINTA_2Z2Z_S:
    case AArch64::FRINTM_2Z2Z_S:
    case AArch64::FRINTN_2Z2Z_S:
    case AArch64::FRINTP_2Z2Z_S:
    case AArch64::SCVTF_2Z2Z_StoS:
    case AArch64::UCVTF_2Z2Z_StoS: {
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::SUNPK_VG4_4Z2Z_D:
    case AArch64::SUNPK_VG4_4Z2Z_H:
    case AArch64::SUNPK_VG4_4Z2Z_S:
    case AArch64::UUNPK_VG4_4Z2Z_D:
    case AArch64::UUNPK_VG4_4Z2Z_H:
    case AArch64::UUNPK_VG4_4Z2Z_S: {
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case AArch64::BFCVTN_Z2Z_StoH:
    case AArch64::BFCVT_Z2Z_HtoB:
    case AArch64::BFCVT_Z2Z_StoH:
    case AArch64::FCVTN_Z2Z_StoH:
    case AArch64::FCVT_Z2Z_HtoB:
    case AArch64::FCVT_Z2Z_StoH:
    case AArch64::SQCVTU_Z2Z_StoH:
    case AArch64::SQCVT_Z2Z_StoH:
    case AArch64::UQCVT_Z2Z_StoH: {
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::LUTI4_4ZZT2Z: {
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case AArch64::LUTI4_S_4ZZT2Z: {
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zd
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x4) << 2;
      Value |= (op & 0x3);
      break;
    }
    case AArch64::FCVTZS_4Z4Z_StoS:
    case AArch64::FCVTZU_4Z4Z_StoS:
    case AArch64::FRINTA_4Z4Z_S:
    case AArch64::FRINTM_4Z4Z_S:
    case AArch64::FRINTN_4Z4Z_S:
    case AArch64::FRINTP_4Z4Z_S:
    case AArch64::SCVTF_4Z4Z_StoS:
    case AArch64::UCVTF_4Z4Z_StoS:
    case AArch64::UZP_VG4_4Z4Z_B:
    case AArch64::UZP_VG4_4Z4Z_D:
    case AArch64::UZP_VG4_4Z4Z_H:
    case AArch64::UZP_VG4_4Z4Z_Q:
    case AArch64::UZP_VG4_4Z4Z_S:
    case AArch64::ZIP_VG4_4Z4Z_B:
    case AArch64::ZIP_VG4_4Z4Z_D:
    case AArch64::ZIP_VG4_4Z4Z_H:
    case AArch64::ZIP_VG4_4Z4Z_Q:
    case AArch64::ZIP_VG4_4Z4Z_S: {
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      break;
    }
    case AArch64::FCVTN_Z4Z_StoB:
    case AArch64::FCVT_Z4Z_StoB:
    case AArch64::SQCVTN_Z4Z_DtoH:
    case AArch64::SQCVTN_Z4Z_StoB:
    case AArch64::SQCVTUN_Z4Z_DtoH:
    case AArch64::SQCVTUN_Z4Z_StoB:
    case AArch64::SQCVTU_Z4Z_DtoH:
    case AArch64::SQCVTU_Z4Z_StoB:
    case AArch64::SQCVT_Z4Z_DtoH:
    case AArch64::SQCVT_Z4Z_StoB:
    case AArch64::UQCVTN_Z4Z_DtoH:
    case AArch64::UQCVTN_Z4Z_StoB:
    case AArch64::UQCVT_Z4Z_DtoH:
    case AArch64::UQCVT_Z4Z_StoB: {
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::SQRSHRN_VG4_Z4ZI_B:
    case AArch64::SQRSHRUN_VG4_Z4ZI_B:
    case AArch64::SQRSHRU_VG4_Z4ZI_B:
    case AArch64::SQRSHR_VG4_Z4ZI_B:
    case AArch64::UQRSHRN_VG4_Z4ZI_B:
    case AArch64::UQRSHR_VG4_Z4ZI_B: {
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftR32OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::SQRSHRN_VG4_Z4ZI_H:
    case AArch64::SQRSHRUN_VG4_Z4ZI_H:
    case AArch64::SQRSHRU_VG4_Z4ZI_H:
    case AArch64::SQRSHR_VG4_Z4ZI_H:
    case AArch64::UQRSHRN_VG4_Z4ZI_H:
    case AArch64::UQRSHR_VG4_Z4ZI_H: {
      // op: Zn
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 7;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: imm
      op = getVecShiftR64OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0x20) << 17;
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::BF1CVTL_2ZZ_BtoH:
    case AArch64::BF1CVT_2ZZ_BtoH:
    case AArch64::BF2CVTL_2ZZ_BtoH:
    case AArch64::BF2CVT_2ZZ_BtoH:
    case AArch64::F1CVTL_2ZZ_BtoH:
    case AArch64::F1CVT_2ZZ_BtoH:
    case AArch64::F2CVTL_2ZZ_BtoH:
    case AArch64::F2CVT_2ZZ_BtoH:
    case AArch64::FCVTL_2ZZ_H_S:
    case AArch64::FCVT_2ZZ_H_S:
    case AArch64::SUNPK_VG2_2ZZ_D:
    case AArch64::SUNPK_VG2_2ZZ_H:
    case AArch64::SUNPK_VG2_2ZZ_S:
    case AArch64::UUNPK_VG2_2ZZ_D:
    case AArch64::UUNPK_VG2_2ZZ_H:
    case AArch64::UUNPK_VG2_2ZZ_S: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      break;
    }
    case AArch64::FADDV_VPZ_D:
    case AArch64::FADDV_VPZ_H:
    case AArch64::FADDV_VPZ_S:
    case AArch64::FMAXNMV_VPZ_D:
    case AArch64::FMAXNMV_VPZ_H:
    case AArch64::FMAXNMV_VPZ_S:
    case AArch64::FMAXV_VPZ_D:
    case AArch64::FMAXV_VPZ_H:
    case AArch64::FMAXV_VPZ_S:
    case AArch64::FMINNMV_VPZ_D:
    case AArch64::FMINNMV_VPZ_H:
    case AArch64::FMINNMV_VPZ_S:
    case AArch64::FMINV_VPZ_D:
    case AArch64::FMINV_VPZ_H:
    case AArch64::FMINV_VPZ_S: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Vd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::LUTI4_2ZTZI_B:
    case AArch64::LUTI4_2ZTZI_H:
    case AArch64::LUTI4_2ZTZI_S: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 15;
      break;
    }
    case AArch64::LUTI2_2ZTZI_B:
    case AArch64::LUTI2_2ZTZI_H:
    case AArch64::LUTI2_2ZTZI_S: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 15;
      break;
    }
    case AArch64::LUTI4_4ZTZI_H:
    case AArch64::LUTI4_4ZTZI_S: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 16;
      break;
    }
    case AArch64::LUTI2_4ZTZI_B:
    case AArch64::LUTI2_4ZTZI_H:
    case AArch64::LUTI2_4ZTZI_S: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 16;
      break;
    }
    case AArch64::LUTI4_S_2ZTZI_B:
    case AArch64::LUTI4_S_2ZTZI_H: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeZPR2StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x8) << 1;
      Value |= (op & 0x7);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 15;
      break;
    }
    case AArch64::LUTI2_S_2ZTZI_B:
    case AArch64::LUTI2_S_2ZTZI_H: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeZPR2StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x8) << 1;
      Value |= (op & 0x7);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 15;
      break;
    }
    case AArch64::LUTI4_S_4ZTZI_H: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x4) << 2;
      Value |= (op & 0x3);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1) << 16;
      break;
    }
    case AArch64::LUTI2_S_4ZTZI_B:
    case AArch64::LUTI2_S_4ZTZI_H: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x4) << 2;
      Value |= (op & 0x3);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x3) << 16;
      break;
    }
    case AArch64::LUTI4_ZTZI_B:
    case AArch64::LUTI4_ZTZI_H:
    case AArch64::LUTI4_ZTZI_S: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 14;
      break;
    }
    case AArch64::LUTI2_ZTZI_B:
    case AArch64::LUTI2_ZTZI_H:
    case AArch64::LUTI2_ZTZI_S: {
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: i
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 14;
      break;
    }
    case AArch64::LD1B_2Z:
    case AArch64::LD1D_2Z:
    case AArch64::LD1H_2Z:
    case AArch64::LD1W_2Z:
    case AArch64::LDNT1B_2Z:
    case AArch64::LDNT1D_2Z:
    case AArch64::LDNT1H_2Z:
    case AArch64::LDNT1W_2Z:
    case AArch64::ST1B_2Z:
    case AArch64::ST1D_2Z:
    case AArch64::ST1H_2Z:
    case AArch64::ST1W_2Z:
    case AArch64::STNT1B_2Z:
    case AArch64::STNT1D_2Z:
    case AArch64::STNT1H_2Z:
    case AArch64::STNT1W_2Z: {
      // op: Zt
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::LD1B_2Z_IMM:
    case AArch64::LD1D_2Z_IMM:
    case AArch64::LD1H_2Z_IMM:
    case AArch64::LD1W_2Z_IMM:
    case AArch64::LDNT1B_2Z_IMM:
    case AArch64::LDNT1D_2Z_IMM:
    case AArch64::LDNT1H_2Z_IMM:
    case AArch64::LDNT1W_2Z_IMM:
    case AArch64::ST1B_2Z_IMM:
    case AArch64::ST1D_2Z_IMM:
    case AArch64::ST1H_2Z_IMM:
    case AArch64::ST1W_2Z_IMM:
    case AArch64::STNT1B_2Z_IMM:
    case AArch64::STNT1D_2Z_IMM:
    case AArch64::STNT1H_2Z_IMM:
    case AArch64::STNT1W_2Z_IMM: {
      // op: Zt
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 0, Fixups, STI);
      Value |= (op & 0xf) << 1;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::LD1B_4Z:
    case AArch64::LD1D_4Z:
    case AArch64::LD1H_4Z:
    case AArch64::LD1W_4Z:
    case AArch64::LDNT1B_4Z:
    case AArch64::LDNT1D_4Z:
    case AArch64::LDNT1H_4Z:
    case AArch64::LDNT1W_4Z:
    case AArch64::ST1B_4Z:
    case AArch64::ST1D_4Z:
    case AArch64::ST1H_4Z:
    case AArch64::ST1W_4Z:
    case AArch64::STNT1B_4Z:
    case AArch64::STNT1D_4Z:
    case AArch64::STNT1H_4Z:
    case AArch64::STNT1W_4Z: {
      // op: Zt
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      break;
    }
    case AArch64::LD1B_4Z_IMM:
    case AArch64::LD1D_4Z_IMM:
    case AArch64::LD1H_4Z_IMM:
    case AArch64::LD1W_4Z_IMM:
    case AArch64::LDNT1B_4Z_IMM:
    case AArch64::LDNT1D_4Z_IMM:
    case AArch64::LDNT1H_4Z_IMM:
    case AArch64::LDNT1W_4Z_IMM:
    case AArch64::ST1B_4Z_IMM:
    case AArch64::ST1D_4Z_IMM:
    case AArch64::ST1H_4Z_IMM:
    case AArch64::ST1W_4Z_IMM:
    case AArch64::STNT1B_4Z_IMM:
    case AArch64::STNT1D_4Z_IMM:
    case AArch64::STNT1H_4Z_IMM:
    case AArch64::STNT1W_4Z_IMM: {
      // op: Zt
      op = EncodeRegMul_MinMax<4, 0, 28>(MI, 0, Fixups, STI);
      Value |= (op & 0x7) << 2;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::LD1B:
    case AArch64::LD1B_D:
    case AArch64::LD1B_H:
    case AArch64::LD1B_S:
    case AArch64::LD1D:
    case AArch64::LD1H:
    case AArch64::LD1H_D:
    case AArch64::LD1H_S:
    case AArch64::LD1SB_D:
    case AArch64::LD1SB_H:
    case AArch64::LD1SB_S:
    case AArch64::LD1SH_D:
    case AArch64::LD1SH_S:
    case AArch64::LD1SW_D:
    case AArch64::LD1W:
    case AArch64::LD1W_D:
    case AArch64::LDFF1B:
    case AArch64::LDFF1B_D:
    case AArch64::LDFF1B_H:
    case AArch64::LDFF1B_S:
    case AArch64::LDFF1D:
    case AArch64::LDFF1H:
    case AArch64::LDFF1H_D:
    case AArch64::LDFF1H_S:
    case AArch64::LDFF1SB_D:
    case AArch64::LDFF1SB_H:
    case AArch64::LDFF1SB_S:
    case AArch64::LDFF1SH_D:
    case AArch64::LDFF1SH_S:
    case AArch64::LDFF1SW_D:
    case AArch64::LDFF1W:
    case AArch64::LDFF1W_D: {
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      break;
    }
    case AArch64::LD1RO_B:
    case AArch64::LD1RO_D:
    case AArch64::LD1RO_H:
    case AArch64::LD1RO_W:
    case AArch64::LD1RQ_B:
    case AArch64::LD1RQ_D:
    case AArch64::LD1RQ_H:
    case AArch64::LD1RQ_W: {
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LD2B_IMM:
    case AArch64::LD2D_IMM:
    case AArch64::LD2H_IMM:
    case AArch64::LD2Q_IMM:
    case AArch64::LD2W_IMM:
    case AArch64::LD3B_IMM:
    case AArch64::LD3D_IMM:
    case AArch64::LD3H_IMM:
    case AArch64::LD3Q_IMM:
    case AArch64::LD3W_IMM:
    case AArch64::LD4B_IMM:
    case AArch64::LD4D_IMM:
    case AArch64::LD4H_IMM:
    case AArch64::LD4Q_IMM:
    case AArch64::LD4W_IMM:
    case AArch64::LDNT1B_ZRI:
    case AArch64::LDNT1D_ZRI:
    case AArch64::LDNT1H_ZRI:
    case AArch64::LDNT1W_ZRI: {
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::LD1D_Q:
    case AArch64::LD1W_Q:
    case AArch64::ST2Q:
    case AArch64::ST3Q:
    case AArch64::ST4Q: {
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::LD1D_Q_IMM:
    case AArch64::LD1RO_B_IMM:
    case AArch64::LD1RO_D_IMM:
    case AArch64::LD1RO_H_IMM:
    case AArch64::LD1RO_W_IMM:
    case AArch64::LD1RQ_B_IMM:
    case AArch64::LD1RQ_D_IMM:
    case AArch64::LD1RQ_H_IMM:
    case AArch64::LD1RQ_W_IMM:
    case AArch64::LD1W_Q_IMM:
    case AArch64::ST2Q_IMM:
    case AArch64::ST3Q_IMM:
    case AArch64::ST4Q_IMM: {
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      break;
    }
    case AArch64::GLD1Q:
    case AArch64::SST1Q: {
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: Zn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Pg
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rm
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x1f) << 16;
      break;
    }
    case AArch64::MOVT_TIZ: {
      // op: Zt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      // op: off2
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x3) << 12;
      break;
    }
    case AArch64::B:
    case AArch64::BL: {
      // op: addr
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
      Value |= (op & 0x3ffffff);
      break;
    }
    case AArch64::BCcc:
    case AArch64::Bcc: {
      // op: cond
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xf);
      // op: target
      op = getCondBranchTargetOpValue(MI, 1, Fixups, STI);
      Value |= (op & 0x7ffff) << 5;
      break;
    }
    case AArch64::DUPi64: {
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: src
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1) << 20;
      break;
    }
    case AArch64::DUPi32: {
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: src
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x3) << 19;
      break;
    }
    case AArch64::DUPi16: {
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: src
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 18;
      break;
    }
    case AArch64::DUPi8: {
      // op: dst
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      // op: src
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: idx
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 17;
      break;
    }
    case AArch64::ZERO_M: {
      // op: imm
      op = EncodeMatrixTileListRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0xff);
      break;
    }
    case AArch64::HINT: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7f) << 5;
      break;
    }
    case AArch64::TENTER: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7f) << 5;
      // op: nb
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1) << 17;
      break;
    }
    case AArch64::BRK:
    case AArch64::DCPS1:
    case AArch64::DCPS2:
    case AArch64::DCPS3:
    case AArch64::HLT:
    case AArch64::HVC:
    case AArch64::SMC:
    case AArch64::SVC: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xffff) << 5;
      break;
    }
    case AArch64::UDF: {
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0xffff);
      break;
    }
    case AArch64::MOVT_TIX: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x7) << 12;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::MOVT_XTI: {
      // op: imm3
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x7) << 12;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::LD1B_2Z_STRIDED_IMM:
    case AArch64::LD1D_2Z_STRIDED_IMM:
    case AArch64::LD1H_2Z_STRIDED_IMM:
    case AArch64::LD1W_2Z_STRIDED_IMM:
    case AArch64::LDNT1B_2Z_STRIDED_IMM:
    case AArch64::LDNT1D_2Z_STRIDED_IMM:
    case AArch64::LDNT1H_2Z_STRIDED_IMM:
    case AArch64::LDNT1W_2Z_STRIDED_IMM:
    case AArch64::ST1B_2Z_STRIDED_IMM:
    case AArch64::ST1D_2Z_STRIDED_IMM:
    case AArch64::ST1H_2Z_STRIDED_IMM:
    case AArch64::ST1W_2Z_STRIDED_IMM:
    case AArch64::STNT1B_2Z_STRIDED_IMM:
    case AArch64::STNT1D_2Z_STRIDED_IMM:
    case AArch64::STNT1H_2Z_STRIDED_IMM:
    case AArch64::STNT1W_2Z_STRIDED_IMM: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = EncodeZPR2StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x8) << 1;
      Value |= (op & 0x7);
      break;
    }
    case AArch64::LD1B_4Z_STRIDED_IMM:
    case AArch64::LD1D_4Z_STRIDED_IMM:
    case AArch64::LD1H_4Z_STRIDED_IMM:
    case AArch64::LD1W_4Z_STRIDED_IMM:
    case AArch64::LDNT1B_4Z_STRIDED_IMM:
    case AArch64::LDNT1D_4Z_STRIDED_IMM:
    case AArch64::LDNT1H_4Z_STRIDED_IMM:
    case AArch64::LDNT1W_4Z_STRIDED_IMM:
    case AArch64::ST1B_4Z_STRIDED_IMM:
    case AArch64::ST1D_4Z_STRIDED_IMM:
    case AArch64::ST1H_4Z_STRIDED_IMM:
    case AArch64::ST1W_4Z_STRIDED_IMM:
    case AArch64::STNT1B_4Z_STRIDED_IMM:
    case AArch64::STNT1D_4Z_STRIDED_IMM:
    case AArch64::STNT1H_4Z_STRIDED_IMM:
    case AArch64::STNT1W_4Z_STRIDED_IMM: {
      // op: imm4
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: PNg
      op = EncodePNR_p8to15(MI, 1, Fixups, STI);
      Value |= (op & 0x7) << 10;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Zt
      op = EncodeZPR4StridedRegisterClass(MI, 0, Fixups, STI);
      Value |= (op & 0x4) << 2;
      Value |= (op & 0x3);
      break;
    }
    case AArch64::SQRSHRU_VG2_Z2ZI_H:
    case AArch64::SQRSHR_VG2_Z2ZI_H:
    case AArch64::UQRSHR_VG2_Z2ZI_H: {
      // op: imm4
      op = getVecShiftR16OpValue(MI, 2, Fixups, STI);
      Value |= (op & 0xf) << 16;
      // op: Zn
      op = EncodeRegMul_MinMax<2, 0, 30>(MI, 1, Fixups, STI);
      Value |= (op & 0xf) << 6;
      // op: Zd
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::AUTIASPPCi:
    case AArch64::AUTIBSPPCi:
    case AArch64::RETAASPPCi:
    case AArch64::RETABSPPCi: {
      // op: label
      op = getPAuthPCRelOpValue(MI, 0, Fixups, STI);
      Value |= (op & 0xffff) << 5;
      break;
    }
    case AArch64::TEXIT: {
      // op: nb
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1) << 10;
      break;
    }
    case AArch64::LDRAAindexed:
    case AArch64::LDRABindexed: {
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x200) << 13;
      Value |= (op & 0x1ff) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::LDRAAwriteback:
    case AArch64::LDRABwriteback: {
      // op: offset
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x200) << 13;
      Value |= (op & 0x1ff) << 12;
      // op: Rn
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0x1f) << 5;
      // op: Rt
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1f);
      break;
    }
    case AArch64::SYSPxt_XZR: {
      // op: op1
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 16;
      // op: Cn
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 12;
      // op: Cm
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
      Value |= (op & 0xf) << 8;
      // op: op2
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::STSHH: {
      // op: policy
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 5;
      break;
    }
    case AArch64::SHUH: {
      // op: priority
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x1) << 5;
      break;
    }
    case AArch64::MSRpstateImm1: {
      // op: pstatefield
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x38) << 13;
      Value |= (op & 0x1c0) << 3;
      Value |= (op & 0x7) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1) << 8;
      break;
    }
    case AArch64::MSRpstateImm4: {
      // op: pstatefield
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x38) << 13;
      Value |= (op & 0x7) << 5;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0xf) << 8;
      break;
    }
    case AArch64::MSRpstatesvcrImm1: {
      // op: pstatefield
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
      Value |= (op & 0x7) << 9;
      // op: imm
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
      Value |= (op & 0x1) << 8;
      break;
    }
  default:
    reportUnsupportedInst(MI);
  }
  return Value;
}

#ifdef GET_OPERAND_BIT_OFFSET
#undef GET_OPERAND_BIT_OFFSET

uint32_t AArch64MCCodeEmitter::getOperandBitOffset(const MCInst &MI,
    unsigned OpNum,
    const MCSubtargetInfo &STI) const {
  switch (MI.getOpcode()) {
    case AArch64::AUTIA1716:
    case AArch64::AUTIA171615:
    case AArch64::AUTIASP:
    case AArch64::AUTIAZ:
    case AArch64::AUTIB1716:
    case AArch64::AUTIB171615:
    case AArch64::AUTIBSP:
    case AArch64::AUTIBZ:
    case AArch64::AXFLAG:
    case AArch64::BRB_IALL:
    case AArch64::BRB_INJ:
    case AArch64::CFINV:
    case AArch64::CHKFEAT:
    case AArch64::DRPS:
    case AArch64::ERET:
    case AArch64::ERETAA:
    case AArch64::ERETAB:
    case AArch64::GCSPOPCX:
    case AArch64::GCSPOPX:
    case AArch64::GCSPUSHX:
    case AArch64::NOP:
    case AArch64::PACIA1716:
    case AArch64::PACIA171615:
    case AArch64::PACIASP:
    case AArch64::PACIASPPC:
    case AArch64::PACIAZ:
    case AArch64::PACIB1716:
    case AArch64::PACIB171615:
    case AArch64::PACIBSP:
    case AArch64::PACIBSPPC:
    case AArch64::PACIBZ:
    case AArch64::PACM:
    case AArch64::PACNBIASPPC:
    case AArch64::PACNBIBSPPC:
    case AArch64::RETAA:
    case AArch64::RETAB:
    case AArch64::SB:
    case AArch64::SETFFR:
    case AArch64::STCPH:
    case AArch64::TSB:
    case AArch64::XAFLAG:
    case AArch64::XPACLRI:
    case AArch64::ZERO_T: {
      break;
    }
    case AArch64::DSBnXS: {
      switch (OpNum) {
      case 0:
        // op: CRm
        return 10;
      }
      break;
    }
    case AArch64::CLREX:
    case AArch64::DMB:
    case AArch64::DSB:
    case AArch64::ISB: {
      switch (OpNum) {
      case 0:
        // op: CRm
        return 8;
      }
      break;
    }
    case AArch64::WHILEGE_CXX_B:
    case AArch64::WHILEGE_CXX_D:
    case AArch64::WHILEGE_CXX_H:
    case AArch64::WHILEGE_CXX_S:
    case AArch64::WHILEGT_CXX_B:
    case AArch64::WHILEGT_CXX_D:
    case AArch64::WHILEGT_CXX_H:
    case AArch64::WHILEGT_CXX_S:
    case AArch64::WHILEHI_CXX_B:
    case AArch64::WHILEHI_CXX_D:
    case AArch64::WHILEHI_CXX_H:
    case AArch64::WHILEHI_CXX_S:
    case AArch64::WHILEHS_CXX_B:
    case AArch64::WHILEHS_CXX_D:
    case AArch64::WHILEHS_CXX_H:
    case AArch64::WHILEHS_CXX_S:
    case AArch64::WHILELE_CXX_B:
    case AArch64::WHILELE_CXX_D:
    case AArch64::WHILELE_CXX_H:
    case AArch64::WHILELE_CXX_S:
    case AArch64::WHILELO_CXX_B:
    case AArch64::WHILELO_CXX_D:
    case AArch64::WHILELO_CXX_H:
    case AArch64::WHILELO_CXX_S:
    case AArch64::WHILELS_CXX_B:
    case AArch64::WHILELS_CXX_D:
    case AArch64::WHILELS_CXX_H:
    case AArch64::WHILELS_CXX_S:
    case AArch64::WHILELT_CXX_B:
    case AArch64::WHILELT_CXX_D:
    case AArch64::WHILELT_CXX_H:
    case AArch64::WHILELT_CXX_S: {
      switch (OpNum) {
      case 0:
        // op: PNd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 3:
        // op: vl
        return 13;
      case 2:
        // op: Rm
        return 16;
      }
      break;
    }
    case AArch64::PTRUE_C_B:
    case AArch64::PTRUE_C_D:
    case AArch64::PTRUE_C_H:
    case AArch64::PTRUE_C_S: {
      switch (OpNum) {
      case 0:
        // op: PNd
        return 0;
      }
      break;
    }
    case AArch64::PEXT_2PCI_B:
    case AArch64::PEXT_2PCI_D:
    case AArch64::PEXT_2PCI_H:
    case AArch64::PEXT_2PCI_S:
    case AArch64::PEXT_PCI_B:
    case AArch64::PEXT_PCI_D:
    case AArch64::PEXT_PCI_H:
    case AArch64::PEXT_PCI_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: PNn
        return 5;
      case 2:
        // op: index
        return 8;
      }
      break;
    }
    case AArch64::BRKAS_PPzP:
    case AArch64::BRKA_PPzP:
    case AArch64::BRKBS_PPzP:
    case AArch64::BRKB_PPzP: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Pn
        return 5;
      }
      break;
    }
    case AArch64::CMPEQ_PPzZI_B:
    case AArch64::CMPEQ_PPzZI_D:
    case AArch64::CMPEQ_PPzZI_H:
    case AArch64::CMPEQ_PPzZI_S:
    case AArch64::CMPGE_PPzZI_B:
    case AArch64::CMPGE_PPzZI_D:
    case AArch64::CMPGE_PPzZI_H:
    case AArch64::CMPGE_PPzZI_S:
    case AArch64::CMPGT_PPzZI_B:
    case AArch64::CMPGT_PPzZI_D:
    case AArch64::CMPGT_PPzZI_H:
    case AArch64::CMPGT_PPzZI_S:
    case AArch64::CMPLE_PPzZI_B:
    case AArch64::CMPLE_PPzZI_D:
    case AArch64::CMPLE_PPzZI_H:
    case AArch64::CMPLE_PPzZI_S:
    case AArch64::CMPLT_PPzZI_B:
    case AArch64::CMPLT_PPzZI_D:
    case AArch64::CMPLT_PPzZI_H:
    case AArch64::CMPLT_PPzZI_S:
    case AArch64::CMPNE_PPzZI_B:
    case AArch64::CMPNE_PPzZI_D:
    case AArch64::CMPNE_PPzZI_H:
    case AArch64::CMPNE_PPzZI_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: imm5
        return 16;
      }
      break;
    }
    case AArch64::CMPHI_PPzZI_B:
    case AArch64::CMPHI_PPzZI_D:
    case AArch64::CMPHI_PPzZI_H:
    case AArch64::CMPHI_PPzZI_S:
    case AArch64::CMPHS_PPzZI_B:
    case AArch64::CMPHS_PPzZI_D:
    case AArch64::CMPHS_PPzZI_H:
    case AArch64::CMPHS_PPzZI_S:
    case AArch64::CMPLO_PPzZI_B:
    case AArch64::CMPLO_PPzZI_D:
    case AArch64::CMPLO_PPzZI_H:
    case AArch64::CMPLO_PPzZI_S:
    case AArch64::CMPLS_PPzZI_B:
    case AArch64::CMPLS_PPzZI_D:
    case AArch64::CMPLS_PPzZI_H:
    case AArch64::CMPLS_PPzZI_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: imm7
        return 14;
      }
      break;
    }
    case AArch64::FCMEQ_PPzZ0_D:
    case AArch64::FCMEQ_PPzZ0_H:
    case AArch64::FCMEQ_PPzZ0_S:
    case AArch64::FCMGE_PPzZ0_D:
    case AArch64::FCMGE_PPzZ0_H:
    case AArch64::FCMGE_PPzZ0_S:
    case AArch64::FCMGT_PPzZ0_D:
    case AArch64::FCMGT_PPzZ0_H:
    case AArch64::FCMGT_PPzZ0_S:
    case AArch64::FCMLE_PPzZ0_D:
    case AArch64::FCMLE_PPzZ0_H:
    case AArch64::FCMLE_PPzZ0_S:
    case AArch64::FCMLT_PPzZ0_D:
    case AArch64::FCMLT_PPzZ0_H:
    case AArch64::FCMLT_PPzZ0_S:
    case AArch64::FCMNE_PPzZ0_D:
    case AArch64::FCMNE_PPzZ0_H:
    case AArch64::FCMNE_PPzZ0_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::ANDS_PPzPP:
    case AArch64::AND_PPzPP:
    case AArch64::BICS_PPzPP:
    case AArch64::BIC_PPzPP:
    case AArch64::BRKPAS_PPzPP:
    case AArch64::BRKPA_PPzPP:
    case AArch64::BRKPBS_PPzPP:
    case AArch64::BRKPB_PPzPP:
    case AArch64::EORS_PPzPP:
    case AArch64::EOR_PPzPP:
    case AArch64::NANDS_PPzPP:
    case AArch64::NAND_PPzPP:
    case AArch64::NORS_PPzPP:
    case AArch64::NOR_PPzPP:
    case AArch64::ORNS_PPzPP:
    case AArch64::ORN_PPzPP:
    case AArch64::ORRS_PPzPP:
    case AArch64::ORR_PPzPP:
    case AArch64::SEL_PPPP: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Pm
        return 16;
      case 2:
        // op: Pn
        return 5;
      }
      break;
    }
    case AArch64::CMPEQ_PPzZZ_B:
    case AArch64::CMPEQ_PPzZZ_D:
    case AArch64::CMPEQ_PPzZZ_H:
    case AArch64::CMPEQ_PPzZZ_S:
    case AArch64::CMPEQ_WIDE_PPzZZ_B:
    case AArch64::CMPEQ_WIDE_PPzZZ_H:
    case AArch64::CMPEQ_WIDE_PPzZZ_S:
    case AArch64::CMPGE_PPzZZ_B:
    case AArch64::CMPGE_PPzZZ_D:
    case AArch64::CMPGE_PPzZZ_H:
    case AArch64::CMPGE_PPzZZ_S:
    case AArch64::CMPGE_WIDE_PPzZZ_B:
    case AArch64::CMPGE_WIDE_PPzZZ_H:
    case AArch64::CMPGE_WIDE_PPzZZ_S:
    case AArch64::CMPGT_PPzZZ_B:
    case AArch64::CMPGT_PPzZZ_D:
    case AArch64::CMPGT_PPzZZ_H:
    case AArch64::CMPGT_PPzZZ_S:
    case AArch64::CMPGT_WIDE_PPzZZ_B:
    case AArch64::CMPGT_WIDE_PPzZZ_H:
    case AArch64::CMPGT_WIDE_PPzZZ_S:
    case AArch64::CMPHI_PPzZZ_B:
    case AArch64::CMPHI_PPzZZ_D:
    case AArch64::CMPHI_PPzZZ_H:
    case AArch64::CMPHI_PPzZZ_S:
    case AArch64::CMPHI_WIDE_PPzZZ_B:
    case AArch64::CMPHI_WIDE_PPzZZ_H:
    case AArch64::CMPHI_WIDE_PPzZZ_S:
    case AArch64::CMPHS_PPzZZ_B:
    case AArch64::CMPHS_PPzZZ_D:
    case AArch64::CMPHS_PPzZZ_H:
    case AArch64::CMPHS_PPzZZ_S:
    case AArch64::CMPHS_WIDE_PPzZZ_B:
    case AArch64::CMPHS_WIDE_PPzZZ_H:
    case AArch64::CMPHS_WIDE_PPzZZ_S:
    case AArch64::CMPLE_WIDE_PPzZZ_B:
    case AArch64::CMPLE_WIDE_PPzZZ_H:
    case AArch64::CMPLE_WIDE_PPzZZ_S:
    case AArch64::CMPLO_WIDE_PPzZZ_B:
    case AArch64::CMPLO_WIDE_PPzZZ_H:
    case AArch64::CMPLO_WIDE_PPzZZ_S:
    case AArch64::CMPLS_WIDE_PPzZZ_B:
    case AArch64::CMPLS_WIDE_PPzZZ_H:
    case AArch64::CMPLS_WIDE_PPzZZ_S:
    case AArch64::CMPLT_WIDE_PPzZZ_B:
    case AArch64::CMPLT_WIDE_PPzZZ_H:
    case AArch64::CMPLT_WIDE_PPzZZ_S:
    case AArch64::CMPNE_PPzZZ_B:
    case AArch64::CMPNE_PPzZZ_D:
    case AArch64::CMPNE_PPzZZ_H:
    case AArch64::CMPNE_PPzZZ_S:
    case AArch64::CMPNE_WIDE_PPzZZ_B:
    case AArch64::CMPNE_WIDE_PPzZZ_H:
    case AArch64::CMPNE_WIDE_PPzZZ_S:
    case AArch64::FACGE_PPzZZ_D:
    case AArch64::FACGE_PPzZZ_H:
    case AArch64::FACGE_PPzZZ_S:
    case AArch64::FACGT_PPzZZ_D:
    case AArch64::FACGT_PPzZZ_H:
    case AArch64::FACGT_PPzZZ_S:
    case AArch64::FCMEQ_PPzZZ_D:
    case AArch64::FCMEQ_PPzZZ_H:
    case AArch64::FCMEQ_PPzZZ_S:
    case AArch64::FCMGE_PPzZZ_D:
    case AArch64::FCMGE_PPzZZ_H:
    case AArch64::FCMGE_PPzZZ_S:
    case AArch64::FCMGT_PPzZZ_D:
    case AArch64::FCMGT_PPzZZ_H:
    case AArch64::FCMGT_PPzZZ_S:
    case AArch64::FCMNE_PPzZZ_D:
    case AArch64::FCMNE_PPzZZ_H:
    case AArch64::FCMNE_PPzZZ_S:
    case AArch64::FCMUO_PPzZZ_D:
    case AArch64::FCMUO_PPzZZ_H:
    case AArch64::FCMUO_PPzZZ_S:
    case AArch64::MATCH_PPzZZ_B:
    case AArch64::MATCH_PPzZZ_H:
    case AArch64::NMATCH_PPzZZ_B:
    case AArch64::NMATCH_PPzZZ_H: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Zm
        return 16;
      case 2:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::RDFFRS_PPz:
    case AArch64::RDFFR_PPz: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Pg
        return 5;
      }
      break;
    }
    case AArch64::PUNPKHI_PP:
    case AArch64::PUNPKLO_PP:
    case AArch64::REV_PP_B:
    case AArch64::REV_PP_D:
    case AArch64::REV_PP_H:
    case AArch64::REV_PP_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Pn
        return 5;
      }
      break;
    }
    case AArch64::PMOV_PZI_D:
    case AArch64::PMOV_PZI_H:
    case AArch64::PMOV_PZI_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: index
        return 17;
      }
      break;
    }
    case AArch64::PMOV_PZI_B: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::PTRUES_B:
    case AArch64::PTRUES_D:
    case AArch64::PTRUES_H:
    case AArch64::PTRUES_S:
    case AArch64::PTRUE_B:
    case AArch64::PTRUE_D:
    case AArch64::PTRUE_H:
    case AArch64::PTRUE_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 1:
        // op: pattern
        return 5;
      }
      break;
    }
    case AArch64::BRKA_PPmP:
    case AArch64::BRKB_PPmP: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 2:
        // op: Pg
        return 10;
      case 3:
        // op: Pn
        return 5;
      }
      break;
    }
    case AArch64::TRN1_PPP_B:
    case AArch64::TRN1_PPP_D:
    case AArch64::TRN1_PPP_H:
    case AArch64::TRN1_PPP_S:
    case AArch64::TRN2_PPP_B:
    case AArch64::TRN2_PPP_D:
    case AArch64::TRN2_PPP_H:
    case AArch64::TRN2_PPP_S:
    case AArch64::UZP1_PPP_B:
    case AArch64::UZP1_PPP_D:
    case AArch64::UZP1_PPP_H:
    case AArch64::UZP1_PPP_S:
    case AArch64::UZP2_PPP_B:
    case AArch64::UZP2_PPP_D:
    case AArch64::UZP2_PPP_H:
    case AArch64::UZP2_PPP_S:
    case AArch64::ZIP1_PPP_B:
    case AArch64::ZIP1_PPP_D:
    case AArch64::ZIP1_PPP_H:
    case AArch64::ZIP1_PPP_S:
    case AArch64::ZIP2_PPP_B:
    case AArch64::ZIP2_PPP_D:
    case AArch64::ZIP2_PPP_H:
    case AArch64::ZIP2_PPP_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 2:
        // op: Pm
        return 16;
      case 1:
        // op: Pn
        return 5;
      }
      break;
    }
    case AArch64::WHILEGE_PWW_B:
    case AArch64::WHILEGE_PWW_D:
    case AArch64::WHILEGE_PWW_H:
    case AArch64::WHILEGE_PWW_S:
    case AArch64::WHILEGE_PXX_B:
    case AArch64::WHILEGE_PXX_D:
    case AArch64::WHILEGE_PXX_H:
    case AArch64::WHILEGE_PXX_S:
    case AArch64::WHILEGT_PWW_B:
    case AArch64::WHILEGT_PWW_D:
    case AArch64::WHILEGT_PWW_H:
    case AArch64::WHILEGT_PWW_S:
    case AArch64::WHILEGT_PXX_B:
    case AArch64::WHILEGT_PXX_D:
    case AArch64::WHILEGT_PXX_H:
    case AArch64::WHILEGT_PXX_S:
    case AArch64::WHILEHI_PWW_B:
    case AArch64::WHILEHI_PWW_D:
    case AArch64::WHILEHI_PWW_H:
    case AArch64::WHILEHI_PWW_S:
    case AArch64::WHILEHI_PXX_B:
    case AArch64::WHILEHI_PXX_D:
    case AArch64::WHILEHI_PXX_H:
    case AArch64::WHILEHI_PXX_S:
    case AArch64::WHILEHS_PWW_B:
    case AArch64::WHILEHS_PWW_D:
    case AArch64::WHILEHS_PWW_H:
    case AArch64::WHILEHS_PWW_S:
    case AArch64::WHILEHS_PXX_B:
    case AArch64::WHILEHS_PXX_D:
    case AArch64::WHILEHS_PXX_H:
    case AArch64::WHILEHS_PXX_S:
    case AArch64::WHILELE_PWW_B:
    case AArch64::WHILELE_PWW_D:
    case AArch64::WHILELE_PWW_H:
    case AArch64::WHILELE_PWW_S:
    case AArch64::WHILELE_PXX_B:
    case AArch64::WHILELE_PXX_D:
    case AArch64::WHILELE_PXX_H:
    case AArch64::WHILELE_PXX_S:
    case AArch64::WHILELO_PWW_B:
    case AArch64::WHILELO_PWW_D:
    case AArch64::WHILELO_PWW_H:
    case AArch64::WHILELO_PWW_S:
    case AArch64::WHILELO_PXX_B:
    case AArch64::WHILELO_PXX_D:
    case AArch64::WHILELO_PXX_H:
    case AArch64::WHILELO_PXX_S:
    case AArch64::WHILELS_PWW_B:
    case AArch64::WHILELS_PWW_D:
    case AArch64::WHILELS_PWW_H:
    case AArch64::WHILELS_PWW_S:
    case AArch64::WHILELS_PXX_B:
    case AArch64::WHILELS_PXX_D:
    case AArch64::WHILELS_PXX_H:
    case AArch64::WHILELS_PXX_S:
    case AArch64::WHILELT_PWW_B:
    case AArch64::WHILELT_PWW_D:
    case AArch64::WHILELT_PWW_H:
    case AArch64::WHILELT_PWW_S:
    case AArch64::WHILELT_PXX_B:
    case AArch64::WHILELT_PXX_D:
    case AArch64::WHILELT_PXX_H:
    case AArch64::WHILELT_PXX_S:
    case AArch64::WHILERW_PXX_B:
    case AArch64::WHILERW_PXX_D:
    case AArch64::WHILERW_PXX_H:
    case AArch64::WHILERW_PXX_S:
    case AArch64::WHILEWR_PXX_B:
    case AArch64::WHILEWR_PXX_D:
    case AArch64::WHILEWR_PXX_H:
    case AArch64::WHILEWR_PXX_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      case 2:
        // op: Rm
        return 16;
      case 1:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::PFALSE:
    case AArch64::RDFFR_P: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 0;
      }
      break;
    }
    case AArch64::WHILEGE_2PXX_B:
    case AArch64::WHILEGE_2PXX_D:
    case AArch64::WHILEGE_2PXX_H:
    case AArch64::WHILEGE_2PXX_S:
    case AArch64::WHILEGT_2PXX_B:
    case AArch64::WHILEGT_2PXX_D:
    case AArch64::WHILEGT_2PXX_H:
    case AArch64::WHILEGT_2PXX_S:
    case AArch64::WHILEHI_2PXX_B:
    case AArch64::WHILEHI_2PXX_D:
    case AArch64::WHILEHI_2PXX_H:
    case AArch64::WHILEHI_2PXX_S:
    case AArch64::WHILEHS_2PXX_B:
    case AArch64::WHILEHS_2PXX_D:
    case AArch64::WHILEHS_2PXX_H:
    case AArch64::WHILEHS_2PXX_S:
    case AArch64::WHILELE_2PXX_B:
    case AArch64::WHILELE_2PXX_D:
    case AArch64::WHILELE_2PXX_H:
    case AArch64::WHILELE_2PXX_S:
    case AArch64::WHILELO_2PXX_B:
    case AArch64::WHILELO_2PXX_D:
    case AArch64::WHILELO_2PXX_H:
    case AArch64::WHILELO_2PXX_S:
    case AArch64::WHILELS_2PXX_B:
    case AArch64::WHILELS_2PXX_D:
    case AArch64::WHILELS_2PXX_H:
    case AArch64::WHILELS_2PXX_S:
    case AArch64::WHILELT_2PXX_B:
    case AArch64::WHILELT_2PXX_D:
    case AArch64::WHILELT_2PXX_H:
    case AArch64::WHILELT_2PXX_S: {
      switch (OpNum) {
      case 0:
        // op: Pd
        return 1;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      }
      break;
    }
    case AArch64::BRKNS_PPzP:
    case AArch64::BRKN_PPzP: {
      switch (OpNum) {
      case 0:
        // op: Pdm
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Pn
        return 5;
      }
      break;
    }
    case AArch64::PFIRST_B:
    case AArch64::PNEXT_B:
    case AArch64::PNEXT_D:
    case AArch64::PNEXT_H:
    case AArch64::PNEXT_S: {
      switch (OpNum) {
      case 0:
        // op: Pdn
        return 0;
      case 1:
        // op: Pg
        return 5;
      }
      break;
    }
    case AArch64::PTEST_PP: {
      switch (OpNum) {
      case 0:
        // op: Pg
        return 10;
      case 1:
        // op: Pn
        return 5;
      }
      break;
    }
    case AArch64::WRFFR: {
      switch (OpNum) {
      case 0:
        // op: Pn
        return 5;
      }
      break;
    }
    case AArch64::LDR_PXI:
    case AArch64::STR_PXI: {
      switch (OpNum) {
      case 0:
        // op: Pt
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: imm9
        return 10;
      }
      break;
    }
    case AArch64::CNTP_XCI_B:
    case AArch64::CNTP_XCI_D:
    case AArch64::CNTP_XCI_H:
    case AArch64::CNTP_XCI_S: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: PNn
        return 5;
      case 2:
        // op: vl
        return 10;
      }
      break;
    }
    case AArch64::ADDPL_XXI:
    case AArch64::ADDSPL_XXI:
    case AArch64::ADDSVL_XXI:
    case AArch64::ADDVL_XXI: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 16;
      case 2:
        // op: imm6
        return 5;
      }
      break;
    }
    case AArch64::FMADDDrrr:
    case AArch64::FMADDHrrr:
    case AArch64::FMADDSrrr:
    case AArch64::FMSUBDrrr:
    case AArch64::FMSUBHrrr:
    case AArch64::FMSUBSrrr:
    case AArch64::FNMADDDrrr:
    case AArch64::FNMADDHrrr:
    case AArch64::FNMADDSrrr:
    case AArch64::FNMSUBDrrr:
    case AArch64::FNMSUBHrrr:
    case AArch64::FNMSUBSrrr:
    case AArch64::MADDPT:
    case AArch64::MADDWrrr:
    case AArch64::MADDXrrr:
    case AArch64::MSUBPT:
    case AArch64::MSUBWrrr:
    case AArch64::MSUBXrrr:
    case AArch64::SMADDLrrr:
    case AArch64::SMSUBLrrr:
    case AArch64::UMADDLrrr:
    case AArch64::UMSUBLrrr: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: Ra
        return 10;
      }
      break;
    }
    case AArch64::CSELWr:
    case AArch64::CSELXr:
    case AArch64::CSINCWr:
    case AArch64::CSINCXr:
    case AArch64::CSINVWr:
    case AArch64::CSINVXr:
    case AArch64::CSNEGWr:
    case AArch64::CSNEGXr:
    case AArch64::FCSELDrrr:
    case AArch64::FCSELHrrr:
    case AArch64::FCSELSrrr: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: cond
        return 12;
      }
      break;
    }
    case AArch64::ADDSXrx64:
    case AArch64::ADDXrx64:
    case AArch64::SUBSXrx64:
    case AArch64::SUBXrx64: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: ext
        return 10;
      }
      break;
    }
    case AArch64::ADDSWrx:
    case AArch64::ADDSXrx:
    case AArch64::ADDWrx:
    case AArch64::ADDXrx:
    case AArch64::SUBSWrx:
    case AArch64::SUBSXrx:
    case AArch64::SUBWrx:
    case AArch64::SUBXrx: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: extend
        return 10;
      }
      break;
    }
    case AArch64::FMULXv1i16_indexed:
    case AArch64::FMULXv1i32_indexed:
    case AArch64::FMULXv1i64_indexed:
    case AArch64::FMULXv2i32_indexed:
    case AArch64::FMULXv2i64_indexed:
    case AArch64::FMULXv4i16_indexed:
    case AArch64::FMULXv4i32_indexed:
    case AArch64::FMULXv8i16_indexed:
    case AArch64::FMULv1i16_indexed:
    case AArch64::FMULv1i32_indexed:
    case AArch64::FMULv1i64_indexed:
    case AArch64::FMULv2i32_indexed:
    case AArch64::FMULv2i64_indexed:
    case AArch64::FMULv4i16_indexed:
    case AArch64::FMULv4i32_indexed:
    case AArch64::FMULv8i16_indexed:
    case AArch64::MULv2i32_indexed:
    case AArch64::MULv4i16_indexed:
    case AArch64::MULv4i32_indexed:
    case AArch64::MULv8i16_indexed:
    case AArch64::SMULLv2i32_indexed:
    case AArch64::SMULLv4i16_indexed:
    case AArch64::SMULLv4i32_indexed:
    case AArch64::SMULLv8i16_indexed:
    case AArch64::SQDMULHv1i16_indexed:
    case AArch64::SQDMULHv1i32_indexed:
    case AArch64::SQDMULHv2i32_indexed:
    case AArch64::SQDMULHv4i16_indexed:
    case AArch64::SQDMULHv4i32_indexed:
    case AArch64::SQDMULHv8i16_indexed:
    case AArch64::SQDMULLv1i32_indexed:
    case AArch64::SQDMULLv1i64_indexed:
    case AArch64::SQDMULLv2i32_indexed:
    case AArch64::SQDMULLv4i16_indexed:
    case AArch64::SQDMULLv4i32_indexed:
    case AArch64::SQDMULLv8i16_indexed:
    case AArch64::SQRDMULHv1i16_indexed:
    case AArch64::SQRDMULHv1i32_indexed:
    case AArch64::SQRDMULHv2i32_indexed:
    case AArch64::SQRDMULHv4i16_indexed:
    case AArch64::SQRDMULHv4i32_indexed:
    case AArch64::SQRDMULHv8i16_indexed:
    case AArch64::UMULLv2i32_indexed:
    case AArch64::UMULLv4i16_indexed:
    case AArch64::UMULLv4i32_indexed:
    case AArch64::UMULLv8i16_indexed: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: idx
        return 11;
      }
      break;
    }
    case AArch64::LUT2_H: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: idx
        return 12;
      }
      break;
    }
    case AArch64::LUT2_B:
    case AArch64::LUT4_H: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: idx
        return 13;
      }
      break;
    }
    case AArch64::LUT4_B: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: idx
        return 14;
      }
      break;
    }
    case AArch64::EXTRWrri:
    case AArch64::EXTRXrri: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: imm
        return 10;
      }
      break;
    }
    case AArch64::EXTv16i8:
    case AArch64::EXTv8i8: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: imm
        return 11;
      }
      break;
    }
    case AArch64::FCADDv2f32:
    case AArch64::FCADDv2f64:
    case AArch64::FCADDv4f16:
    case AArch64::FCADDv4f32:
    case AArch64::FCADDv8f16: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: rot
        return 12;
      }
      break;
    }
    case AArch64::ADDSWrs:
    case AArch64::ADDSXrs:
    case AArch64::ADDWrs:
    case AArch64::ADDXrs:
    case AArch64::ANDSWrs:
    case AArch64::ANDSXrs:
    case AArch64::ANDWrs:
    case AArch64::ANDXrs:
    case AArch64::BICSWrs:
    case AArch64::BICSXrs:
    case AArch64::BICWrs:
    case AArch64::BICXrs:
    case AArch64::EONWrs:
    case AArch64::EONXrs:
    case AArch64::EORWrs:
    case AArch64::EORXrs:
    case AArch64::ORNWrs:
    case AArch64::ORNXrs:
    case AArch64::ORRWrs:
    case AArch64::ORRXrs:
    case AArch64::SUBSWrs:
    case AArch64::SUBSXrs:
    case AArch64::SUBWrs:
    case AArch64::SUBXrs: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: shift
        return 10;
      }
      break;
    }
    case AArch64::ADDPT_shift:
    case AArch64::SUBPT_shift: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: shift_imm
        return 10;
      }
      break;
    }
    case AArch64::ADCSWr:
    case AArch64::ADCSXr:
    case AArch64::ADCWr:
    case AArch64::ADCXr:
    case AArch64::ADDHNv2i64_v2i32:
    case AArch64::ADDHNv4i32_v4i16:
    case AArch64::ADDHNv8i16_v8i8:
    case AArch64::ADDPv16i8:
    case AArch64::ADDPv2i32:
    case AArch64::ADDPv2i64:
    case AArch64::ADDPv4i16:
    case AArch64::ADDPv4i32:
    case AArch64::ADDPv8i16:
    case AArch64::ADDPv8i8:
    case AArch64::ADDv16i8:
    case AArch64::ADDv1i64:
    case AArch64::ADDv2i32:
    case AArch64::ADDv2i64:
    case AArch64::ADDv4i16:
    case AArch64::ADDv4i32:
    case AArch64::ADDv8i16:
    case AArch64::ADDv8i8:
    case AArch64::ANDv16i8:
    case AArch64::ANDv8i8:
    case AArch64::ASRVWr:
    case AArch64::ASRVXr:
    case AArch64::BICv16i8:
    case AArch64::BICv8i8:
    case AArch64::CMEQv16i8:
    case AArch64::CMEQv1i64:
    case AArch64::CMEQv2i32:
    case AArch64::CMEQv2i64:
    case AArch64::CMEQv4i16:
    case AArch64::CMEQv4i32:
    case AArch64::CMEQv8i16:
    case AArch64::CMEQv8i8:
    case AArch64::CMGEv16i8:
    case AArch64::CMGEv1i64:
    case AArch64::CMGEv2i32:
    case AArch64::CMGEv2i64:
    case AArch64::CMGEv4i16:
    case AArch64::CMGEv4i32:
    case AArch64::CMGEv8i16:
    case AArch64::CMGEv8i8:
    case AArch64::CMGTv16i8:
    case AArch64::CMGTv1i64:
    case AArch64::CMGTv2i32:
    case AArch64::CMGTv2i64:
    case AArch64::CMGTv4i16:
    case AArch64::CMGTv4i32:
    case AArch64::CMGTv8i16:
    case AArch64::CMGTv8i8:
    case AArch64::CMHIv16i8:
    case AArch64::CMHIv1i64:
    case AArch64::CMHIv2i32:
    case AArch64::CMHIv2i64:
    case AArch64::CMHIv4i16:
    case AArch64::CMHIv4i32:
    case AArch64::CMHIv8i16:
    case AArch64::CMHIv8i8:
    case AArch64::CMHSv16i8:
    case AArch64::CMHSv1i64:
    case AArch64::CMHSv2i32:
    case AArch64::CMHSv2i64:
    case AArch64::CMHSv4i16:
    case AArch64::CMHSv4i32:
    case AArch64::CMHSv8i16:
    case AArch64::CMHSv8i8:
    case AArch64::CMTSTv16i8:
    case AArch64::CMTSTv1i64:
    case AArch64::CMTSTv2i32:
    case AArch64::CMTSTv2i64:
    case AArch64::CMTSTv4i16:
    case AArch64::CMTSTv4i32:
    case AArch64::CMTSTv8i16:
    case AArch64::CMTSTv8i8:
    case AArch64::CRC32Brr:
    case AArch64::CRC32CBrr:
    case AArch64::CRC32CHrr:
    case AArch64::CRC32CWrr:
    case AArch64::CRC32CXrr:
    case AArch64::CRC32Hrr:
    case AArch64::CRC32Wrr:
    case AArch64::CRC32Xrr:
    case AArch64::EORv16i8:
    case AArch64::EORv8i8:
    case AArch64::FABD16:
    case AArch64::FABD32:
    case AArch64::FABD64:
    case AArch64::FABDv2f32:
    case AArch64::FABDv2f64:
    case AArch64::FABDv4f16:
    case AArch64::FABDv4f32:
    case AArch64::FABDv8f16:
    case AArch64::FACGE16:
    case AArch64::FACGE32:
    case AArch64::FACGE64:
    case AArch64::FACGEv2f32:
    case AArch64::FACGEv2f64:
    case AArch64::FACGEv4f16:
    case AArch64::FACGEv4f32:
    case AArch64::FACGEv8f16:
    case AArch64::FACGT16:
    case AArch64::FACGT32:
    case AArch64::FACGT64:
    case AArch64::FACGTv2f32:
    case AArch64::FACGTv2f64:
    case AArch64::FACGTv4f16:
    case AArch64::FACGTv4f32:
    case AArch64::FACGTv8f16:
    case AArch64::FADDDrr:
    case AArch64::FADDHrr:
    case AArch64::FADDPv2f32:
    case AArch64::FADDPv2f64:
    case AArch64::FADDPv4f16:
    case AArch64::FADDPv4f32:
    case AArch64::FADDPv8f16:
    case AArch64::FADDSrr:
    case AArch64::FADDv2f32:
    case AArch64::FADDv2f64:
    case AArch64::FADDv4f16:
    case AArch64::FADDv4f32:
    case AArch64::FADDv8f16:
    case AArch64::FAMAXv2f32:
    case AArch64::FAMAXv2f64:
    case AArch64::FAMAXv4f16:
    case AArch64::FAMAXv4f32:
    case AArch64::FAMAXv8f16:
    case AArch64::FAMINv2f32:
    case AArch64::FAMINv2f64:
    case AArch64::FAMINv4f16:
    case AArch64::FAMINv4f32:
    case AArch64::FAMINv8f16:
    case AArch64::FCMEQ16:
    case AArch64::FCMEQ32:
    case AArch64::FCMEQ64:
    case AArch64::FCMEQv2f32:
    case AArch64::FCMEQv2f64:
    case AArch64::FCMEQv4f16:
    case AArch64::FCMEQv4f32:
    case AArch64::FCMEQv8f16:
    case AArch64::FCMGE16:
    case AArch64::FCMGE32:
    case AArch64::FCMGE64:
    case AArch64::FCMGEv2f32:
    case AArch64::FCMGEv2f64:
    case AArch64::FCMGEv4f16:
    case AArch64::FCMGEv4f32:
    case AArch64::FCMGEv8f16:
    case AArch64::FCMGT16:
    case AArch64::FCMGT32:
    case AArch64::FCMGT64:
    case AArch64::FCMGTv2f32:
    case AArch64::FCMGTv2f64:
    case AArch64::FCMGTv4f16:
    case AArch64::FCMGTv4f32:
    case AArch64::FCMGTv8f16:
    case AArch64::FCVTN_F16v16f8:
    case AArch64::FCVTN_F16v8f8:
    case AArch64::FCVTN_F32v8f8:
    case AArch64::FDIVDrr:
    case AArch64::FDIVHrr:
    case AArch64::FDIVSrr:
    case AArch64::FDIVv2f32:
    case AArch64::FDIVv2f64:
    case AArch64::FDIVv4f16:
    case AArch64::FDIVv4f32:
    case AArch64::FDIVv8f16:
    case AArch64::FMAXDrr:
    case AArch64::FMAXHrr:
    case AArch64::FMAXNMDrr:
    case AArch64::FMAXNMHrr:
    case AArch64::FMAXNMPv2f32:
    case AArch64::FMAXNMPv2f64:
    case AArch64::FMAXNMPv4f16:
    case AArch64::FMAXNMPv4f32:
    case AArch64::FMAXNMPv8f16:
    case AArch64::FMAXNMSrr:
    case AArch64::FMAXNMv2f32:
    case AArch64::FMAXNMv2f64:
    case AArch64::FMAXNMv4f16:
    case AArch64::FMAXNMv4f32:
    case AArch64::FMAXNMv8f16:
    case AArch64::FMAXPv2f32:
    case AArch64::FMAXPv2f64:
    case AArch64::FMAXPv4f16:
    case AArch64::FMAXPv4f32:
    case AArch64::FMAXPv8f16:
    case AArch64::FMAXSrr:
    case AArch64::FMAXv2f32:
    case AArch64::FMAXv2f64:
    case AArch64::FMAXv4f16:
    case AArch64::FMAXv4f32:
    case AArch64::FMAXv8f16:
    case AArch64::FMINDrr:
    case AArch64::FMINHrr:
    case AArch64::FMINNMDrr:
    case AArch64::FMINNMHrr:
    case AArch64::FMINNMPv2f32:
    case AArch64::FMINNMPv2f64:
    case AArch64::FMINNMPv4f16:
    case AArch64::FMINNMPv4f32:
    case AArch64::FMINNMPv8f16:
    case AArch64::FMINNMSrr:
    case AArch64::FMINNMv2f32:
    case AArch64::FMINNMv2f64:
    case AArch64::FMINNMv4f16:
    case AArch64::FMINNMv4f32:
    case AArch64::FMINNMv8f16:
    case AArch64::FMINPv2f32:
    case AArch64::FMINPv2f64:
    case AArch64::FMINPv4f16:
    case AArch64::FMINPv4f32:
    case AArch64::FMINPv8f16:
    case AArch64::FMINSrr:
    case AArch64::FMINv2f32:
    case AArch64::FMINv2f64:
    case AArch64::FMINv4f16:
    case AArch64::FMINv4f32:
    case AArch64::FMINv8f16:
    case AArch64::FMULDrr:
    case AArch64::FMULHrr:
    case AArch64::FMULSrr:
    case AArch64::FMULX16:
    case AArch64::FMULX32:
    case AArch64::FMULX64:
    case AArch64::FMULXv2f32:
    case AArch64::FMULXv2f64:
    case AArch64::FMULXv4f16:
    case AArch64::FMULXv4f32:
    case AArch64::FMULXv8f16:
    case AArch64::FMULv2f32:
    case AArch64::FMULv2f64:
    case AArch64::FMULv4f16:
    case AArch64::FMULv4f32:
    case AArch64::FMULv8f16:
    case AArch64::FNMULDrr:
    case AArch64::FNMULHrr:
    case AArch64::FNMULSrr:
    case AArch64::FRECPS16:
    case AArch64::FRECPS32:
    case AArch64::FRECPS64:
    case AArch64::FRECPSv2f32:
    case AArch64::FRECPSv2f64:
    case AArch64::FRECPSv4f16:
    case AArch64::FRECPSv4f32:
    case AArch64::FRECPSv8f16:
    case AArch64::FRSQRTS16:
    case AArch64::FRSQRTS32:
    case AArch64::FRSQRTS64:
    case AArch64::FRSQRTSv2f32:
    case AArch64::FRSQRTSv2f64:
    case AArch64::FRSQRTSv4f16:
    case AArch64::FRSQRTSv4f32:
    case AArch64::FRSQRTSv8f16:
    case AArch64::FSCALEv2f32:
    case AArch64::FSCALEv2f64:
    case AArch64::FSCALEv4f16:
    case AArch64::FSCALEv4f32:
    case AArch64::FSCALEv8f16:
    case AArch64::FSUBDrr:
    case AArch64::FSUBHrr:
    case AArch64::FSUBSrr:
    case AArch64::FSUBv2f32:
    case AArch64::FSUBv2f64:
    case AArch64::FSUBv4f16:
    case AArch64::FSUBv4f32:
    case AArch64::FSUBv8f16:
    case AArch64::GMI:
    case AArch64::IRG:
    case AArch64::LSLVWr:
    case AArch64::LSLVXr:
    case AArch64::LSRVWr:
    case AArch64::LSRVXr:
    case AArch64::MULv16i8:
    case AArch64::MULv2i32:
    case AArch64::MULv4i16:
    case AArch64::MULv4i32:
    case AArch64::MULv8i16:
    case AArch64::MULv8i8:
    case AArch64::ORNv16i8:
    case AArch64::ORNv8i8:
    case AArch64::ORRv16i8:
    case AArch64::ORRv8i8:
    case AArch64::PACGA:
    case AArch64::PMULLv16i8:
    case AArch64::PMULLv1i64:
    case AArch64::PMULLv2i64:
    case AArch64::PMULLv8i8:
    case AArch64::PMULv16i8:
    case AArch64::PMULv8i8:
    case AArch64::RADDHNv2i64_v2i32:
    case AArch64::RADDHNv4i32_v4i16:
    case AArch64::RADDHNv8i16_v8i8:
    case AArch64::RORVWr:
    case AArch64::RORVXr:
    case AArch64::RSUBHNv2i64_v2i32:
    case AArch64::RSUBHNv4i32_v4i16:
    case AArch64::RSUBHNv8i16_v8i8:
    case AArch64::SABDLv16i8_v8i16:
    case AArch64::SABDLv2i32_v2i64:
    case AArch64::SABDLv4i16_v4i32:
    case AArch64::SABDLv4i32_v2i64:
    case AArch64::SABDLv8i16_v4i32:
    case AArch64::SABDLv8i8_v8i16:
    case AArch64::SABDv16i8:
    case AArch64::SABDv2i32:
    case AArch64::SABDv4i16:
    case AArch64::SABDv4i32:
    case AArch64::SABDv8i16:
    case AArch64::SABDv8i8:
    case AArch64::SADDLv16i8_v8i16:
    case AArch64::SADDLv2i32_v2i64:
    case AArch64::SADDLv4i16_v4i32:
    case AArch64::SADDLv4i32_v2i64:
    case AArch64::SADDLv8i16_v4i32:
    case AArch64::SADDLv8i8_v8i16:
    case AArch64::SADDWv16i8_v8i16:
    case AArch64::SADDWv2i32_v2i64:
    case AArch64::SADDWv4i16_v4i32:
    case AArch64::SADDWv4i32_v2i64:
    case AArch64::SADDWv8i16_v4i32:
    case AArch64::SADDWv8i8_v8i16:
    case AArch64::SBCSWr:
    case AArch64::SBCSXr:
    case AArch64::SBCWr:
    case AArch64::SBCXr:
    case AArch64::SDIVWr:
    case AArch64::SDIVXr:
    case AArch64::SHADDv16i8:
    case AArch64::SHADDv2i32:
    case AArch64::SHADDv4i16:
    case AArch64::SHADDv4i32:
    case AArch64::SHADDv8i16:
    case AArch64::SHADDv8i8:
    case AArch64::SHSUBv16i8:
    case AArch64::SHSUBv2i32:
    case AArch64::SHSUBv4i16:
    case AArch64::SHSUBv4i32:
    case AArch64::SHSUBv8i16:
    case AArch64::SHSUBv8i8:
    case AArch64::SMAXPv16i8:
    case AArch64::SMAXPv2i32:
    case AArch64::SMAXPv4i16:
    case AArch64::SMAXPv4i32:
    case AArch64::SMAXPv8i16:
    case AArch64::SMAXPv8i8:
    case AArch64::SMAXWrr:
    case AArch64::SMAXXrr:
    case AArch64::SMAXv16i8:
    case AArch64::SMAXv2i32:
    case AArch64::SMAXv4i16:
    case AArch64::SMAXv4i32:
    case AArch64::SMAXv8i16:
    case AArch64::SMAXv8i8:
    case AArch64::SMINPv16i8:
    case AArch64::SMINPv2i32:
    case AArch64::SMINPv4i16:
    case AArch64::SMINPv4i32:
    case AArch64::SMINPv8i16:
    case AArch64::SMINPv8i8:
    case AArch64::SMINWrr:
    case AArch64::SMINXrr:
    case AArch64::SMINv16i8:
    case AArch64::SMINv2i32:
    case AArch64::SMINv4i16:
    case AArch64::SMINv4i32:
    case AArch64::SMINv8i16:
    case AArch64::SMINv8i8:
    case AArch64::SMULHrr:
    case AArch64::SMULLv16i8_v8i16:
    case AArch64::SMULLv2i32_v2i64:
    case AArch64::SMULLv4i16_v4i32:
    case AArch64::SMULLv4i32_v2i64:
    case AArch64::SMULLv8i16_v4i32:
    case AArch64::SMULLv8i8_v8i16:
    case AArch64::SQADDv16i8:
    case AArch64::SQADDv1i16:
    case AArch64::SQADDv1i32:
    case AArch64::SQADDv1i64:
    case AArch64::SQADDv1i8:
    case AArch64::SQADDv2i32:
    case AArch64::SQADDv2i64:
    case AArch64::SQADDv4i16:
    case AArch64::SQADDv4i32:
    case AArch64::SQADDv8i16:
    case AArch64::SQADDv8i8:
    case AArch64::SQDMULHv1i16:
    case AArch64::SQDMULHv1i32:
    case AArch64::SQDMULHv2i32:
    case AArch64::SQDMULHv4i16:
    case AArch64::SQDMULHv4i32:
    case AArch64::SQDMULHv8i16:
    case AArch64::SQDMULLi16:
    case AArch64::SQDMULLi32:
    case AArch64::SQDMULLv2i32_v2i64:
    case AArch64::SQDMULLv4i16_v4i32:
    case AArch64::SQDMULLv4i32_v2i64:
    case AArch64::SQDMULLv8i16_v4i32:
    case AArch64::SQRDMULHv1i16:
    case AArch64::SQRDMULHv1i32:
    case AArch64::SQRDMULHv2i32:
    case AArch64::SQRDMULHv4i16:
    case AArch64::SQRDMULHv4i32:
    case AArch64::SQRDMULHv8i16:
    case AArch64::SQRSHLv16i8:
    case AArch64::SQRSHLv1i16:
    case AArch64::SQRSHLv1i32:
    case AArch64::SQRSHLv1i64:
    case AArch64::SQRSHLv1i8:
    case AArch64::SQRSHLv2i32:
    case AArch64::SQRSHLv2i64:
    case AArch64::SQRSHLv4i16:
    case AArch64::SQRSHLv4i32:
    case AArch64::SQRSHLv8i16:
    case AArch64::SQRSHLv8i8:
    case AArch64::SQSHLv16i8:
    case AArch64::SQSHLv1i16:
    case AArch64::SQSHLv1i32:
    case AArch64::SQSHLv1i64:
    case AArch64::SQSHLv1i8:
    case AArch64::SQSHLv2i32:
    case AArch64::SQSHLv2i64:
    case AArch64::SQSHLv4i16:
    case AArch64::SQSHLv4i32:
    case AArch64::SQSHLv8i16:
    case AArch64::SQSHLv8i8:
    case AArch64::SQSUBv16i8:
    case AArch64::SQSUBv1i16:
    case AArch64::SQSUBv1i32:
    case AArch64::SQSUBv1i64:
    case AArch64::SQSUBv1i8:
    case AArch64::SQSUBv2i32:
    case AArch64::SQSUBv2i64:
    case AArch64::SQSUBv4i16:
    case AArch64::SQSUBv4i32:
    case AArch64::SQSUBv8i16:
    case AArch64::SQSUBv8i8:
    case AArch64::SRHADDv16i8:
    case AArch64::SRHADDv2i32:
    case AArch64::SRHADDv4i16:
    case AArch64::SRHADDv4i32:
    case AArch64::SRHADDv8i16:
    case AArch64::SRHADDv8i8:
    case AArch64::SRSHLv16i8:
    case AArch64::SRSHLv1i64:
    case AArch64::SRSHLv2i32:
    case AArch64::SRSHLv2i64:
    case AArch64::SRSHLv4i16:
    case AArch64::SRSHLv4i32:
    case AArch64::SRSHLv8i16:
    case AArch64::SRSHLv8i8:
    case AArch64::SSHLv16i8:
    case AArch64::SSHLv1i64:
    case AArch64::SSHLv2i32:
    case AArch64::SSHLv2i64:
    case AArch64::SSHLv4i16:
    case AArch64::SSHLv4i32:
    case AArch64::SSHLv8i16:
    case AArch64::SSHLv8i8:
    case AArch64::SSUBLv16i8_v8i16:
    case AArch64::SSUBLv2i32_v2i64:
    case AArch64::SSUBLv4i16_v4i32:
    case AArch64::SSUBLv4i32_v2i64:
    case AArch64::SSUBLv8i16_v4i32:
    case AArch64::SSUBLv8i8_v8i16:
    case AArch64::SSUBWv16i8_v8i16:
    case AArch64::SSUBWv2i32_v2i64:
    case AArch64::SSUBWv4i16_v4i32:
    case AArch64::SSUBWv4i32_v2i64:
    case AArch64::SSUBWv8i16_v4i32:
    case AArch64::SSUBWv8i8_v8i16:
    case AArch64::SUBHNv2i64_v2i32:
    case AArch64::SUBHNv4i32_v4i16:
    case AArch64::SUBHNv8i16_v8i8:
    case AArch64::SUBP:
    case AArch64::SUBPS:
    case AArch64::SUBv16i8:
    case AArch64::SUBv1i64:
    case AArch64::SUBv2i32:
    case AArch64::SUBv2i64:
    case AArch64::SUBv4i16:
    case AArch64::SUBv4i32:
    case AArch64::SUBv8i16:
    case AArch64::SUBv8i8:
    case AArch64::TRN1v16i8:
    case AArch64::TRN1v2i32:
    case AArch64::TRN1v2i64:
    case AArch64::TRN1v4i16:
    case AArch64::TRN1v4i32:
    case AArch64::TRN1v8i16:
    case AArch64::TRN1v8i8:
    case AArch64::TRN2v16i8:
    case AArch64::TRN2v2i32:
    case AArch64::TRN2v2i64:
    case AArch64::TRN2v4i16:
    case AArch64::TRN2v4i32:
    case AArch64::TRN2v8i16:
    case AArch64::TRN2v8i8:
    case AArch64::UABDLv16i8_v8i16:
    case AArch64::UABDLv2i32_v2i64:
    case AArch64::UABDLv4i16_v4i32:
    case AArch64::UABDLv4i32_v2i64:
    case AArch64::UABDLv8i16_v4i32:
    case AArch64::UABDLv8i8_v8i16:
    case AArch64::UABDv16i8:
    case AArch64::UABDv2i32:
    case AArch64::UABDv4i16:
    case AArch64::UABDv4i32:
    case AArch64::UABDv8i16:
    case AArch64::UABDv8i8:
    case AArch64::UADDLv16i8_v8i16:
    case AArch64::UADDLv2i32_v2i64:
    case AArch64::UADDLv4i16_v4i32:
    case AArch64::UADDLv4i32_v2i64:
    case AArch64::UADDLv8i16_v4i32:
    case AArch64::UADDLv8i8_v8i16:
    case AArch64::UADDWv16i8_v8i16:
    case AArch64::UADDWv2i32_v2i64:
    case AArch64::UADDWv4i16_v4i32:
    case AArch64::UADDWv4i32_v2i64:
    case AArch64::UADDWv8i16_v4i32:
    case AArch64::UADDWv8i8_v8i16:
    case AArch64::UDIVWr:
    case AArch64::UDIVXr:
    case AArch64::UHADDv16i8:
    case AArch64::UHADDv2i32:
    case AArch64::UHADDv4i16:
    case AArch64::UHADDv4i32:
    case AArch64::UHADDv8i16:
    case AArch64::UHADDv8i8:
    case AArch64::UHSUBv16i8:
    case AArch64::UHSUBv2i32:
    case AArch64::UHSUBv4i16:
    case AArch64::UHSUBv4i32:
    case AArch64::UHSUBv8i16:
    case AArch64::UHSUBv8i8:
    case AArch64::UMAXPv16i8:
    case AArch64::UMAXPv2i32:
    case AArch64::UMAXPv4i16:
    case AArch64::UMAXPv4i32:
    case AArch64::UMAXPv8i16:
    case AArch64::UMAXPv8i8:
    case AArch64::UMAXWrr:
    case AArch64::UMAXXrr:
    case AArch64::UMAXv16i8:
    case AArch64::UMAXv2i32:
    case AArch64::UMAXv4i16:
    case AArch64::UMAXv4i32:
    case AArch64::UMAXv8i16:
    case AArch64::UMAXv8i8:
    case AArch64::UMINPv16i8:
    case AArch64::UMINPv2i32:
    case AArch64::UMINPv4i16:
    case AArch64::UMINPv4i32:
    case AArch64::UMINPv8i16:
    case AArch64::UMINPv8i8:
    case AArch64::UMINWrr:
    case AArch64::UMINXrr:
    case AArch64::UMINv16i8:
    case AArch64::UMINv2i32:
    case AArch64::UMINv4i16:
    case AArch64::UMINv4i32:
    case AArch64::UMINv8i16:
    case AArch64::UMINv8i8:
    case AArch64::UMULHrr:
    case AArch64::UMULLv16i8_v8i16:
    case AArch64::UMULLv2i32_v2i64:
    case AArch64::UMULLv4i16_v4i32:
    case AArch64::UMULLv4i32_v2i64:
    case AArch64::UMULLv8i16_v4i32:
    case AArch64::UMULLv8i8_v8i16:
    case AArch64::UQADDv16i8:
    case AArch64::UQADDv1i16:
    case AArch64::UQADDv1i32:
    case AArch64::UQADDv1i64:
    case AArch64::UQADDv1i8:
    case AArch64::UQADDv2i32:
    case AArch64::UQADDv2i64:
    case AArch64::UQADDv4i16:
    case AArch64::UQADDv4i32:
    case AArch64::UQADDv8i16:
    case AArch64::UQADDv8i8:
    case AArch64::UQRSHLv16i8:
    case AArch64::UQRSHLv1i16:
    case AArch64::UQRSHLv1i32:
    case AArch64::UQRSHLv1i64:
    case AArch64::UQRSHLv1i8:
    case AArch64::UQRSHLv2i32:
    case AArch64::UQRSHLv2i64:
    case AArch64::UQRSHLv4i16:
    case AArch64::UQRSHLv4i32:
    case AArch64::UQRSHLv8i16:
    case AArch64::UQRSHLv8i8:
    case AArch64::UQSHLv16i8:
    case AArch64::UQSHLv1i16:
    case AArch64::UQSHLv1i32:
    case AArch64::UQSHLv1i64:
    case AArch64::UQSHLv1i8:
    case AArch64::UQSHLv2i32:
    case AArch64::UQSHLv2i64:
    case AArch64::UQSHLv4i16:
    case AArch64::UQSHLv4i32:
    case AArch64::UQSHLv8i16:
    case AArch64::UQSHLv8i8:
    case AArch64::UQSUBv16i8:
    case AArch64::UQSUBv1i16:
    case AArch64::UQSUBv1i32:
    case AArch64::UQSUBv1i64:
    case AArch64::UQSUBv1i8:
    case AArch64::UQSUBv2i32:
    case AArch64::UQSUBv2i64:
    case AArch64::UQSUBv4i16:
    case AArch64::UQSUBv4i32:
    case AArch64::UQSUBv8i16:
    case AArch64::UQSUBv8i8:
    case AArch64::URHADDv16i8:
    case AArch64::URHADDv2i32:
    case AArch64::URHADDv4i16:
    case AArch64::URHADDv4i32:
    case AArch64::URHADDv8i16:
    case AArch64::URHADDv8i8:
    case AArch64::URSHLv16i8:
    case AArch64::URSHLv1i64:
    case AArch64::URSHLv2i32:
    case AArch64::URSHLv2i64:
    case AArch64::URSHLv4i16:
    case AArch64::URSHLv4i32:
    case AArch64::URSHLv8i16:
    case AArch64::URSHLv8i8:
    case AArch64::USHLv16i8:
    case AArch64::USHLv1i64:
    case AArch64::USHLv2i32:
    case AArch64::USHLv2i64:
    case AArch64::USHLv4i16:
    case AArch64::USHLv4i32:
    case AArch64::USHLv8i16:
    case AArch64::USHLv8i8:
    case AArch64::USUBLv16i8_v8i16:
    case AArch64::USUBLv2i32_v2i64:
    case AArch64::USUBLv4i16_v4i32:
    case AArch64::USUBLv4i32_v2i64:
    case AArch64::USUBLv8i16_v4i32:
    case AArch64::USUBLv8i8_v8i16:
    case AArch64::USUBWv16i8_v8i16:
    case AArch64::USUBWv2i32_v2i64:
    case AArch64::USUBWv4i16_v4i32:
    case AArch64::USUBWv4i32_v2i64:
    case AArch64::USUBWv8i16_v4i32:
    case AArch64::USUBWv8i8_v8i16:
    case AArch64::UZP1v16i8:
    case AArch64::UZP1v2i32:
    case AArch64::UZP1v2i64:
    case AArch64::UZP1v4i16:
    case AArch64::UZP1v4i32:
    case AArch64::UZP1v8i16:
    case AArch64::UZP1v8i8:
    case AArch64::UZP2v16i8:
    case AArch64::UZP2v2i32:
    case AArch64::UZP2v2i64:
    case AArch64::UZP2v4i16:
    case AArch64::UZP2v4i32:
    case AArch64::UZP2v8i16:
    case AArch64::UZP2v8i8:
    case AArch64::ZIP1v16i8:
    case AArch64::ZIP1v2i32:
    case AArch64::ZIP1v2i64:
    case AArch64::ZIP1v4i16:
    case AArch64::ZIP1v4i32:
    case AArch64::ZIP1v8i16:
    case AArch64::ZIP1v8i8:
    case AArch64::ZIP2v16i8:
    case AArch64::ZIP2v2i32:
    case AArch64::ZIP2v2i64:
    case AArch64::ZIP2v4i16:
    case AArch64::ZIP2v4i32:
    case AArch64::ZIP2v8i16:
    case AArch64::ZIP2v8i8: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      }
      break;
    }
    case AArch64::DUPv16i8lane:
    case AArch64::DUPv8i8lane:
    case AArch64::SMOVvi8to32:
    case AArch64::SMOVvi8to64:
    case AArch64::UMOVvi8: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 17;
      }
      break;
    }
    case AArch64::DUPv4i16lane:
    case AArch64::DUPv8i16lane:
    case AArch64::SMOVvi16to32:
    case AArch64::SMOVvi16to64:
    case AArch64::UMOVvi16: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 18;
      }
      break;
    }
    case AArch64::DUPv2i32lane:
    case AArch64::DUPv4i32lane:
    case AArch64::SMOVvi32to64:
    case AArch64::UMOVvi32: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 19;
      }
      break;
    }
    case AArch64::DUPv2i64lane:
    case AArch64::UMOVvi64: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 20;
      }
      break;
    }
    case AArch64::ADDSWri:
    case AArch64::ADDSXri:
    case AArch64::ADDWri:
    case AArch64::ADDXri:
    case AArch64::ANDSWri:
    case AArch64::ANDSXri:
    case AArch64::ANDWri:
    case AArch64::ANDXri:
    case AArch64::EORWri:
    case AArch64::EORXri:
    case AArch64::ORRWri:
    case AArch64::ORRXri:
    case AArch64::SMAXWri:
    case AArch64::SMAXXri:
    case AArch64::SMINWri:
    case AArch64::SMINXri:
    case AArch64::SUBSWri:
    case AArch64::SUBSXri:
    case AArch64::SUBWri:
    case AArch64::SUBXri:
    case AArch64::UMAXWri:
    case AArch64::UMAXXri:
    case AArch64::UMINWri:
    case AArch64::UMINXri: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: imm
        return 10;
      }
      break;
    }
    case AArch64::FCVTZSd:
    case AArch64::FCVTZSh:
    case AArch64::FCVTZSs:
    case AArch64::FCVTZSv2i32_shift:
    case AArch64::FCVTZSv2i64_shift:
    case AArch64::FCVTZSv4i16_shift:
    case AArch64::FCVTZSv4i32_shift:
    case AArch64::FCVTZSv8i16_shift:
    case AArch64::FCVTZUd:
    case AArch64::FCVTZUh:
    case AArch64::FCVTZUs:
    case AArch64::FCVTZUv2i32_shift:
    case AArch64::FCVTZUv2i64_shift:
    case AArch64::FCVTZUv4i16_shift:
    case AArch64::FCVTZUv4i32_shift:
    case AArch64::FCVTZUv8i16_shift:
    case AArch64::RSHRNv2i32_shift:
    case AArch64::RSHRNv4i16_shift:
    case AArch64::RSHRNv8i8_shift:
    case AArch64::SCVTFd:
    case AArch64::SCVTFh:
    case AArch64::SCVTFs:
    case AArch64::SCVTFv2i32_shift:
    case AArch64::SCVTFv2i64_shift:
    case AArch64::SCVTFv4i16_shift:
    case AArch64::SCVTFv4i32_shift:
    case AArch64::SCVTFv8i16_shift:
    case AArch64::SHLd:
    case AArch64::SHLv16i8_shift:
    case AArch64::SHLv2i32_shift:
    case AArch64::SHLv2i64_shift:
    case AArch64::SHLv4i16_shift:
    case AArch64::SHLv4i32_shift:
    case AArch64::SHLv8i16_shift:
    case AArch64::SHLv8i8_shift:
    case AArch64::SHRNv2i32_shift:
    case AArch64::SHRNv4i16_shift:
    case AArch64::SHRNv8i8_shift:
    case AArch64::SQRSHRNb:
    case AArch64::SQRSHRNh:
    case AArch64::SQRSHRNs:
    case AArch64::SQRSHRNv2i32_shift:
    case AArch64::SQRSHRNv4i16_shift:
    case AArch64::SQRSHRNv8i8_shift:
    case AArch64::SQRSHRUNb:
    case AArch64::SQRSHRUNh:
    case AArch64::SQRSHRUNs:
    case AArch64::SQRSHRUNv2i32_shift:
    case AArch64::SQRSHRUNv4i16_shift:
    case AArch64::SQRSHRUNv8i8_shift:
    case AArch64::SQSHLUb:
    case AArch64::SQSHLUd:
    case AArch64::SQSHLUh:
    case AArch64::SQSHLUs:
    case AArch64::SQSHLUv16i8_shift:
    case AArch64::SQSHLUv2i32_shift:
    case AArch64::SQSHLUv2i64_shift:
    case AArch64::SQSHLUv4i16_shift:
    case AArch64::SQSHLUv4i32_shift:
    case AArch64::SQSHLUv8i16_shift:
    case AArch64::SQSHLUv8i8_shift:
    case AArch64::SQSHLb:
    case AArch64::SQSHLd:
    case AArch64::SQSHLh:
    case AArch64::SQSHLs:
    case AArch64::SQSHLv16i8_shift:
    case AArch64::SQSHLv2i32_shift:
    case AArch64::SQSHLv2i64_shift:
    case AArch64::SQSHLv4i16_shift:
    case AArch64::SQSHLv4i32_shift:
    case AArch64::SQSHLv8i16_shift:
    case AArch64::SQSHLv8i8_shift:
    case AArch64::SQSHRNb:
    case AArch64::SQSHRNh:
    case AArch64::SQSHRNs:
    case AArch64::SQSHRNv2i32_shift:
    case AArch64::SQSHRNv4i16_shift:
    case AArch64::SQSHRNv8i8_shift:
    case AArch64::SQSHRUNb:
    case AArch64::SQSHRUNh:
    case AArch64::SQSHRUNs:
    case AArch64::SQSHRUNv2i32_shift:
    case AArch64::SQSHRUNv4i16_shift:
    case AArch64::SQSHRUNv8i8_shift:
    case AArch64::SRSHRd:
    case AArch64::SRSHRv16i8_shift:
    case AArch64::SRSHRv2i32_shift:
    case AArch64::SRSHRv2i64_shift:
    case AArch64::SRSHRv4i16_shift:
    case AArch64::SRSHRv4i32_shift:
    case AArch64::SRSHRv8i16_shift:
    case AArch64::SRSHRv8i8_shift:
    case AArch64::SSHLLv16i8_shift:
    case AArch64::SSHLLv2i32_shift:
    case AArch64::SSHLLv4i16_shift:
    case AArch64::SSHLLv4i32_shift:
    case AArch64::SSHLLv8i16_shift:
    case AArch64::SSHLLv8i8_shift:
    case AArch64::SSHRd:
    case AArch64::SSHRv16i8_shift:
    case AArch64::SSHRv2i32_shift:
    case AArch64::SSHRv2i64_shift:
    case AArch64::SSHRv4i16_shift:
    case AArch64::SSHRv4i32_shift:
    case AArch64::SSHRv8i16_shift:
    case AArch64::SSHRv8i8_shift:
    case AArch64::UCVTFd:
    case AArch64::UCVTFh:
    case AArch64::UCVTFs:
    case AArch64::UCVTFv2i32_shift:
    case AArch64::UCVTFv2i64_shift:
    case AArch64::UCVTFv4i16_shift:
    case AArch64::UCVTFv4i32_shift:
    case AArch64::UCVTFv8i16_shift:
    case AArch64::UQRSHRNb:
    case AArch64::UQRSHRNh:
    case AArch64::UQRSHRNs:
    case AArch64::UQRSHRNv2i32_shift:
    case AArch64::UQRSHRNv4i16_shift:
    case AArch64::UQRSHRNv8i8_shift:
    case AArch64::UQSHLb:
    case AArch64::UQSHLd:
    case AArch64::UQSHLh:
    case AArch64::UQSHLs:
    case AArch64::UQSHLv16i8_shift:
    case AArch64::UQSHLv2i32_shift:
    case AArch64::UQSHLv2i64_shift:
    case AArch64::UQSHLv4i16_shift:
    case AArch64::UQSHLv4i32_shift:
    case AArch64::UQSHLv8i16_shift:
    case AArch64::UQSHLv8i8_shift:
    case AArch64::UQSHRNb:
    case AArch64::UQSHRNh:
    case AArch64::UQSHRNs:
    case AArch64::UQSHRNv2i32_shift:
    case AArch64::UQSHRNv4i16_shift:
    case AArch64::UQSHRNv8i8_shift:
    case AArch64::URSHRd:
    case AArch64::URSHRv16i8_shift:
    case AArch64::URSHRv2i32_shift:
    case AArch64::URSHRv2i64_shift:
    case AArch64::URSHRv4i16_shift:
    case AArch64::URSHRv4i32_shift:
    case AArch64::URSHRv8i16_shift:
    case AArch64::URSHRv8i8_shift:
    case AArch64::USHLLv16i8_shift:
    case AArch64::USHLLv2i32_shift:
    case AArch64::USHLLv4i16_shift:
    case AArch64::USHLLv4i32_shift:
    case AArch64::USHLLv8i16_shift:
    case AArch64::USHLLv8i8_shift:
    case AArch64::USHRd:
    case AArch64::USHRv16i8_shift:
    case AArch64::USHRv2i32_shift:
    case AArch64::USHRv2i64_shift:
    case AArch64::USHRv4i16_shift:
    case AArch64::USHRv4i32_shift:
    case AArch64::USHRv8i16_shift:
    case AArch64::USHRv8i8_shift: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: imm
        return 16;
      }
      break;
    }
    case AArch64::ADDG:
    case AArch64::SUBG: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: imm6
        return 16;
      case 3:
        // op: imm4
        return 10;
      }
      break;
    }
    case AArch64::SBFMWri:
    case AArch64::SBFMXri:
    case AArch64::UBFMWri:
    case AArch64::UBFMXri: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: immr
        return 16;
      case 3:
        // op: imms
        return 10;
      }
      break;
    }
    case AArch64::FCVTZSSWDri:
    case AArch64::FCVTZSSWHri:
    case AArch64::FCVTZSSWSri:
    case AArch64::FCVTZSSXDri:
    case AArch64::FCVTZSSXHri:
    case AArch64::FCVTZSSXSri:
    case AArch64::FCVTZUSWDri:
    case AArch64::FCVTZUSWHri:
    case AArch64::FCVTZUSWSri:
    case AArch64::FCVTZUSXDri:
    case AArch64::FCVTZUSXHri:
    case AArch64::FCVTZUSXSri:
    case AArch64::SCVTFSWDri:
    case AArch64::SCVTFSWHri:
    case AArch64::SCVTFSWSri:
    case AArch64::SCVTFSXDri:
    case AArch64::SCVTFSXHri:
    case AArch64::SCVTFSXSri:
    case AArch64::UCVTFSWDri:
    case AArch64::UCVTFSWHri:
    case AArch64::UCVTFSWSri:
    case AArch64::UCVTFSXDri:
    case AArch64::UCVTFSXHri:
    case AArch64::UCVTFSXSri: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: scale
        return 10;
      }
      break;
    }
    case AArch64::ABSWr:
    case AArch64::ABSXr:
    case AArch64::ABSv16i8:
    case AArch64::ABSv1i64:
    case AArch64::ABSv2i32:
    case AArch64::ABSv2i64:
    case AArch64::ABSv4i16:
    case AArch64::ABSv4i32:
    case AArch64::ABSv8i16:
    case AArch64::ABSv8i8:
    case AArch64::ADDPv2i64p:
    case AArch64::ADDVv16i8v:
    case AArch64::ADDVv4i16v:
    case AArch64::ADDVv4i32v:
    case AArch64::ADDVv8i16v:
    case AArch64::ADDVv8i8v:
    case AArch64::AESIMCrr:
    case AArch64::AESMCrr:
    case AArch64::BF1CVTL:
    case AArch64::BF1CVTL2:
    case AArch64::BF2CVTL:
    case AArch64::BF2CVTL2:
    case AArch64::BFCVT:
    case AArch64::BFCVTN:
    case AArch64::CLSWr:
    case AArch64::CLSXr:
    case AArch64::CLSv16i8:
    case AArch64::CLSv2i32:
    case AArch64::CLSv4i16:
    case AArch64::CLSv4i32:
    case AArch64::CLSv8i16:
    case AArch64::CLSv8i8:
    case AArch64::CLZWr:
    case AArch64::CLZXr:
    case AArch64::CLZv16i8:
    case AArch64::CLZv2i32:
    case AArch64::CLZv4i16:
    case AArch64::CLZv4i32:
    case AArch64::CLZv8i16:
    case AArch64::CLZv8i8:
    case AArch64::CMEQv16i8rz:
    case AArch64::CMEQv1i64rz:
    case AArch64::CMEQv2i32rz:
    case AArch64::CMEQv2i64rz:
    case AArch64::CMEQv4i16rz:
    case AArch64::CMEQv4i32rz:
    case AArch64::CMEQv8i16rz:
    case AArch64::CMEQv8i8rz:
    case AArch64::CMGEv16i8rz:
    case AArch64::CMGEv1i64rz:
    case AArch64::CMGEv2i32rz:
    case AArch64::CMGEv2i64rz:
    case AArch64::CMGEv4i16rz:
    case AArch64::CMGEv4i32rz:
    case AArch64::CMGEv8i16rz:
    case AArch64::CMGEv8i8rz:
    case AArch64::CMGTv16i8rz:
    case AArch64::CMGTv1i64rz:
    case AArch64::CMGTv2i32rz:
    case AArch64::CMGTv2i64rz:
    case AArch64::CMGTv4i16rz:
    case AArch64::CMGTv4i32rz:
    case AArch64::CMGTv8i16rz:
    case AArch64::CMGTv8i8rz:
    case AArch64::CMLEv16i8rz:
    case AArch64::CMLEv1i64rz:
    case AArch64::CMLEv2i32rz:
    case AArch64::CMLEv2i64rz:
    case AArch64::CMLEv4i16rz:
    case AArch64::CMLEv4i32rz:
    case AArch64::CMLEv8i16rz:
    case AArch64::CMLEv8i8rz:
    case AArch64::CMLTv16i8rz:
    case AArch64::CMLTv1i64rz:
    case AArch64::CMLTv2i32rz:
    case AArch64::CMLTv2i64rz:
    case AArch64::CMLTv4i16rz:
    case AArch64::CMLTv4i32rz:
    case AArch64::CMLTv8i16rz:
    case AArch64::CMLTv8i8rz:
    case AArch64::CNTWr:
    case AArch64::CNTXr:
    case AArch64::CNTv16i8:
    case AArch64::CNTv8i8:
    case AArch64::CTZWr:
    case AArch64::CTZXr:
    case AArch64::DUPv16i8gpr:
    case AArch64::DUPv2i32gpr:
    case AArch64::DUPv2i64gpr:
    case AArch64::DUPv4i16gpr:
    case AArch64::DUPv4i32gpr:
    case AArch64::DUPv8i16gpr:
    case AArch64::DUPv8i8gpr:
    case AArch64::F1CVTL:
    case AArch64::F1CVTL2:
    case AArch64::F2CVTL:
    case AArch64::F2CVTL2:
    case AArch64::FABSDr:
    case AArch64::FABSHr:
    case AArch64::FABSSr:
    case AArch64::FABSv2f32:
    case AArch64::FABSv2f64:
    case AArch64::FABSv4f16:
    case AArch64::FABSv4f32:
    case AArch64::FABSv8f16:
    case AArch64::FADDPv2i16p:
    case AArch64::FADDPv2i32p:
    case AArch64::FADDPv2i64p:
    case AArch64::FCMEQv1i16rz:
    case AArch64::FCMEQv1i32rz:
    case AArch64::FCMEQv1i64rz:
    case AArch64::FCMEQv2i32rz:
    case AArch64::FCMEQv2i64rz:
    case AArch64::FCMEQv4i16rz:
    case AArch64::FCMEQv4i32rz:
    case AArch64::FCMEQv8i16rz:
    case AArch64::FCMGEv1i16rz:
    case AArch64::FCMGEv1i32rz:
    case AArch64::FCMGEv1i64rz:
    case AArch64::FCMGEv2i32rz:
    case AArch64::FCMGEv2i64rz:
    case AArch64::FCMGEv4i16rz:
    case AArch64::FCMGEv4i32rz:
    case AArch64::FCMGEv8i16rz:
    case AArch64::FCMGTv1i16rz:
    case AArch64::FCMGTv1i32rz:
    case AArch64::FCMGTv1i64rz:
    case AArch64::FCMGTv2i32rz:
    case AArch64::FCMGTv2i64rz:
    case AArch64::FCMGTv4i16rz:
    case AArch64::FCMGTv4i32rz:
    case AArch64::FCMGTv8i16rz:
    case AArch64::FCMLEv1i16rz:
    case AArch64::FCMLEv1i32rz:
    case AArch64::FCMLEv1i64rz:
    case AArch64::FCMLEv2i32rz:
    case AArch64::FCMLEv2i64rz:
    case AArch64::FCMLEv4i16rz:
    case AArch64::FCMLEv4i32rz:
    case AArch64::FCMLEv8i16rz:
    case AArch64::FCMLTv1i16rz:
    case AArch64::FCMLTv1i32rz:
    case AArch64::FCMLTv1i64rz:
    case AArch64::FCMLTv2i32rz:
    case AArch64::FCMLTv2i64rz:
    case AArch64::FCMLTv4i16rz:
    case AArch64::FCMLTv4i32rz:
    case AArch64::FCMLTv8i16rz:
    case AArch64::FCVTASDHr:
    case AArch64::FCVTASDSr:
    case AArch64::FCVTASSDr:
    case AArch64::FCVTASSHr:
    case AArch64::FCVTASUWDr:
    case AArch64::FCVTASUWHr:
    case AArch64::FCVTASUWSr:
    case AArch64::FCVTASUXDr:
    case AArch64::FCVTASUXHr:
    case AArch64::FCVTASUXSr:
    case AArch64::FCVTASv1f16:
    case AArch64::FCVTASv1i32:
    case AArch64::FCVTASv1i64:
    case AArch64::FCVTASv2f32:
    case AArch64::FCVTASv2f64:
    case AArch64::FCVTASv4f16:
    case AArch64::FCVTASv4f32:
    case AArch64::FCVTASv8f16:
    case AArch64::FCVTAUDHr:
    case AArch64::FCVTAUDSr:
    case AArch64::FCVTAUSDr:
    case AArch64::FCVTAUSHr:
    case AArch64::FCVTAUUWDr:
    case AArch64::FCVTAUUWHr:
    case AArch64::FCVTAUUWSr:
    case AArch64::FCVTAUUXDr:
    case AArch64::FCVTAUUXHr:
    case AArch64::FCVTAUUXSr:
    case AArch64::FCVTAUv1f16:
    case AArch64::FCVTAUv1i32:
    case AArch64::FCVTAUv1i64:
    case AArch64::FCVTAUv2f32:
    case AArch64::FCVTAUv2f64:
    case AArch64::FCVTAUv4f16:
    case AArch64::FCVTAUv4f32:
    case AArch64::FCVTAUv8f16:
    case AArch64::FCVTDHr:
    case AArch64::FCVTDSr:
    case AArch64::FCVTHDr:
    case AArch64::FCVTHSr:
    case AArch64::FCVTLv2i32:
    case AArch64::FCVTLv4i16:
    case AArch64::FCVTLv4i32:
    case AArch64::FCVTLv8i16:
    case AArch64::FCVTMSDHr:
    case AArch64::FCVTMSDSr:
    case AArch64::FCVTMSSDr:
    case AArch64::FCVTMSSHr:
    case AArch64::FCVTMSUWDr:
    case AArch64::FCVTMSUWHr:
    case AArch64::FCVTMSUWSr:
    case AArch64::FCVTMSUXDr:
    case AArch64::FCVTMSUXHr:
    case AArch64::FCVTMSUXSr:
    case AArch64::FCVTMSv1f16:
    case AArch64::FCVTMSv1i32:
    case AArch64::FCVTMSv1i64:
    case AArch64::FCVTMSv2f32:
    case AArch64::FCVTMSv2f64:
    case AArch64::FCVTMSv4f16:
    case AArch64::FCVTMSv4f32:
    case AArch64::FCVTMSv8f16:
    case AArch64::FCVTMUDHr:
    case AArch64::FCVTMUDSr:
    case AArch64::FCVTMUSDr:
    case AArch64::FCVTMUSHr:
    case AArch64::FCVTMUUWDr:
    case AArch64::FCVTMUUWHr:
    case AArch64::FCVTMUUWSr:
    case AArch64::FCVTMUUXDr:
    case AArch64::FCVTMUUXHr:
    case AArch64::FCVTMUUXSr:
    case AArch64::FCVTMUv1f16:
    case AArch64::FCVTMUv1i32:
    case AArch64::FCVTMUv1i64:
    case AArch64::FCVTMUv2f32:
    case AArch64::FCVTMUv2f64:
    case AArch64::FCVTMUv4f16:
    case AArch64::FCVTMUv4f32:
    case AArch64::FCVTMUv8f16:
    case AArch64::FCVTNSDHr:
    case AArch64::FCVTNSDSr:
    case AArch64::FCVTNSSDr:
    case AArch64::FCVTNSSHr:
    case AArch64::FCVTNSUWDr:
    case AArch64::FCVTNSUWHr:
    case AArch64::FCVTNSUWSr:
    case AArch64::FCVTNSUXDr:
    case AArch64::FCVTNSUXHr:
    case AArch64::FCVTNSUXSr:
    case AArch64::FCVTNSv1f16:
    case AArch64::FCVTNSv1i32:
    case AArch64::FCVTNSv1i64:
    case AArch64::FCVTNSv2f32:
    case AArch64::FCVTNSv2f64:
    case AArch64::FCVTNSv4f16:
    case AArch64::FCVTNSv4f32:
    case AArch64::FCVTNSv8f16:
    case AArch64::FCVTNUDHr:
    case AArch64::FCVTNUDSr:
    case AArch64::FCVTNUSDr:
    case AArch64::FCVTNUSHr:
    case AArch64::FCVTNUUWDr:
    case AArch64::FCVTNUUWHr:
    case AArch64::FCVTNUUWSr:
    case AArch64::FCVTNUUXDr:
    case AArch64::FCVTNUUXHr:
    case AArch64::FCVTNUUXSr:
    case AArch64::FCVTNUv1f16:
    case AArch64::FCVTNUv1i32:
    case AArch64::FCVTNUv1i64:
    case AArch64::FCVTNUv2f32:
    case AArch64::FCVTNUv2f64:
    case AArch64::FCVTNUv4f16:
    case AArch64::FCVTNUv4f32:
    case AArch64::FCVTNUv8f16:
    case AArch64::FCVTNv2i32:
    case AArch64::FCVTNv4i16:
    case AArch64::FCVTPSDHr:
    case AArch64::FCVTPSDSr:
    case AArch64::FCVTPSSDr:
    case AArch64::FCVTPSSHr:
    case AArch64::FCVTPSUWDr:
    case AArch64::FCVTPSUWHr:
    case AArch64::FCVTPSUWSr:
    case AArch64::FCVTPSUXDr:
    case AArch64::FCVTPSUXHr:
    case AArch64::FCVTPSUXSr:
    case AArch64::FCVTPSv1f16:
    case AArch64::FCVTPSv1i32:
    case AArch64::FCVTPSv1i64:
    case AArch64::FCVTPSv2f32:
    case AArch64::FCVTPSv2f64:
    case AArch64::FCVTPSv4f16:
    case AArch64::FCVTPSv4f32:
    case AArch64::FCVTPSv8f16:
    case AArch64::FCVTPUDHr:
    case AArch64::FCVTPUDSr:
    case AArch64::FCVTPUSDr:
    case AArch64::FCVTPUSHr:
    case AArch64::FCVTPUUWDr:
    case AArch64::FCVTPUUWHr:
    case AArch64::FCVTPUUWSr:
    case AArch64::FCVTPUUXDr:
    case AArch64::FCVTPUUXHr:
    case AArch64::FCVTPUUXSr:
    case AArch64::FCVTPUv1f16:
    case AArch64::FCVTPUv1i32:
    case AArch64::FCVTPUv1i64:
    case AArch64::FCVTPUv2f32:
    case AArch64::FCVTPUv2f64:
    case AArch64::FCVTPUv4f16:
    case AArch64::FCVTPUv4f32:
    case AArch64::FCVTPUv8f16:
    case AArch64::FCVTSDr:
    case AArch64::FCVTSHr:
    case AArch64::FCVTXNv1i64:
    case AArch64::FCVTXNv2f32:
    case AArch64::FCVTZSDHr:
    case AArch64::FCVTZSDSr:
    case AArch64::FCVTZSSDr:
    case AArch64::FCVTZSSHr:
    case AArch64::FCVTZSUWDr:
    case AArch64::FCVTZSUWHr:
    case AArch64::FCVTZSUWSr:
    case AArch64::FCVTZSUXDr:
    case AArch64::FCVTZSUXHr:
    case AArch64::FCVTZSUXSr:
    case AArch64::FCVTZSv1f16:
    case AArch64::FCVTZSv1i32:
    case AArch64::FCVTZSv1i64:
    case AArch64::FCVTZSv2f32:
    case AArch64::FCVTZSv2f64:
    case AArch64::FCVTZSv4f16:
    case AArch64::FCVTZSv4f32:
    case AArch64::FCVTZSv8f16:
    case AArch64::FCVTZUDHr:
    case AArch64::FCVTZUDSr:
    case AArch64::FCVTZUSDr:
    case AArch64::FCVTZUSHr:
    case AArch64::FCVTZUUWDr:
    case AArch64::FCVTZUUWHr:
    case AArch64::FCVTZUUWSr:
    case AArch64::FCVTZUUXDr:
    case AArch64::FCVTZUUXHr:
    case AArch64::FCVTZUUXSr:
    case AArch64::FCVTZUv1f16:
    case AArch64::FCVTZUv1i32:
    case AArch64::FCVTZUv1i64:
    case AArch64::FCVTZUv2f32:
    case AArch64::FCVTZUv2f64:
    case AArch64::FCVTZUv4f16:
    case AArch64::FCVTZUv4f32:
    case AArch64::FCVTZUv8f16:
    case AArch64::FJCVTZS:
    case AArch64::FMAXNMPv2i16p:
    case AArch64::FMAXNMPv2i32p:
    case AArch64::FMAXNMPv2i64p:
    case AArch64::FMAXNMVv4i16v:
    case AArch64::FMAXNMVv4i32v:
    case AArch64::FMAXNMVv8i16v:
    case AArch64::FMAXPv2i16p:
    case AArch64::FMAXPv2i32p:
    case AArch64::FMAXPv2i64p:
    case AArch64::FMAXVv4i16v:
    case AArch64::FMAXVv4i32v:
    case AArch64::FMAXVv8i16v:
    case AArch64::FMINNMPv2i16p:
    case AArch64::FMINNMPv2i32p:
    case AArch64::FMINNMPv2i64p:
    case AArch64::FMINNMVv4i16v:
    case AArch64::FMINNMVv4i32v:
    case AArch64::FMINNMVv8i16v:
    case AArch64::FMINPv2i16p:
    case AArch64::FMINPv2i32p:
    case AArch64::FMINPv2i64p:
    case AArch64::FMINVv4i16v:
    case AArch64::FMINVv4i32v:
    case AArch64::FMINVv8i16v:
    case AArch64::FMOVDXHighr:
    case AArch64::FMOVDXr:
    case AArch64::FMOVDr:
    case AArch64::FMOVHWr:
    case AArch64::FMOVHXr:
    case AArch64::FMOVHr:
    case AArch64::FMOVSWr:
    case AArch64::FMOVSr:
    case AArch64::FMOVWHr:
    case AArch64::FMOVWSr:
    case AArch64::FMOVXDHighr:
    case AArch64::FMOVXDr:
    case AArch64::FMOVXHr:
    case AArch64::FNEGDr:
    case AArch64::FNEGHr:
    case AArch64::FNEGSr:
    case AArch64::FNEGv2f32:
    case AArch64::FNEGv2f64:
    case AArch64::FNEGv4f16:
    case AArch64::FNEGv4f32:
    case AArch64::FNEGv8f16:
    case AArch64::FRECPEv1f16:
    case AArch64::FRECPEv1i32:
    case AArch64::FRECPEv1i64:
    case AArch64::FRECPEv2f32:
    case AArch64::FRECPEv2f64:
    case AArch64::FRECPEv4f16:
    case AArch64::FRECPEv4f32:
    case AArch64::FRECPEv8f16:
    case AArch64::FRECPXv1f16:
    case AArch64::FRECPXv1i32:
    case AArch64::FRECPXv1i64:
    case AArch64::FRINT32XDr:
    case AArch64::FRINT32XSr:
    case AArch64::FRINT32Xv2f32:
    case AArch64::FRINT32Xv2f64:
    case AArch64::FRINT32Xv4f32:
    case AArch64::FRINT32ZDr:
    case AArch64::FRINT32ZSr:
    case AArch64::FRINT32Zv2f32:
    case AArch64::FRINT32Zv2f64:
    case AArch64::FRINT32Zv4f32:
    case AArch64::FRINT64XDr:
    case AArch64::FRINT64XSr:
    case AArch64::FRINT64Xv2f32:
    case AArch64::FRINT64Xv2f64:
    case AArch64::FRINT64Xv4f32:
    case AArch64::FRINT64ZDr:
    case AArch64::FRINT64ZSr:
    case AArch64::FRINT64Zv2f32:
    case AArch64::FRINT64Zv2f64:
    case AArch64::FRINT64Zv4f32:
    case AArch64::FRINTADr:
    case AArch64::FRINTAHr:
    case AArch64::FRINTASr:
    case AArch64::FRINTAv2f32:
    case AArch64::FRINTAv2f64:
    case AArch64::FRINTAv4f16:
    case AArch64::FRINTAv4f32:
    case AArch64::FRINTAv8f16:
    case AArch64::FRINTIDr:
    case AArch64::FRINTIHr:
    case AArch64::FRINTISr:
    case AArch64::FRINTIv2f32:
    case AArch64::FRINTIv2f64:
    case AArch64::FRINTIv4f16:
    case AArch64::FRINTIv4f32:
    case AArch64::FRINTIv8f16:
    case AArch64::FRINTMDr:
    case AArch64::FRINTMHr:
    case AArch64::FRINTMSr:
    case AArch64::FRINTMv2f32:
    case AArch64::FRINTMv2f64:
    case AArch64::FRINTMv4f16:
    case AArch64::FRINTMv4f32:
    case AArch64::FRINTMv8f16:
    case AArch64::FRINTNDr:
    case AArch64::FRINTNHr:
    case AArch64::FRINTNSr:
    case AArch64::FRINTNv2f32:
    case AArch64::FRINTNv2f64:
    case AArch64::FRINTNv4f16:
    case AArch64::FRINTNv4f32:
    case AArch64::FRINTNv8f16:
    case AArch64::FRINTPDr:
    case AArch64::FRINTPHr:
    case AArch64::FRINTPSr:
    case AArch64::FRINTPv2f32:
    case AArch64::FRINTPv2f64:
    case AArch64::FRINTPv4f16:
    case AArch64::FRINTPv4f32:
    case AArch64::FRINTPv8f16:
    case AArch64::FRINTXDr:
    case AArch64::FRINTXHr:
    case AArch64::FRINTXSr:
    case AArch64::FRINTXv2f32:
    case AArch64::FRINTXv2f64:
    case AArch64::FRINTXv4f16:
    case AArch64::FRINTXv4f32:
    case AArch64::FRINTXv8f16:
    case AArch64::FRINTZDr:
    case AArch64::FRINTZHr:
    case AArch64::FRINTZSr:
    case AArch64::FRINTZv2f32:
    case AArch64::FRINTZv2f64:
    case AArch64::FRINTZv4f16:
    case AArch64::FRINTZv4f32:
    case AArch64::FRINTZv8f16:
    case AArch64::FRSQRTEv1f16:
    case AArch64::FRSQRTEv1i32:
    case AArch64::FRSQRTEv1i64:
    case AArch64::FRSQRTEv2f32:
    case AArch64::FRSQRTEv2f64:
    case AArch64::FRSQRTEv4f16:
    case AArch64::FRSQRTEv4f32:
    case AArch64::FRSQRTEv8f16:
    case AArch64::FSQRTDr:
    case AArch64::FSQRTHr:
    case AArch64::FSQRTSr:
    case AArch64::FSQRTv2f32:
    case AArch64::FSQRTv2f64:
    case AArch64::FSQRTv4f16:
    case AArch64::FSQRTv4f32:
    case AArch64::FSQRTv8f16:
    case AArch64::NEGv16i8:
    case AArch64::NEGv1i64:
    case AArch64::NEGv2i32:
    case AArch64::NEGv2i64:
    case AArch64::NEGv4i16:
    case AArch64::NEGv4i32:
    case AArch64::NEGv8i16:
    case AArch64::NEGv8i8:
    case AArch64::NOTv16i8:
    case AArch64::NOTv8i8:
    case AArch64::RBITWr:
    case AArch64::RBITXr:
    case AArch64::RBITv16i8:
    case AArch64::RBITv8i8:
    case AArch64::REV16Wr:
    case AArch64::REV16Xr:
    case AArch64::REV16v16i8:
    case AArch64::REV16v8i8:
    case AArch64::REV32Xr:
    case AArch64::REV32v16i8:
    case AArch64::REV32v4i16:
    case AArch64::REV32v8i16:
    case AArch64::REV32v8i8:
    case AArch64::REV64v16i8:
    case AArch64::REV64v2i32:
    case AArch64::REV64v4i16:
    case AArch64::REV64v4i32:
    case AArch64::REV64v8i16:
    case AArch64::REV64v8i8:
    case AArch64::REVWr:
    case AArch64::REVXr:
    case AArch64::SADDLPv16i8_v8i16:
    case AArch64::SADDLPv2i32_v1i64:
    case AArch64::SADDLPv4i16_v2i32:
    case AArch64::SADDLPv4i32_v2i64:
    case AArch64::SADDLPv8i16_v4i32:
    case AArch64::SADDLPv8i8_v4i16:
    case AArch64::SADDLVv16i8v:
    case AArch64::SADDLVv4i16v:
    case AArch64::SADDLVv4i32v:
    case AArch64::SADDLVv8i16v:
    case AArch64::SADDLVv8i8v:
    case AArch64::SCVTFDSr:
    case AArch64::SCVTFHDr:
    case AArch64::SCVTFHSr:
    case AArch64::SCVTFSDr:
    case AArch64::SCVTFUWDri:
    case AArch64::SCVTFUWHri:
    case AArch64::SCVTFUWSri:
    case AArch64::SCVTFUXDri:
    case AArch64::SCVTFUXHri:
    case AArch64::SCVTFUXSri:
    case AArch64::SCVTFv1i16:
    case AArch64::SCVTFv1i32:
    case AArch64::SCVTFv1i64:
    case AArch64::SCVTFv2f32:
    case AArch64::SCVTFv2f64:
    case AArch64::SCVTFv4f16:
    case AArch64::SCVTFv4f32:
    case AArch64::SCVTFv8f16:
    case AArch64::SHA1Hrr:
    case AArch64::SHLLv16i8:
    case AArch64::SHLLv2i32:
    case AArch64::SHLLv4i16:
    case AArch64::SHLLv4i32:
    case AArch64::SHLLv8i16:
    case AArch64::SHLLv8i8:
    case AArch64::SMAXVv16i8v:
    case AArch64::SMAXVv4i16v:
    case AArch64::SMAXVv4i32v:
    case AArch64::SMAXVv8i16v:
    case AArch64::SMAXVv8i8v:
    case AArch64::SMINVv16i8v:
    case AArch64::SMINVv4i16v:
    case AArch64::SMINVv4i32v:
    case AArch64::SMINVv8i16v:
    case AArch64::SMINVv8i8v:
    case AArch64::SMOVvi16to32_idx0:
    case AArch64::SMOVvi16to64_idx0:
    case AArch64::SMOVvi32to64_idx0:
    case AArch64::SMOVvi8to32_idx0:
    case AArch64::SMOVvi8to64_idx0:
    case AArch64::SQABSv16i8:
    case AArch64::SQABSv1i16:
    case AArch64::SQABSv1i32:
    case AArch64::SQABSv1i64:
    case AArch64::SQABSv1i8:
    case AArch64::SQABSv2i32:
    case AArch64::SQABSv2i64:
    case AArch64::SQABSv4i16:
    case AArch64::SQABSv4i32:
    case AArch64::SQABSv8i16:
    case AArch64::SQABSv8i8:
    case AArch64::SQNEGv16i8:
    case AArch64::SQNEGv1i16:
    case AArch64::SQNEGv1i32:
    case AArch64::SQNEGv1i64:
    case AArch64::SQNEGv1i8:
    case AArch64::SQNEGv2i32:
    case AArch64::SQNEGv2i64:
    case AArch64::SQNEGv4i16:
    case AArch64::SQNEGv4i32:
    case AArch64::SQNEGv8i16:
    case AArch64::SQNEGv8i8:
    case AArch64::SQXTNv1i16:
    case AArch64::SQXTNv1i32:
    case AArch64::SQXTNv1i8:
    case AArch64::SQXTNv2i32:
    case AArch64::SQXTNv4i16:
    case AArch64::SQXTNv8i8:
    case AArch64::SQXTUNv1i16:
    case AArch64::SQXTUNv1i32:
    case AArch64::SQXTUNv1i8:
    case AArch64::SQXTUNv2i32:
    case AArch64::SQXTUNv4i16:
    case AArch64::SQXTUNv8i8:
    case AArch64::UADDLPv16i8_v8i16:
    case AArch64::UADDLPv2i32_v1i64:
    case AArch64::UADDLPv4i16_v2i32:
    case AArch64::UADDLPv4i32_v2i64:
    case AArch64::UADDLPv8i16_v4i32:
    case AArch64::UADDLPv8i8_v4i16:
    case AArch64::UADDLVv16i8v:
    case AArch64::UADDLVv4i16v:
    case AArch64::UADDLVv4i32v:
    case AArch64::UADDLVv8i16v:
    case AArch64::UADDLVv8i8v:
    case AArch64::UCVTFDSr:
    case AArch64::UCVTFHDr:
    case AArch64::UCVTFHSr:
    case AArch64::UCVTFSDr:
    case AArch64::UCVTFUWDri:
    case AArch64::UCVTFUWHri:
    case AArch64::UCVTFUWSri:
    case AArch64::UCVTFUXDri:
    case AArch64::UCVTFUXHri:
    case AArch64::UCVTFUXSri:
    case AArch64::UCVTFv1i16:
    case AArch64::UCVTFv1i32:
    case AArch64::UCVTFv1i64:
    case AArch64::UCVTFv2f32:
    case AArch64::UCVTFv2f64:
    case AArch64::UCVTFv4f16:
    case AArch64::UCVTFv4f32:
    case AArch64::UCVTFv8f16:
    case AArch64::UMAXVv16i8v:
    case AArch64::UMAXVv4i16v:
    case AArch64::UMAXVv4i32v:
    case AArch64::UMAXVv8i16v:
    case AArch64::UMAXVv8i8v:
    case AArch64::UMINVv16i8v:
    case AArch64::UMINVv4i16v:
    case AArch64::UMINVv4i32v:
    case AArch64::UMINVv8i16v:
    case AArch64::UMINVv8i8v:
    case AArch64::UMOVvi16_idx0:
    case AArch64::UMOVvi32_idx0:
    case AArch64::UMOVvi64_idx0:
    case AArch64::UMOVvi8_idx0:
    case AArch64::UQXTNv1i16:
    case AArch64::UQXTNv1i32:
    case AArch64::UQXTNv1i8:
    case AArch64::UQXTNv2i32:
    case AArch64::UQXTNv4i16:
    case AArch64::UQXTNv8i8:
    case AArch64::URECPEv2i32:
    case AArch64::URECPEv4i32:
    case AArch64::URSQRTEv2i32:
    case AArch64::URSQRTEv4i32:
    case AArch64::XTNv2i32:
    case AArch64::XTNv4i16:
    case AArch64::XTNv8i8: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::FMOVDi:
    case AArch64::FMOVHi:
    case AArch64::FMOVSi: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: imm
        return 13;
      }
      break;
    }
    case AArch64::MOVNWi:
    case AArch64::MOVNXi:
    case AArch64::MOVZWi:
    case AArch64::MOVZXi: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: imm
        return 5;
      case 2:
        // op: shift
        return 21;
      }
      break;
    }
    case AArch64::RDSVLI_XI:
    case AArch64::RDVLI_XI: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: imm6
        return 5;
      }
      break;
    }
    case AArch64::MOVIv2s_msl:
    case AArch64::MOVIv4s_msl:
    case AArch64::MVNIv2s_msl:
    case AArch64::MVNIv4s_msl: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: imm8
        return 5;
      case 2:
        // op: shift
        return 12;
      }
      break;
    }
    case AArch64::MOVIv2i32:
    case AArch64::MOVIv4i16:
    case AArch64::MOVIv4i32:
    case AArch64::MOVIv8i16:
    case AArch64::MVNIv2i32:
    case AArch64::MVNIv4i16:
    case AArch64::MVNIv4i32:
    case AArch64::MVNIv8i16: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: imm8
        return 5;
      case 2:
        // op: shift
        return 13;
      }
      break;
    }
    case AArch64::FMOVv2f32_ns:
    case AArch64::FMOVv2f64_ns:
    case AArch64::FMOVv4f16_ns:
    case AArch64::FMOVv4f32_ns:
    case AArch64::FMOVv8f16_ns:
    case AArch64::MOVID:
    case AArch64::MOVIv16b_ns:
    case AArch64::MOVIv2d_ns:
    case AArch64::MOVIv8b_ns: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 1:
        // op: imm8
        return 5;
      }
      break;
    }
    case AArch64::BFMWri:
    case AArch64::BFMXri: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: immr
        return 16;
      case 4:
        // op: imms
        return 10;
      }
      break;
    }
    case AArch64::MOVKWi:
    case AArch64::MOVKXi: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 2:
        // op: imm
        return 5;
      case 3:
        // op: shift
        return 21;
      }
      break;
    }
    case AArch64::CNTB_XPiI:
    case AArch64::CNTD_XPiI:
    case AArch64::CNTH_XPiI:
    case AArch64::CNTW_XPiI: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      case 2:
        // op: imm4
        return 16;
      case 1:
        // op: pattern
        return 5;
      }
      break;
    }
    case AArch64::XPACD:
    case AArch64::XPACI: {
      switch (OpNum) {
      case 0:
        // op: Rd
        return 0;
      }
      break;
    }
    case AArch64::DECP_XP_B:
    case AArch64::DECP_XP_D:
    case AArch64::DECP_XP_H:
    case AArch64::DECP_XP_S:
    case AArch64::INCP_XP_B:
    case AArch64::INCP_XP_D:
    case AArch64::INCP_XP_H:
    case AArch64::INCP_XP_S:
    case AArch64::SQDECP_XPWd_B:
    case AArch64::SQDECP_XPWd_D:
    case AArch64::SQDECP_XPWd_H:
    case AArch64::SQDECP_XPWd_S:
    case AArch64::SQDECP_XP_B:
    case AArch64::SQDECP_XP_D:
    case AArch64::SQDECP_XP_H:
    case AArch64::SQDECP_XP_S:
    case AArch64::SQINCP_XPWd_B:
    case AArch64::SQINCP_XPWd_D:
    case AArch64::SQINCP_XPWd_H:
    case AArch64::SQINCP_XPWd_S:
    case AArch64::SQINCP_XP_B:
    case AArch64::SQINCP_XP_D:
    case AArch64::SQINCP_XP_H:
    case AArch64::SQINCP_XP_S:
    case AArch64::UQDECP_WP_B:
    case AArch64::UQDECP_WP_D:
    case AArch64::UQDECP_WP_H:
    case AArch64::UQDECP_WP_S:
    case AArch64::UQDECP_XP_B:
    case AArch64::UQDECP_XP_D:
    case AArch64::UQDECP_XP_H:
    case AArch64::UQDECP_XP_S:
    case AArch64::UQINCP_WP_B:
    case AArch64::UQINCP_WP_D:
    case AArch64::UQINCP_WP_H:
    case AArch64::UQINCP_WP_S:
    case AArch64::UQINCP_XP_B:
    case AArch64::UQINCP_XP_D:
    case AArch64::UQINCP_XP_H:
    case AArch64::UQINCP_XP_S: {
      switch (OpNum) {
      case 0:
        // op: Rdn
        return 0;
      case 1:
        // op: Pg
        return 5;
      }
      break;
    }
    case AArch64::DECB_XPiI:
    case AArch64::DECD_XPiI:
    case AArch64::DECH_XPiI:
    case AArch64::DECW_XPiI:
    case AArch64::INCB_XPiI:
    case AArch64::INCD_XPiI:
    case AArch64::INCH_XPiI:
    case AArch64::INCW_XPiI:
    case AArch64::SQDECB_XPiI:
    case AArch64::SQDECB_XPiWdI:
    case AArch64::SQDECD_XPiI:
    case AArch64::SQDECD_XPiWdI:
    case AArch64::SQDECH_XPiI:
    case AArch64::SQDECH_XPiWdI:
    case AArch64::SQDECW_XPiI:
    case AArch64::SQDECW_XPiWdI:
    case AArch64::SQINCB_XPiI:
    case AArch64::SQINCB_XPiWdI:
    case AArch64::SQINCD_XPiI:
    case AArch64::SQINCD_XPiWdI:
    case AArch64::SQINCH_XPiI:
    case AArch64::SQINCH_XPiWdI:
    case AArch64::SQINCW_XPiI:
    case AArch64::SQINCW_XPiWdI:
    case AArch64::UQDECB_WPiI:
    case AArch64::UQDECB_XPiI:
    case AArch64::UQDECD_WPiI:
    case AArch64::UQDECD_XPiI:
    case AArch64::UQDECH_WPiI:
    case AArch64::UQDECH_XPiI:
    case AArch64::UQDECW_WPiI:
    case AArch64::UQDECW_XPiI:
    case AArch64::UQINCB_WPiI:
    case AArch64::UQINCB_XPiI:
    case AArch64::UQINCD_WPiI:
    case AArch64::UQINCD_XPiI:
    case AArch64::UQINCH_WPiI:
    case AArch64::UQINCH_XPiI:
    case AArch64::UQINCW_WPiI:
    case AArch64::UQINCW_XPiI: {
      switch (OpNum) {
      case 0:
        // op: Rdn
        return 0;
      case 2:
        // op: pattern
        return 5;
      case 3:
        // op: imm4
        return 16;
      }
      break;
    }
    case AArch64::RETAASPPCr:
    case AArch64::RETABSPPCr: {
      switch (OpNum) {
      case 0:
        // op: Rm
        return 0;
      }
      break;
    }
    case AArch64::BLRAA:
    case AArch64::BLRAB:
    case AArch64::BRAA:
    case AArch64::BRAB: {
      switch (OpNum) {
      case 0:
        // op: Rn
        return 5;
      case 1:
        // op: Rm
        return 0;
      }
      break;
    }
    case AArch64::CCMNWr:
    case AArch64::CCMNXr:
    case AArch64::CCMPWr:
    case AArch64::CCMPXr:
    case AArch64::FCCMPDrr:
    case AArch64::FCCMPEDrr:
    case AArch64::FCCMPEHrr:
    case AArch64::FCCMPESrr:
    case AArch64::FCCMPHrr:
    case AArch64::FCCMPSrr: {
      switch (OpNum) {
      case 0:
        // op: Rn
        return 5;
      case 1:
        // op: Rm
        return 16;
      case 2:
        // op: nzcv
        return 0;
      case 3:
        // op: cond
        return 12;
      }
      break;
    }
    case AArch64::RMIF: {
      switch (OpNum) {
      case 0:
        // op: Rn
        return 5;
      case 1:
        // op: imm
        return 15;
      case 2:
        // op: mask
        return 0;
      }
      break;
    }
    case AArch64::CCMNWi:
    case AArch64::CCMNXi:
    case AArch64::CCMPWi:
    case AArch64::CCMPXi: {
      switch (OpNum) {
      case 0:
        // op: Rn
        return 5;
      case 1:
        // op: imm
        return 16;
      case 2:
        // op: nzcv
        return 0;
      case 3:
        // op: cond
        return 12;
      }
      break;
    }
    case AArch64::AUTIASPPCr:
    case AArch64::AUTIBSPPCr:
    case AArch64::BLR:
    case AArch64::BLRAAZ:
    case AArch64::BLRABZ:
    case AArch64::BR:
    case AArch64::BRAAZ:
    case AArch64::BRABZ:
    case AArch64::FCMPDri:
    case AArch64::FCMPEDri:
    case AArch64::FCMPEHri:
    case AArch64::FCMPESri:
    case AArch64::FCMPHri:
    case AArch64::FCMPSri:
    case AArch64::RET:
    case AArch64::SETF16:
    case AArch64::SETF8: {
      switch (OpNum) {
      case 0:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::STBFADD:
    case AArch64::STBFADDL:
    case AArch64::STBFMAX:
    case AArch64::STBFMAXL:
    case AArch64::STBFMAXNM:
    case AArch64::STBFMAXNML:
    case AArch64::STBFMIN:
    case AArch64::STBFMINL:
    case AArch64::STBFMINNM:
    case AArch64::STBFMINNML:
    case AArch64::STFADDD:
    case AArch64::STFADDH:
    case AArch64::STFADDLD:
    case AArch64::STFADDLH:
    case AArch64::STFADDLS:
    case AArch64::STFADDS:
    case AArch64::STFMAXD:
    case AArch64::STFMAXH:
    case AArch64::STFMAXLD:
    case AArch64::STFMAXLH:
    case AArch64::STFMAXLS:
    case AArch64::STFMAXNMD:
    case AArch64::STFMAXNMH:
    case AArch64::STFMAXNMLD:
    case AArch64::STFMAXNMLH:
    case AArch64::STFMAXNMLS:
    case AArch64::STFMAXNMS:
    case AArch64::STFMAXS:
    case AArch64::STFMIND:
    case AArch64::STFMINH:
    case AArch64::STFMINLD:
    case AArch64::STFMINLH:
    case AArch64::STFMINLS:
    case AArch64::STFMINNMD:
    case AArch64::STFMINNMH:
    case AArch64::STFMINNMLD:
    case AArch64::STFMINNMLH:
    case AArch64::STFMINNMLS:
    case AArch64::STFMINNMS:
    case AArch64::STFMINS: {
      switch (OpNum) {
      case 0:
        // op: Rs
        return 16;
      case 1:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::LDRBBroW:
    case AArch64::LDRBBroX:
    case AArch64::LDRBroW:
    case AArch64::LDRBroX:
    case AArch64::LDRDroW:
    case AArch64::LDRDroX:
    case AArch64::LDRHHroW:
    case AArch64::LDRHHroX:
    case AArch64::LDRHroW:
    case AArch64::LDRHroX:
    case AArch64::LDRQroW:
    case AArch64::LDRQroX:
    case AArch64::LDRSBWroW:
    case AArch64::LDRSBWroX:
    case AArch64::LDRSBXroW:
    case AArch64::LDRSBXroX:
    case AArch64::LDRSHWroW:
    case AArch64::LDRSHWroX:
    case AArch64::LDRSHXroW:
    case AArch64::LDRSHXroX:
    case AArch64::LDRSWroW:
    case AArch64::LDRSWroX:
    case AArch64::LDRSroW:
    case AArch64::LDRSroX:
    case AArch64::LDRWroW:
    case AArch64::LDRWroX:
    case AArch64::LDRXroW:
    case AArch64::LDRXroX:
    case AArch64::PRFMroW:
    case AArch64::PRFMroX:
    case AArch64::STRBBroW:
    case AArch64::STRBBroX:
    case AArch64::STRBroW:
    case AArch64::STRBroX:
    case AArch64::STRDroW:
    case AArch64::STRDroX:
    case AArch64::STRHHroW:
    case AArch64::STRHHroX:
    case AArch64::STRHroW:
    case AArch64::STRHroX:
    case AArch64::STRQroW:
    case AArch64::STRQroX:
    case AArch64::STRSroW:
    case AArch64::STRSroX:
    case AArch64::STRWroW:
    case AArch64::STRWroX:
    case AArch64::STRXroW:
    case AArch64::STRXroX: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: Rm
        return 16;
      case 3:
        // op: extend
        return 12;
      }
      break;
    }
    case AArch64::LDRBBui:
    case AArch64::LDRBui:
    case AArch64::LDRDui:
    case AArch64::LDRHHui:
    case AArch64::LDRHui:
    case AArch64::LDRQui:
    case AArch64::LDRSBWui:
    case AArch64::LDRSBXui:
    case AArch64::LDRSHWui:
    case AArch64::LDRSHXui:
    case AArch64::LDRSWui:
    case AArch64::LDRSui:
    case AArch64::LDRWui:
    case AArch64::LDRXui:
    case AArch64::PRFMui:
    case AArch64::STRBBui:
    case AArch64::STRBui:
    case AArch64::STRDui:
    case AArch64::STRHHui:
    case AArch64::STRHui:
    case AArch64::STRQui:
    case AArch64::STRSui:
    case AArch64::STRWui:
    case AArch64::STRXui: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: offset
        return 10;
      }
      break;
    }
    case AArch64::LDAPURBi:
    case AArch64::LDAPURHi:
    case AArch64::LDAPURSBWi:
    case AArch64::LDAPURSBXi:
    case AArch64::LDAPURSHWi:
    case AArch64::LDAPURSHXi:
    case AArch64::LDAPURSWi:
    case AArch64::LDAPURXi:
    case AArch64::LDAPURi:
    case AArch64::LDTRBi:
    case AArch64::LDTRHi:
    case AArch64::LDTRSBWi:
    case AArch64::LDTRSBXi:
    case AArch64::LDTRSHWi:
    case AArch64::LDTRSHXi:
    case AArch64::LDTRSWi:
    case AArch64::LDTRWi:
    case AArch64::LDTRXi:
    case AArch64::LDURBBi:
    case AArch64::LDURBi:
    case AArch64::LDURDi:
    case AArch64::LDURHHi:
    case AArch64::LDURHi:
    case AArch64::LDURQi:
    case AArch64::LDURSBWi:
    case AArch64::LDURSBXi:
    case AArch64::LDURSHWi:
    case AArch64::LDURSHXi:
    case AArch64::LDURSWi:
    case AArch64::LDURSi:
    case AArch64::LDURWi:
    case AArch64::LDURXi:
    case AArch64::PRFUMi:
    case AArch64::STLURBi:
    case AArch64::STLURHi:
    case AArch64::STLURWi:
    case AArch64::STLURXi:
    case AArch64::STTRBi:
    case AArch64::STTRHi:
    case AArch64::STTRWi:
    case AArch64::STTRXi:
    case AArch64::STURBBi:
    case AArch64::STURBi:
    case AArch64::STURDi:
    case AArch64::STURHHi:
    case AArch64::STURHi:
    case AArch64::STURQi:
    case AArch64::STURSi:
    case AArch64::STURWi:
    case AArch64::STURXi: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: offset
        return 12;
      }
      break;
    }
    case AArch64::LDAPURbi:
    case AArch64::LDAPURdi:
    case AArch64::LDAPURhi:
    case AArch64::LDAPURqi:
    case AArch64::LDAPURsi:
    case AArch64::STLURbi:
    case AArch64::STLURdi:
    case AArch64::STLURhi:
    case AArch64::STLURqi:
    case AArch64::STLURsi: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: Rn
        return 5;
      case 2:
        // op: simm
        return 12;
      }
      break;
    }
    case AArch64::GCSSTR:
    case AArch64::GCSSTTR:
    case AArch64::LD64B:
    case AArch64::LDARB:
    case AArch64::LDARH:
    case AArch64::LDARW:
    case AArch64::LDARX:
    case AArch64::LDATXRW:
    case AArch64::LDATXRX:
    case AArch64::LDAXRB:
    case AArch64::LDAXRH:
    case AArch64::LDAXRW:
    case AArch64::LDAXRX:
    case AArch64::LDLARB:
    case AArch64::LDLARH:
    case AArch64::LDLARW:
    case AArch64::LDLARX:
    case AArch64::LDTXRWr:
    case AArch64::LDTXRXr:
    case AArch64::LDXRB:
    case AArch64::LDXRH:
    case AArch64::LDXRW:
    case AArch64::LDXRX:
    case AArch64::ST64B:
    case AArch64::STLLRB:
    case AArch64::STLLRH:
    case AArch64::STLLRW:
    case AArch64::STLLRX:
    case AArch64::STLRB:
    case AArch64::STLRH:
    case AArch64::STLRW:
    case AArch64::STLRX: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::LDBFADD:
    case AArch64::LDBFADDA:
    case AArch64::LDBFADDAL:
    case AArch64::LDBFADDL:
    case AArch64::LDBFMAX:
    case AArch64::LDBFMAXA:
    case AArch64::LDBFMAXAL:
    case AArch64::LDBFMAXL:
    case AArch64::LDBFMAXNM:
    case AArch64::LDBFMAXNMA:
    case AArch64::LDBFMAXNMAL:
    case AArch64::LDBFMAXNML:
    case AArch64::LDBFMIN:
    case AArch64::LDBFMINA:
    case AArch64::LDBFMINAL:
    case AArch64::LDBFMINL:
    case AArch64::LDBFMINNM:
    case AArch64::LDBFMINNMA:
    case AArch64::LDBFMINNMAL:
    case AArch64::LDBFMINNML:
    case AArch64::LDFADDAD:
    case AArch64::LDFADDAH:
    case AArch64::LDFADDALD:
    case AArch64::LDFADDALH:
    case AArch64::LDFADDALS:
    case AArch64::LDFADDAS:
    case AArch64::LDFADDD:
    case AArch64::LDFADDH:
    case AArch64::LDFADDLD:
    case AArch64::LDFADDLH:
    case AArch64::LDFADDLS:
    case AArch64::LDFADDS:
    case AArch64::LDFMAXAD:
    case AArch64::LDFMAXAH:
    case AArch64::LDFMAXALD:
    case AArch64::LDFMAXALH:
    case AArch64::LDFMAXALS:
    case AArch64::LDFMAXAS:
    case AArch64::LDFMAXD:
    case AArch64::LDFMAXH:
    case AArch64::LDFMAXLD:
    case AArch64::LDFMAXLH:
    case AArch64::LDFMAXLS:
    case AArch64::LDFMAXNMAD:
    case AArch64::LDFMAXNMAH:
    case AArch64::LDFMAXNMALD:
    case AArch64::LDFMAXNMALH:
    case AArch64::LDFMAXNMALS:
    case AArch64::LDFMAXNMAS:
    case AArch64::LDFMAXNMD:
    case AArch64::LDFMAXNMH:
    case AArch64::LDFMAXNMLD:
    case AArch64::LDFMAXNMLH:
    case AArch64::LDFMAXNMLS:
    case AArch64::LDFMAXNMS:
    case AArch64::LDFMAXS:
    case AArch64::LDFMINAD:
    case AArch64::LDFMINAH:
    case AArch64::LDFMINALD:
    case AArch64::LDFMINALH:
    case AArch64::LDFMINALS:
    case AArch64::LDFMINAS:
    case AArch64::LDFMIND:
    case AArch64::LDFMINH:
    case AArch64::LDFMINLD:
    case AArch64::LDFMINLH:
    case AArch64::LDFMINLS:
    case AArch64::LDFMINNMAD:
    case AArch64::LDFMINNMAH:
    case AArch64::LDFMINNMALD:
    case AArch64::LDFMINNMALH:
    case AArch64::LDFMINNMALS:
    case AArch64::LDFMINNMAS:
    case AArch64::LDFMINNMD:
    case AArch64::LDFMINNMH:
    case AArch64::LDFMINNMLD:
    case AArch64::LDFMINNMLH:
    case AArch64::LDFMINNMLS:
    case AArch64::LDFMINNMS:
    case AArch64::LDFMINS: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: Rs
        return 16;
      case 2:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::LDNPDi:
    case AArch64::LDNPQi:
    case AArch64::LDNPSi:
    case AArch64::LDNPWi:
    case AArch64::LDNPXi:
    case AArch64::LDPDi:
    case AArch64::LDPQi:
    case AArch64::LDPSWi:
    case AArch64::LDPSi:
    case AArch64::LDPWi:
    case AArch64::LDPXi:
    case AArch64::LDTNPQi:
    case AArch64::LDTNPXi:
    case AArch64::LDTPQi:
    case AArch64::LDTPi:
    case AArch64::STGPi:
    case AArch64::STNPDi:
    case AArch64::STNPQi:
    case AArch64::STNPSi:
    case AArch64::STNPWi:
    case AArch64::STNPXi:
    case AArch64::STPDi:
    case AArch64::STPQi:
    case AArch64::STPSi:
    case AArch64::STPWi:
    case AArch64::STPXi:
    case AArch64::STTNPQi:
    case AArch64::STTNPXi:
    case AArch64::STTPQi:
    case AArch64::STTPi: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: Rt2
        return 10;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: offset
        return 15;
      }
      break;
    }
    case AArch64::LDAXPW:
    case AArch64::LDAXPX:
    case AArch64::LDXPW:
    case AArch64::LDXPX: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: Rt2
        return 10;
      case 2:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::LDAPPi:
    case AArch64::LDAPi:
    case AArch64::STLPi: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: Rt2
        return 16;
      case 2:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::TBNZW:
    case AArch64::TBNZX:
    case AArch64::TBZW:
    case AArch64::TBZX: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: bit_off
        return 19;
      case 2:
        // op: target
        return 5;
      }
      break;
    }
    case AArch64::CBEQWri:
    case AArch64::CBEQXri:
    case AArch64::CBGTWri:
    case AArch64::CBGTXri:
    case AArch64::CBHIWri:
    case AArch64::CBHIXri:
    case AArch64::CBLOWri:
    case AArch64::CBLOXri:
    case AArch64::CBLTWri:
    case AArch64::CBLTXri:
    case AArch64::CBNEWri:
    case AArch64::CBNEXri: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: imm
        return 15;
      case 2:
        // op: target
        return 5;
      }
      break;
    }
    case AArch64::LDRDl:
    case AArch64::LDRQl:
    case AArch64::LDRSWl:
    case AArch64::LDRSl:
    case AArch64::LDRWl:
    case AArch64::LDRXl:
    case AArch64::PRFMl: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: label
        return 5;
      }
      break;
    }
    case AArch64::SYSLxt: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: op1
        return 16;
      case 2:
        // op: Cn
        return 12;
      case 3:
        // op: Cm
        return 8;
      case 4:
        // op: op2
        return 5;
      }
      break;
    }
    case AArch64::MRRS:
    case AArch64::MRS: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: systemreg
        return 5;
      }
      break;
    }
    case AArch64::CBNZW:
    case AArch64::CBNZX:
    case AArch64::CBZW:
    case AArch64::CBZX: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 1:
        // op: target
        return 5;
      }
      break;
    }
    case AArch64::RPRFM: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: Rm
        return 16;
      }
      break;
    }
    case AArch64::LDIAPPW:
    case AArch64::LDIAPPX:
    case AArch64::STILPW:
    case AArch64::STILPX: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: Rt2
        return 16;
      }
      break;
    }
    case AArch64::GCSPOPM:
    case AArch64::GCSPUSHM:
    case AArch64::GCSSS1:
    case AArch64::GCSSS2:
    case AArch64::TRCIT:
    case AArch64::WFET:
    case AArch64::WFIT: {
      switch (OpNum) {
      case 0:
        // op: Rt
        return 0;
      }
      break;
    }
    case AArch64::BCAX:
    case AArch64::EOR3:
    case AArch64::SM3SS1: {
      switch (OpNum) {
      case 0:
        // op: Vd
        return 0;
      case 1:
        // op: Vn
        return 5;
      case 2:
        // op: Vm
        return 16;
      case 3:
        // op: Va
        return 10;
      }
      break;
    }
    case AArch64::RAX1:
    case AArch64::SM4ENCKEY:
    case AArch64::TBLv16i8Four:
    case AArch64::TBLv16i8One:
    case AArch64::TBLv16i8Three:
    case AArch64::TBLv16i8Two:
    case AArch64::TBLv8i8Four:
    case AArch64::TBLv8i8One:
    case AArch64::TBLv8i8Three:
    case AArch64::TBLv8i8Two: {
      switch (OpNum) {
      case 0:
        // op: Vd
        return 0;
      case 1:
        // op: Vn
        return 5;
      case 2:
        // op: Vm
        return 16;
      }
      break;
    }
    case AArch64::XAR: {
      switch (OpNum) {
      case 0:
        // op: Vd
        return 0;
      case 1:
        // op: Vn
        return 5;
      case 3:
        // op: imm
        return 10;
      case 2:
        // op: Vm
        return 16;
      }
      break;
    }
    case AArch64::ADDQV_VPZ_B:
    case AArch64::ADDQV_VPZ_D:
    case AArch64::ADDQV_VPZ_H:
    case AArch64::ADDQV_VPZ_S:
    case AArch64::ANDQV_VPZ_B:
    case AArch64::ANDQV_VPZ_D:
    case AArch64::ANDQV_VPZ_H:
    case AArch64::ANDQV_VPZ_S:
    case AArch64::EORQV_VPZ_B:
    case AArch64::EORQV_VPZ_D:
    case AArch64::EORQV_VPZ_H:
    case AArch64::EORQV_VPZ_S:
    case AArch64::FADDQV_D:
    case AArch64::FADDQV_H:
    case AArch64::FADDQV_S:
    case AArch64::FMAXNMQV_D:
    case AArch64::FMAXNMQV_H:
    case AArch64::FMAXNMQV_S:
    case AArch64::FMAXQV_D:
    case AArch64::FMAXQV_H:
    case AArch64::FMAXQV_S:
    case AArch64::FMINNMQV_D:
    case AArch64::FMINNMQV_H:
    case AArch64::FMINNMQV_S:
    case AArch64::FMINQV_D:
    case AArch64::FMINQV_H:
    case AArch64::FMINQV_S:
    case AArch64::ORQV_VPZ_B:
    case AArch64::ORQV_VPZ_D:
    case AArch64::ORQV_VPZ_H:
    case AArch64::ORQV_VPZ_S:
    case AArch64::SMAXQV_VPZ_B:
    case AArch64::SMAXQV_VPZ_D:
    case AArch64::SMAXQV_VPZ_H:
    case AArch64::SMAXQV_VPZ_S:
    case AArch64::SMINQV_VPZ_B:
    case AArch64::SMINQV_VPZ_D:
    case AArch64::SMINQV_VPZ_H:
    case AArch64::SMINQV_VPZ_S:
    case AArch64::UMAXQV_VPZ_B:
    case AArch64::UMAXQV_VPZ_D:
    case AArch64::UMAXQV_VPZ_H:
    case AArch64::UMAXQV_VPZ_S:
    case AArch64::UMINQV_VPZ_B:
    case AArch64::UMINQV_VPZ_D:
    case AArch64::UMINQV_VPZ_H:
    case AArch64::UMINQV_VPZ_S: {
      switch (OpNum) {
      case 0:
        // op: Vd
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 1:
        // op: Pg
        return 10;
      }
      break;
    }
    case AArch64::LD1Fourv16b:
    case AArch64::LD1Fourv1d:
    case AArch64::LD1Fourv2d:
    case AArch64::LD1Fourv2s:
    case AArch64::LD1Fourv4h:
    case AArch64::LD1Fourv4s:
    case AArch64::LD1Fourv8b:
    case AArch64::LD1Fourv8h:
    case AArch64::LD1Onev16b:
    case AArch64::LD1Onev1d:
    case AArch64::LD1Onev2d:
    case AArch64::LD1Onev2s:
    case AArch64::LD1Onev4h:
    case AArch64::LD1Onev4s:
    case AArch64::LD1Onev8b:
    case AArch64::LD1Onev8h:
    case AArch64::LD1Rv16b:
    case AArch64::LD1Rv1d:
    case AArch64::LD1Rv2d:
    case AArch64::LD1Rv2s:
    case AArch64::LD1Rv4h:
    case AArch64::LD1Rv4s:
    case AArch64::LD1Rv8b:
    case AArch64::LD1Rv8h:
    case AArch64::LD1Threev16b:
    case AArch64::LD1Threev1d:
    case AArch64::LD1Threev2d:
    case AArch64::LD1Threev2s:
    case AArch64::LD1Threev4h:
    case AArch64::LD1Threev4s:
    case AArch64::LD1Threev8b:
    case AArch64::LD1Threev8h:
    case AArch64::LD1Twov16b:
    case AArch64::LD1Twov1d:
    case AArch64::LD1Twov2d:
    case AArch64::LD1Twov2s:
    case AArch64::LD1Twov4h:
    case AArch64::LD1Twov4s:
    case AArch64::LD1Twov8b:
    case AArch64::LD1Twov8h:
    case AArch64::LD2Rv16b:
    case AArch64::LD2Rv1d:
    case AArch64::LD2Rv2d:
    case AArch64::LD2Rv2s:
    case AArch64::LD2Rv4h:
    case AArch64::LD2Rv4s:
    case AArch64::LD2Rv8b:
    case AArch64::LD2Rv8h:
    case AArch64::LD2Twov16b:
    case AArch64::LD2Twov2d:
    case AArch64::LD2Twov2s:
    case AArch64::LD2Twov4h:
    case AArch64::LD2Twov4s:
    case AArch64::LD2Twov8b:
    case AArch64::LD2Twov8h:
    case AArch64::LD3Rv16b:
    case AArch64::LD3Rv1d:
    case AArch64::LD3Rv2d:
    case AArch64::LD3Rv2s:
    case AArch64::LD3Rv4h:
    case AArch64::LD3Rv4s:
    case AArch64::LD3Rv8b:
    case AArch64::LD3Rv8h:
    case AArch64::LD3Threev16b:
    case AArch64::LD3Threev2d:
    case AArch64::LD3Threev2s:
    case AArch64::LD3Threev4h:
    case AArch64::LD3Threev4s:
    case AArch64::LD3Threev8b:
    case AArch64::LD3Threev8h:
    case AArch64::LD4Fourv16b:
    case AArch64::LD4Fourv2d:
    case AArch64::LD4Fourv2s:
    case AArch64::LD4Fourv4h:
    case AArch64::LD4Fourv4s:
    case AArch64::LD4Fourv8b:
    case AArch64::LD4Fourv8h:
    case AArch64::LD4Rv16b:
    case AArch64::LD4Rv1d:
    case AArch64::LD4Rv2d:
    case AArch64::LD4Rv2s:
    case AArch64::LD4Rv4h:
    case AArch64::LD4Rv4s:
    case AArch64::LD4Rv8b:
    case AArch64::LD4Rv8h:
    case AArch64::ST1Fourv16b:
    case AArch64::ST1Fourv1d:
    case AArch64::ST1Fourv2d:
    case AArch64::ST1Fourv2s:
    case AArch64::ST1Fourv4h:
    case AArch64::ST1Fourv4s:
    case AArch64::ST1Fourv8b:
    case AArch64::ST1Fourv8h:
    case AArch64::ST1Onev16b:
    case AArch64::ST1Onev1d:
    case AArch64::ST1Onev2d:
    case AArch64::ST1Onev2s:
    case AArch64::ST1Onev4h:
    case AArch64::ST1Onev4s:
    case AArch64::ST1Onev8b:
    case AArch64::ST1Onev8h:
    case AArch64::ST1Threev16b:
    case AArch64::ST1Threev1d:
    case AArch64::ST1Threev2d:
    case AArch64::ST1Threev2s:
    case AArch64::ST1Threev4h:
    case AArch64::ST1Threev4s:
    case AArch64::ST1Threev8b:
    case AArch64::ST1Threev8h:
    case AArch64::ST1Twov16b:
    case AArch64::ST1Twov1d:
    case AArch64::ST1Twov2d:
    case AArch64::ST1Twov2s:
    case AArch64::ST1Twov4h:
    case AArch64::ST1Twov4s:
    case AArch64::ST1Twov8b:
    case AArch64::ST1Twov8h:
    case AArch64::ST2Twov16b:
    case AArch64::ST2Twov2d:
    case AArch64::ST2Twov2s:
    case AArch64::ST2Twov4h:
    case AArch64::ST2Twov4s:
    case AArch64::ST2Twov8b:
    case AArch64::ST2Twov8h:
    case AArch64::ST3Threev16b:
    case AArch64::ST3Threev2d:
    case AArch64::ST3Threev2s:
    case AArch64::ST3Threev4h:
    case AArch64::ST3Threev4s:
    case AArch64::ST3Threev8b:
    case AArch64::ST3Threev8h:
    case AArch64::ST4Fourv16b:
    case AArch64::ST4Fourv2d:
    case AArch64::ST4Fourv2s:
    case AArch64::ST4Fourv4h:
    case AArch64::ST4Fourv4s:
    case AArch64::ST4Fourv8b:
    case AArch64::ST4Fourv8h: {
      switch (OpNum) {
      case 0:
        // op: Vt
        return 0;
      case 1:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::STL1: {
      switch (OpNum) {
      case 0:
        // op: Vt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: Q
        return 30;
      }
      break;
    }
    case AArch64::ST1i8:
    case AArch64::ST2i8:
    case AArch64::ST3i8:
    case AArch64::ST4i8: {
      switch (OpNum) {
      case 0:
        // op: Vt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: idx
        return 10;
      }
      break;
    }
    case AArch64::ST1i16:
    case AArch64::ST2i16:
    case AArch64::ST3i16:
    case AArch64::ST4i16: {
      switch (OpNum) {
      case 0:
        // op: Vt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: idx
        return 11;
      }
      break;
    }
    case AArch64::ST1i32:
    case AArch64::ST2i32:
    case AArch64::ST3i32:
    case AArch64::ST4i32: {
      switch (OpNum) {
      case 0:
        // op: Vt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: idx
        return 12;
      }
      break;
    }
    case AArch64::ST1i64:
    case AArch64::ST2i64:
    case AArch64::ST3i64:
    case AArch64::ST4i64: {
      switch (OpNum) {
      case 0:
        // op: Vt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: idx
        return 30;
      }
      break;
    }
    case AArch64::STLTXRW:
    case AArch64::STLTXRX:
    case AArch64::STLXRB:
    case AArch64::STLXRH:
    case AArch64::STLXRW:
    case AArch64::STLXRX:
    case AArch64::STXRB:
    case AArch64::STXRH:
    case AArch64::STXRW:
    case AArch64::STXRX: {
      switch (OpNum) {
      case 0:
        // op: Ws
        return 16;
      case 1:
        // op: Rt
        return 0;
      case 2:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::STLXPW:
    case AArch64::STLXPX:
    case AArch64::STXPW:
    case AArch64::STXPX: {
      switch (OpNum) {
      case 0:
        // op: Ws
        return 16;
      case 1:
        // op: Rt
        return 0;
      case 2:
        // op: Rt2
        return 10;
      case 3:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::TCHANGEBrr:
    case AArch64::TCHANGEFrr: {
      switch (OpNum) {
      case 0:
        // op: Xd
        return 0;
      case 1:
        // op: Xn
        return 5;
      case 2:
        // op: nb
        return 17;
      }
      break;
    }
    case AArch64::TCHANGEBri:
    case AArch64::TCHANGEFri: {
      switch (OpNum) {
      case 0:
        // op: Xd
        return 0;
      case 1:
        // op: imm
        return 5;
      case 2:
        // op: nb
        return 17;
      }
      break;
    }
    case AArch64::ADR:
    case AArch64::ADRP: {
      switch (OpNum) {
      case 0:
        // op: Xd
        return 0;
      case 1:
        // op: label
        return 5;
      }
      break;
    }
    case AArch64::APAS: {
      switch (OpNum) {
      case 0:
        // op: Xt
        return 0;
      }
      break;
    }
    case AArch64::BFTMOPA_M2ZZZI_HtoH:
    case AArch64::BFTMOPA_M2ZZZI_HtoS:
    case AArch64::FTMOPA_M2ZZZI_BtoH:
    case AArch64::FTMOPA_M2ZZZI_BtoS:
    case AArch64::FTMOPA_M2ZZZI_HtoH:
    case AArch64::FTMOPA_M2ZZZI_HtoS:
    case AArch64::FTMOPA_M2ZZZI_StoS:
    case AArch64::STMOPA_M2ZZZI_BtoS:
    case AArch64::STMOPA_M2ZZZI_HtoS:
    case AArch64::SUTMOPA_M2ZZZI_BtoS:
    case AArch64::USTMOPA_M2ZZZI_BtoS:
    case AArch64::UTMOPA_M2ZZZI_BtoS:
    case AArch64::UTMOPA_M2ZZZI_HtoS: {
      switch (OpNum) {
      case 0:
        // op: ZAda
        return 0;
      case 2:
        // op: Zn
        return 6;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: Zk
        return 10;
      case 5:
        // op: imm
        return 4;
      }
      break;
    }
    case AArch64::BFMOP4A_M2Z2Z_H:
    case AArch64::BFMOP4A_M2Z2Z_S:
    case AArch64::BFMOP4A_M2ZZ_H:
    case AArch64::BFMOP4A_M2ZZ_S:
    case AArch64::BFMOP4A_MZ2Z_H:
    case AArch64::BFMOP4A_MZ2Z_S:
    case AArch64::BFMOP4A_MZZ_H:
    case AArch64::BFMOP4A_MZZ_S:
    case AArch64::BFMOP4S_M2Z2Z_H:
    case AArch64::BFMOP4S_M2Z2Z_S:
    case AArch64::BFMOP4S_M2ZZ_H:
    case AArch64::BFMOP4S_M2ZZ_S:
    case AArch64::BFMOP4S_MZ2Z_H:
    case AArch64::BFMOP4S_MZ2Z_S:
    case AArch64::BFMOP4S_MZZ_H:
    case AArch64::BFMOP4S_MZZ_S:
    case AArch64::FMOP4A_M2Z2Z_BtoH:
    case AArch64::FMOP4A_M2Z2Z_BtoS:
    case AArch64::FMOP4A_M2Z2Z_D:
    case AArch64::FMOP4A_M2Z2Z_H:
    case AArch64::FMOP4A_M2Z2Z_HtoS:
    case AArch64::FMOP4A_M2Z2Z_S:
    case AArch64::FMOP4A_M2ZZ_BtoH:
    case AArch64::FMOP4A_M2ZZ_BtoS:
    case AArch64::FMOP4A_M2ZZ_D:
    case AArch64::FMOP4A_M2ZZ_H:
    case AArch64::FMOP4A_M2ZZ_HtoS:
    case AArch64::FMOP4A_M2ZZ_S:
    case AArch64::FMOP4A_MZ2Z_BtoH:
    case AArch64::FMOP4A_MZ2Z_BtoS:
    case AArch64::FMOP4A_MZ2Z_D:
    case AArch64::FMOP4A_MZ2Z_H:
    case AArch64::FMOP4A_MZ2Z_HtoS:
    case AArch64::FMOP4A_MZ2Z_S:
    case AArch64::FMOP4A_MZZ_BtoH:
    case AArch64::FMOP4A_MZZ_BtoS:
    case AArch64::FMOP4A_MZZ_D:
    case AArch64::FMOP4A_MZZ_H:
    case AArch64::FMOP4A_MZZ_HtoS:
    case AArch64::FMOP4A_MZZ_S:
    case AArch64::FMOP4S_M2Z2Z_D:
    case AArch64::FMOP4S_M2Z2Z_H:
    case AArch64::FMOP4S_M2Z2Z_HtoS:
    case AArch64::FMOP4S_M2Z2Z_S:
    case AArch64::FMOP4S_M2ZZ_D:
    case AArch64::FMOP4S_M2ZZ_H:
    case AArch64::FMOP4S_M2ZZ_HtoS:
    case AArch64::FMOP4S_M2ZZ_S:
    case AArch64::FMOP4S_MZ2Z_D:
    case AArch64::FMOP4S_MZ2Z_H:
    case AArch64::FMOP4S_MZ2Z_HtoS:
    case AArch64::FMOP4S_MZ2Z_S:
    case AArch64::FMOP4S_MZZ_D:
    case AArch64::FMOP4S_MZZ_H:
    case AArch64::FMOP4S_MZZ_HtoS:
    case AArch64::FMOP4S_MZZ_S:
    case AArch64::SMOP4A_M2Z2Z_BToS:
    case AArch64::SMOP4A_M2Z2Z_HToS:
    case AArch64::SMOP4A_M2Z2Z_HtoD:
    case AArch64::SMOP4A_M2ZZ_BToS:
    case AArch64::SMOP4A_M2ZZ_HToS:
    case AArch64::SMOP4A_M2ZZ_HtoD:
    case AArch64::SMOP4A_MZ2Z_BToS:
    case AArch64::SMOP4A_MZ2Z_HToS:
    case AArch64::SMOP4A_MZ2Z_HtoD:
    case AArch64::SMOP4A_MZZ_BToS:
    case AArch64::SMOP4A_MZZ_HToS:
    case AArch64::SMOP4A_MZZ_HtoD:
    case AArch64::SMOP4S_M2Z2Z_BToS:
    case AArch64::SMOP4S_M2Z2Z_HToS:
    case AArch64::SMOP4S_M2Z2Z_HtoD:
    case AArch64::SMOP4S_M2ZZ_BToS:
    case AArch64::SMOP4S_M2ZZ_HToS:
    case AArch64::SMOP4S_M2ZZ_HtoD:
    case AArch64::SMOP4S_MZ2Z_BToS:
    case AArch64::SMOP4S_MZ2Z_HToS:
    case AArch64::SMOP4S_MZ2Z_HtoD:
    case AArch64::SMOP4S_MZZ_BToS:
    case AArch64::SMOP4S_MZZ_HToS:
    case AArch64::SMOP4S_MZZ_HtoD:
    case AArch64::SUMOP4A_M2Z2Z_BToS:
    case AArch64::SUMOP4A_M2Z2Z_HtoD:
    case AArch64::SUMOP4A_M2ZZ_BToS:
    case AArch64::SUMOP4A_M2ZZ_HtoD:
    case AArch64::SUMOP4A_MZ2Z_BToS:
    case AArch64::SUMOP4A_MZ2Z_HtoD:
    case AArch64::SUMOP4A_MZZ_BToS:
    case AArch64::SUMOP4A_MZZ_HtoD:
    case AArch64::SUMOP4S_M2Z2Z_BToS:
    case AArch64::SUMOP4S_M2Z2Z_HtoD:
    case AArch64::SUMOP4S_M2ZZ_BToS:
    case AArch64::SUMOP4S_M2ZZ_HtoD:
    case AArch64::SUMOP4S_MZ2Z_BToS:
    case AArch64::SUMOP4S_MZ2Z_HtoD:
    case AArch64::SUMOP4S_MZZ_BToS:
    case AArch64::SUMOP4S_MZZ_HtoD:
    case AArch64::UMOP4A_M2Z2Z_BToS:
    case AArch64::UMOP4A_M2Z2Z_HToS:
    case AArch64::UMOP4A_M2Z2Z_HtoD:
    case AArch64::UMOP4A_M2ZZ_BToS:
    case AArch64::UMOP4A_M2ZZ_HToS:
    case AArch64::UMOP4A_M2ZZ_HtoD:
    case AArch64::UMOP4A_MZ2Z_BToS:
    case AArch64::UMOP4A_MZ2Z_HToS:
    case AArch64::UMOP4A_MZ2Z_HtoD:
    case AArch64::UMOP4A_MZZ_BToS:
    case AArch64::UMOP4A_MZZ_HToS:
    case AArch64::UMOP4A_MZZ_HtoD:
    case AArch64::UMOP4S_M2Z2Z_BToS:
    case AArch64::UMOP4S_M2Z2Z_HToS:
    case AArch64::UMOP4S_M2Z2Z_HtoD:
    case AArch64::UMOP4S_M2ZZ_BToS:
    case AArch64::UMOP4S_M2ZZ_HToS:
    case AArch64::UMOP4S_M2ZZ_HtoD:
    case AArch64::UMOP4S_MZ2Z_BToS:
    case AArch64::UMOP4S_MZ2Z_HToS:
    case AArch64::UMOP4S_MZ2Z_HtoD:
    case AArch64::UMOP4S_MZZ_BToS:
    case AArch64::UMOP4S_MZZ_HToS:
    case AArch64::UMOP4S_MZZ_HtoD:
    case AArch64::USMOP4A_M2Z2Z_BToS:
    case AArch64::USMOP4A_M2Z2Z_HtoD:
    case AArch64::USMOP4A_M2ZZ_BToS:
    case AArch64::USMOP4A_M2ZZ_HtoD:
    case AArch64::USMOP4A_MZ2Z_BToS:
    case AArch64::USMOP4A_MZ2Z_HtoD:
    case AArch64::USMOP4A_MZZ_BToS:
    case AArch64::USMOP4A_MZZ_HtoD:
    case AArch64::USMOP4S_M2Z2Z_BToS:
    case AArch64::USMOP4S_M2Z2Z_HtoD:
    case AArch64::USMOP4S_M2ZZ_BToS:
    case AArch64::USMOP4S_M2ZZ_HtoD:
    case AArch64::USMOP4S_MZ2Z_BToS:
    case AArch64::USMOP4S_MZ2Z_HtoD:
    case AArch64::USMOP4S_MZZ_BToS:
    case AArch64::USMOP4S_MZZ_HtoD: {
      switch (OpNum) {
      case 0:
        // op: ZAda
        return 0;
      case 2:
        // op: Zn
        return 6;
      case 3:
        // op: Zm
        return 17;
      }
      break;
    }
    case AArch64::RBIT_ZPzZ_B:
    case AArch64::RBIT_ZPzZ_D:
    case AArch64::RBIT_ZPzZ_H:
    case AArch64::RBIT_ZPzZ_S:
    case AArch64::REVB_ZPzZ_D:
    case AArch64::REVB_ZPzZ_H:
    case AArch64::REVB_ZPzZ_S:
    case AArch64::REVD_ZPzZ:
    case AArch64::REVH_ZPzZ_D:
    case AArch64::REVH_ZPzZ_S:
    case AArch64::REVW_ZPzZ_D: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::CPY_ZPzI_B:
    case AArch64::CPY_ZPzI_D:
    case AArch64::CPY_ZPzI_H:
    case AArch64::CPY_ZPzI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Pg
        return 16;
      case 2:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::LUTI6_S_4Z2Z2ZI: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: Zm
        return 16;
      case 3:
        // op: i1
        return 22;
      }
      break;
    }
    case AArch64::LUTI2_ZZZI_H: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: Zm
        return 16;
      case 3:
        // op: idx
        return 12;
      }
      break;
    }
    case AArch64::LUTI2_ZZZI_B:
    case AArch64::LUTI4_Z2ZZI:
    case AArch64::LUTI4_ZZZI_H: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: Zm
        return 16;
      case 3:
        // op: idx
        return 22;
      }
      break;
    }
    case AArch64::LUTI4_ZZZI_B:
    case AArch64::LUTI6_Z2ZZI_H: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: Zm
        return 16;
      case 3:
        // op: idx
        return 23;
      }
      break;
    }
    case AArch64::SMULLB_ZZZI_D:
    case AArch64::SMULLB_ZZZI_S:
    case AArch64::SMULLT_ZZZI_D:
    case AArch64::SMULLT_ZZZI_S:
    case AArch64::SQDMULLB_ZZZI_D:
    case AArch64::SQDMULLB_ZZZI_S:
    case AArch64::SQDMULLT_ZZZI_D:
    case AArch64::SQDMULLT_ZZZI_S:
    case AArch64::UMULLB_ZZZI_D:
    case AArch64::UMULLB_ZZZI_S:
    case AArch64::UMULLT_ZZZI_D:
    case AArch64::UMULLT_ZZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: Zm
        return 16;
      case 3:
        // op: iop
        return 11;
      }
      break;
    }
    case AArch64::BFMUL_ZZZI:
    case AArch64::FMUL_ZZZI_H:
    case AArch64::FMUL_ZZZI_S:
    case AArch64::MUL_ZZZI_H:
    case AArch64::MUL_ZZZI_S:
    case AArch64::SQDMULH_ZZZI_H:
    case AArch64::SQDMULH_ZZZI_S:
    case AArch64::SQRDMULH_ZZZI_H:
    case AArch64::SQRDMULH_ZZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: Zm
        return 16;
      case 3:
        // op: iop
        return 19;
      }
      break;
    }
    case AArch64::FMUL_ZZZI_D:
    case AArch64::MUL_ZZZI_D:
    case AArch64::SQDMULH_ZZZI_D:
    case AArch64::SQRDMULH_ZZZI_D: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: Zm
        return 16;
      case 3:
        // op: iop
        return 20;
      }
      break;
    }
    case AArch64::ADDHNB_ZZZ_B:
    case AArch64::ADDHNB_ZZZ_H:
    case AArch64::ADDHNB_ZZZ_S:
    case AArch64::ADR_LSL_ZZZ_D_0:
    case AArch64::ADR_LSL_ZZZ_D_1:
    case AArch64::ADR_LSL_ZZZ_D_2:
    case AArch64::ADR_LSL_ZZZ_D_3:
    case AArch64::ADR_LSL_ZZZ_S_0:
    case AArch64::ADR_LSL_ZZZ_S_1:
    case AArch64::ADR_LSL_ZZZ_S_2:
    case AArch64::ADR_LSL_ZZZ_S_3:
    case AArch64::ADR_SXTW_ZZZ_D_0:
    case AArch64::ADR_SXTW_ZZZ_D_1:
    case AArch64::ADR_SXTW_ZZZ_D_2:
    case AArch64::ADR_SXTW_ZZZ_D_3:
    case AArch64::ADR_UXTW_ZZZ_D_0:
    case AArch64::ADR_UXTW_ZZZ_D_1:
    case AArch64::ADR_UXTW_ZZZ_D_2:
    case AArch64::ADR_UXTW_ZZZ_D_3:
    case AArch64::BDEP_ZZZ_B:
    case AArch64::BDEP_ZZZ_D:
    case AArch64::BDEP_ZZZ_H:
    case AArch64::BDEP_ZZZ_S:
    case AArch64::BEXT_ZZZ_B:
    case AArch64::BEXT_ZZZ_D:
    case AArch64::BEXT_ZZZ_H:
    case AArch64::BEXT_ZZZ_S:
    case AArch64::BGRP_ZZZ_B:
    case AArch64::BGRP_ZZZ_D:
    case AArch64::BGRP_ZZZ_H:
    case AArch64::BGRP_ZZZ_S:
    case AArch64::HISTSEG_ZZZ:
    case AArch64::LUTI6_Z2ZZ:
    case AArch64::PMULLB_ZZZ_D:
    case AArch64::PMULLB_ZZZ_H:
    case AArch64::PMULLB_ZZZ_Q:
    case AArch64::PMULLT_ZZZ_D:
    case AArch64::PMULLT_ZZZ_H:
    case AArch64::PMULLT_ZZZ_Q:
    case AArch64::RADDHNB_ZZZ_B:
    case AArch64::RADDHNB_ZZZ_H:
    case AArch64::RADDHNB_ZZZ_S:
    case AArch64::RAX1_ZZZ_D:
    case AArch64::RSUBHNB_ZZZ_B:
    case AArch64::RSUBHNB_ZZZ_H:
    case AArch64::RSUBHNB_ZZZ_S:
    case AArch64::SABDLB_ZZZ_D:
    case AArch64::SABDLB_ZZZ_H:
    case AArch64::SABDLB_ZZZ_S:
    case AArch64::SABDLT_ZZZ_D:
    case AArch64::SABDLT_ZZZ_H:
    case AArch64::SABDLT_ZZZ_S:
    case AArch64::SADDLBT_ZZZ_D:
    case AArch64::SADDLBT_ZZZ_H:
    case AArch64::SADDLBT_ZZZ_S:
    case AArch64::SADDLB_ZZZ_D:
    case AArch64::SADDLB_ZZZ_H:
    case AArch64::SADDLB_ZZZ_S:
    case AArch64::SADDLT_ZZZ_D:
    case AArch64::SADDLT_ZZZ_H:
    case AArch64::SADDLT_ZZZ_S:
    case AArch64::SADDWB_ZZZ_D:
    case AArch64::SADDWB_ZZZ_H:
    case AArch64::SADDWB_ZZZ_S:
    case AArch64::SADDWT_ZZZ_D:
    case AArch64::SADDWT_ZZZ_H:
    case AArch64::SADDWT_ZZZ_S:
    case AArch64::SM4EKEY_ZZZ_S:
    case AArch64::SMULLB_ZZZ_D:
    case AArch64::SMULLB_ZZZ_H:
    case AArch64::SMULLB_ZZZ_S:
    case AArch64::SMULLT_ZZZ_D:
    case AArch64::SMULLT_ZZZ_H:
    case AArch64::SMULLT_ZZZ_S:
    case AArch64::SQDMULLB_ZZZ_D:
    case AArch64::SQDMULLB_ZZZ_H:
    case AArch64::SQDMULLB_ZZZ_S:
    case AArch64::SQDMULLT_ZZZ_D:
    case AArch64::SQDMULLT_ZZZ_H:
    case AArch64::SQDMULLT_ZZZ_S:
    case AArch64::SSUBLBT_ZZZ_D:
    case AArch64::SSUBLBT_ZZZ_H:
    case AArch64::SSUBLBT_ZZZ_S:
    case AArch64::SSUBLB_ZZZ_D:
    case AArch64::SSUBLB_ZZZ_H:
    case AArch64::SSUBLB_ZZZ_S:
    case AArch64::SSUBLTB_ZZZ_D:
    case AArch64::SSUBLTB_ZZZ_H:
    case AArch64::SSUBLTB_ZZZ_S:
    case AArch64::SSUBLT_ZZZ_D:
    case AArch64::SSUBLT_ZZZ_H:
    case AArch64::SSUBLT_ZZZ_S:
    case AArch64::SSUBWB_ZZZ_D:
    case AArch64::SSUBWB_ZZZ_H:
    case AArch64::SSUBWB_ZZZ_S:
    case AArch64::SSUBWT_ZZZ_D:
    case AArch64::SSUBWT_ZZZ_H:
    case AArch64::SSUBWT_ZZZ_S:
    case AArch64::SUBHNB_ZZZ_B:
    case AArch64::SUBHNB_ZZZ_H:
    case AArch64::SUBHNB_ZZZ_S:
    case AArch64::TBLQ_ZZZ_B:
    case AArch64::TBLQ_ZZZ_D:
    case AArch64::TBLQ_ZZZ_H:
    case AArch64::TBLQ_ZZZ_S:
    case AArch64::UABDLB_ZZZ_D:
    case AArch64::UABDLB_ZZZ_H:
    case AArch64::UABDLB_ZZZ_S:
    case AArch64::UABDLT_ZZZ_D:
    case AArch64::UABDLT_ZZZ_H:
    case AArch64::UABDLT_ZZZ_S:
    case AArch64::UADDLB_ZZZ_D:
    case AArch64::UADDLB_ZZZ_H:
    case AArch64::UADDLB_ZZZ_S:
    case AArch64::UADDLT_ZZZ_D:
    case AArch64::UADDLT_ZZZ_H:
    case AArch64::UADDLT_ZZZ_S:
    case AArch64::UADDWB_ZZZ_D:
    case AArch64::UADDWB_ZZZ_H:
    case AArch64::UADDWB_ZZZ_S:
    case AArch64::UADDWT_ZZZ_D:
    case AArch64::UADDWT_ZZZ_H:
    case AArch64::UADDWT_ZZZ_S:
    case AArch64::UMULLB_ZZZ_D:
    case AArch64::UMULLB_ZZZ_H:
    case AArch64::UMULLB_ZZZ_S:
    case AArch64::UMULLT_ZZZ_D:
    case AArch64::UMULLT_ZZZ_H:
    case AArch64::UMULLT_ZZZ_S:
    case AArch64::USUBLB_ZZZ_D:
    case AArch64::USUBLB_ZZZ_H:
    case AArch64::USUBLB_ZZZ_S:
    case AArch64::USUBLT_ZZZ_D:
    case AArch64::USUBLT_ZZZ_H:
    case AArch64::USUBLT_ZZZ_S:
    case AArch64::USUBWB_ZZZ_D:
    case AArch64::USUBWB_ZZZ_H:
    case AArch64::USUBWB_ZZZ_S:
    case AArch64::USUBWT_ZZZ_D:
    case AArch64::USUBWT_ZZZ_H:
    case AArch64::USUBWT_ZZZ_S:
    case AArch64::UZPQ1_ZZZ_B:
    case AArch64::UZPQ1_ZZZ_D:
    case AArch64::UZPQ1_ZZZ_H:
    case AArch64::UZPQ1_ZZZ_S:
    case AArch64::UZPQ2_ZZZ_B:
    case AArch64::UZPQ2_ZZZ_D:
    case AArch64::UZPQ2_ZZZ_H:
    case AArch64::UZPQ2_ZZZ_S:
    case AArch64::ZIPQ1_ZZZ_B:
    case AArch64::ZIPQ1_ZZZ_D:
    case AArch64::ZIPQ1_ZZZ_H:
    case AArch64::ZIPQ1_ZZZ_S:
    case AArch64::ZIPQ2_ZZZ_B:
    case AArch64::ZIPQ2_ZZZ_D:
    case AArch64::ZIPQ2_ZZZ_H:
    case AArch64::ZIPQ2_ZZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::DUP_ZZI_B: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: idx
        return 17;
      }
      break;
    }
    case AArch64::DUP_ZZI_H: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: idx
        return 18;
      }
      break;
    }
    case AArch64::DUP_ZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: idx
        return 19;
      }
      break;
    }
    case AArch64::DUP_ZZI_D: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: idx
        return 20;
      }
      break;
    }
    case AArch64::DUP_ZZI_Q: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: idx
        return 22;
      }
      break;
    }
    case AArch64::ASR_ZZI_B:
    case AArch64::ASR_ZZI_D:
    case AArch64::ASR_ZZI_H:
    case AArch64::ASR_ZZI_S:
    case AArch64::LSL_ZZI_B:
    case AArch64::LSL_ZZI_D:
    case AArch64::LSL_ZZI_H:
    case AArch64::LSL_ZZI_S:
    case AArch64::LSR_ZZI_B:
    case AArch64::LSR_ZZI_D:
    case AArch64::LSR_ZZI_H:
    case AArch64::LSR_ZZI_S:
    case AArch64::RSHRNB_ZZI_B:
    case AArch64::RSHRNB_ZZI_H:
    case AArch64::RSHRNB_ZZI_S:
    case AArch64::SHRNB_ZZI_B:
    case AArch64::SHRNB_ZZI_H:
    case AArch64::SHRNB_ZZI_S:
    case AArch64::SQRSHRNB_ZZI_B:
    case AArch64::SQRSHRNB_ZZI_H:
    case AArch64::SQRSHRNB_ZZI_S:
    case AArch64::SQRSHRUNB_ZZI_B:
    case AArch64::SQRSHRUNB_ZZI_H:
    case AArch64::SQRSHRUNB_ZZI_S:
    case AArch64::SQSHRNB_ZZI_B:
    case AArch64::SQSHRNB_ZZI_H:
    case AArch64::SQSHRNB_ZZI_S:
    case AArch64::SQSHRUNB_ZZI_B:
    case AArch64::SQSHRUNB_ZZI_H:
    case AArch64::SQSHRUNB_ZZI_S:
    case AArch64::SSHLLB_ZZI_D:
    case AArch64::SSHLLB_ZZI_H:
    case AArch64::SSHLLB_ZZI_S:
    case AArch64::SSHLLT_ZZI_D:
    case AArch64::SSHLLT_ZZI_H:
    case AArch64::SSHLLT_ZZI_S:
    case AArch64::UQRSHRNB_ZZI_B:
    case AArch64::UQRSHRNB_ZZI_H:
    case AArch64::UQRSHRNB_ZZI_S:
    case AArch64::UQSHRNB_ZZI_B:
    case AArch64::UQSHRNB_ZZI_H:
    case AArch64::UQSHRNB_ZZI_S:
    case AArch64::USHLLB_ZZI_D:
    case AArch64::USHLLB_ZZI_H:
    case AArch64::USHLLB_ZZI_S:
    case AArch64::USHLLT_ZZI_D:
    case AArch64::USHLLT_ZZI_H:
    case AArch64::USHLLT_ZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: imm
        return 16;
      }
      break;
    }
    case AArch64::EXT_ZZI_B: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: imm8
        return 10;
      }
      break;
    }
    case AArch64::DUPQ_ZZI_B: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: index
        return 17;
      }
      break;
    }
    case AArch64::DUPQ_ZZI_H: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: index
        return 18;
      }
      break;
    }
    case AArch64::DUPQ_ZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: index
        return 19;
      }
      break;
    }
    case AArch64::DUPQ_ZZI_D: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: index
        return 20;
      }
      break;
    }
    case AArch64::BF1CVTLT_ZZ_BtoH:
    case AArch64::BF1CVT_ZZ_BtoH:
    case AArch64::BF2CVTLT_ZZ_BtoH:
    case AArch64::BF2CVT_ZZ_BtoH:
    case AArch64::F1CVTLT_ZZ_BtoH:
    case AArch64::F1CVT_ZZ_BtoH:
    case AArch64::F2CVTLT_ZZ_BtoH:
    case AArch64::F2CVT_ZZ_BtoH:
    case AArch64::FEXPA_ZZ_D:
    case AArch64::FEXPA_ZZ_H:
    case AArch64::FEXPA_ZZ_S:
    case AArch64::FRECPE_ZZ_D:
    case AArch64::FRECPE_ZZ_H:
    case AArch64::FRECPE_ZZ_S:
    case AArch64::FRSQRTE_ZZ_D:
    case AArch64::FRSQRTE_ZZ_H:
    case AArch64::FRSQRTE_ZZ_S:
    case AArch64::MOVPRFX_ZZ:
    case AArch64::REV_ZZ_B:
    case AArch64::REV_ZZ_D:
    case AArch64::REV_ZZ_H:
    case AArch64::REV_ZZ_S:
    case AArch64::SCVTFLT_ZZ_BtoH:
    case AArch64::SCVTFLT_ZZ_HtoS:
    case AArch64::SCVTFLT_ZZ_StoD:
    case AArch64::SCVTF_ZZ_BtoH:
    case AArch64::SCVTF_ZZ_HtoS:
    case AArch64::SCVTF_ZZ_StoD:
    case AArch64::SQXTNB_ZZ_B:
    case AArch64::SQXTNB_ZZ_H:
    case AArch64::SQXTNB_ZZ_S:
    case AArch64::SQXTUNB_ZZ_B:
    case AArch64::SQXTUNB_ZZ_H:
    case AArch64::SQXTUNB_ZZ_S:
    case AArch64::SUNPKHI_ZZ_D:
    case AArch64::SUNPKHI_ZZ_H:
    case AArch64::SUNPKHI_ZZ_S:
    case AArch64::SUNPKLO_ZZ_D:
    case AArch64::SUNPKLO_ZZ_H:
    case AArch64::SUNPKLO_ZZ_S:
    case AArch64::UCVTFLT_ZZ_BtoH:
    case AArch64::UCVTFLT_ZZ_HtoS:
    case AArch64::UCVTFLT_ZZ_StoD:
    case AArch64::UCVTF_ZZ_BtoH:
    case AArch64::UCVTF_ZZ_HtoS:
    case AArch64::UCVTF_ZZ_StoD:
    case AArch64::UQXTNB_ZZ_B:
    case AArch64::UQXTNB_ZZ_H:
    case AArch64::UQXTNB_ZZ_S:
    case AArch64::UUNPKHI_ZZ_D:
    case AArch64::UUNPKHI_ZZ_H:
    case AArch64::UUNPKHI_ZZ_S:
    case AArch64::UUNPKLO_ZZ_D:
    case AArch64::UUNPKLO_ZZ_H:
    case AArch64::UUNPKLO_ZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::SQRSHRN_Z2ZI_HtoB:
    case AArch64::SQRSHRN_Z2ZI_StoH:
    case AArch64::SQRSHRUN_Z2ZI_HtoB:
    case AArch64::SQRSHRUN_Z2ZI_StoH:
    case AArch64::SQSHRN_Z2ZI_HtoB:
    case AArch64::SQSHRN_Z2ZI_StoH:
    case AArch64::SQSHRUN_Z2ZI_HtoB:
    case AArch64::SQSHRUN_Z2ZI_StoH:
    case AArch64::UQRSHRN_Z2ZI_HtoB:
    case AArch64::UQRSHRN_Z2ZI_StoH:
    case AArch64::UQSHRN_Z2ZI_HtoB:
    case AArch64::UQSHRN_Z2ZI_StoH: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 6;
      case 2:
        // op: imm
        return 16;
      }
      break;
    }
    case AArch64::BFCVTN_Z2Z_HtoB:
    case AArch64::FCVTNB_Z2Z_StoB:
    case AArch64::FCVTN_Z2Z_HtoB:
    case AArch64::FCVTZSN_Z2Z_DtoS:
    case AArch64::FCVTZSN_Z2Z_HtoB:
    case AArch64::FCVTZSN_Z2Z_StoH:
    case AArch64::FCVTZUN_Z2Z_DtoS:
    case AArch64::FCVTZUN_Z2Z_HtoB:
    case AArch64::FCVTZUN_Z2Z_StoH:
    case AArch64::SQCVTN_Z2Z_StoH:
    case AArch64::SQCVTUN_Z2Z_StoH:
    case AArch64::UQCVTN_Z2Z_StoH: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: Zn
        return 6;
      }
      break;
    }
    case AArch64::DUP_ZI_B:
    case AArch64::DUP_ZI_D:
    case AArch64::DUP_ZI_H:
    case AArch64::DUP_ZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::INDEX_II_B:
    case AArch64::INDEX_II_D:
    case AArch64::INDEX_II_H:
    case AArch64::INDEX_II_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: imm5
        return 5;
      case 2:
        // op: imm5b
        return 16;
      }
      break;
    }
    case AArch64::FDUP_ZI_D:
    case AArch64::FDUP_ZI_H:
    case AArch64::FDUP_ZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: imm8
        return 5;
      }
      break;
    }
    case AArch64::DUPM_ZI: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: imms
        return 5;
      }
      break;
    }
    case AArch64::RBIT_ZPmZ_B:
    case AArch64::RBIT_ZPmZ_D:
    case AArch64::RBIT_ZPmZ_H:
    case AArch64::RBIT_ZPmZ_S:
    case AArch64::REVB_ZPmZ_D:
    case AArch64::REVB_ZPmZ_H:
    case AArch64::REVB_ZPmZ_S:
    case AArch64::REVD_ZPmZ:
    case AArch64::REVH_ZPmZ_D:
    case AArch64::REVH_ZPmZ_S:
    case AArch64::REVW_ZPmZ_D: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Pg
        return 10;
      case 3:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::CPY_ZPmI_B:
    case AArch64::CPY_ZPmI_D:
    case AArch64::CPY_ZPmI_H:
    case AArch64::CPY_ZPmI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Pg
        return 16;
      case 3:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::INDEX_RR_B:
    case AArch64::INDEX_RR_D:
    case AArch64::INDEX_RR_H:
    case AArch64::INDEX_RR_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Rm
        return 16;
      case 1:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::ADDQP_ZZZ_B:
    case AArch64::ADDQP_ZZZ_D:
    case AArch64::ADDQP_ZZZ_H:
    case AArch64::ADDQP_ZZZ_S:
    case AArch64::ADDSUBP_ZZZ_B:
    case AArch64::ADDSUBP_ZZZ_D:
    case AArch64::ADDSUBP_ZZZ_H:
    case AArch64::ADDSUBP_ZZZ_S:
    case AArch64::ADD_ZZZ_B:
    case AArch64::ADD_ZZZ_CPA:
    case AArch64::ADD_ZZZ_D:
    case AArch64::ADD_ZZZ_H:
    case AArch64::ADD_ZZZ_S:
    case AArch64::AND_ZZZ:
    case AArch64::ASR_WIDE_ZZZ_B:
    case AArch64::ASR_WIDE_ZZZ_H:
    case AArch64::ASR_WIDE_ZZZ_S:
    case AArch64::BFADD_ZZZ:
    case AArch64::BFMUL_ZZZ:
    case AArch64::BFSUB_ZZZ:
    case AArch64::BIC_ZZZ:
    case AArch64::EOR_ZZZ:
    case AArch64::FADD_ZZZ_D:
    case AArch64::FADD_ZZZ_H:
    case AArch64::FADD_ZZZ_S:
    case AArch64::FMUL_ZZZ_D:
    case AArch64::FMUL_ZZZ_H:
    case AArch64::FMUL_ZZZ_S:
    case AArch64::FRECPS_ZZZ_D:
    case AArch64::FRECPS_ZZZ_H:
    case AArch64::FRECPS_ZZZ_S:
    case AArch64::FRSQRTS_ZZZ_D:
    case AArch64::FRSQRTS_ZZZ_H:
    case AArch64::FRSQRTS_ZZZ_S:
    case AArch64::FSUB_ZZZ_D:
    case AArch64::FSUB_ZZZ_H:
    case AArch64::FSUB_ZZZ_S:
    case AArch64::FTSMUL_ZZZ_D:
    case AArch64::FTSMUL_ZZZ_H:
    case AArch64::FTSMUL_ZZZ_S:
    case AArch64::FTSSEL_ZZZ_D:
    case AArch64::FTSSEL_ZZZ_H:
    case AArch64::FTSSEL_ZZZ_S:
    case AArch64::LSL_WIDE_ZZZ_B:
    case AArch64::LSL_WIDE_ZZZ_H:
    case AArch64::LSL_WIDE_ZZZ_S:
    case AArch64::LSR_WIDE_ZZZ_B:
    case AArch64::LSR_WIDE_ZZZ_H:
    case AArch64::LSR_WIDE_ZZZ_S:
    case AArch64::MUL_ZZZ_B:
    case AArch64::MUL_ZZZ_D:
    case AArch64::MUL_ZZZ_H:
    case AArch64::MUL_ZZZ_S:
    case AArch64::ORR_ZZZ:
    case AArch64::PMUL_ZZZ_B:
    case AArch64::SMULH_ZZZ_B:
    case AArch64::SMULH_ZZZ_D:
    case AArch64::SMULH_ZZZ_H:
    case AArch64::SMULH_ZZZ_S:
    case AArch64::SQADD_ZZZ_B:
    case AArch64::SQADD_ZZZ_D:
    case AArch64::SQADD_ZZZ_H:
    case AArch64::SQADD_ZZZ_S:
    case AArch64::SQDMULH_ZZZ_B:
    case AArch64::SQDMULH_ZZZ_D:
    case AArch64::SQDMULH_ZZZ_H:
    case AArch64::SQDMULH_ZZZ_S:
    case AArch64::SQRDMULH_ZZZ_B:
    case AArch64::SQRDMULH_ZZZ_D:
    case AArch64::SQRDMULH_ZZZ_H:
    case AArch64::SQRDMULH_ZZZ_S:
    case AArch64::SQSUB_ZZZ_B:
    case AArch64::SQSUB_ZZZ_D:
    case AArch64::SQSUB_ZZZ_H:
    case AArch64::SQSUB_ZZZ_S:
    case AArch64::SUB_ZZZ_B:
    case AArch64::SUB_ZZZ_CPA:
    case AArch64::SUB_ZZZ_D:
    case AArch64::SUB_ZZZ_H:
    case AArch64::SUB_ZZZ_S:
    case AArch64::TBL_ZZZZ_B:
    case AArch64::TBL_ZZZZ_D:
    case AArch64::TBL_ZZZZ_H:
    case AArch64::TBL_ZZZZ_S:
    case AArch64::TBL_ZZZ_B:
    case AArch64::TBL_ZZZ_D:
    case AArch64::TBL_ZZZ_H:
    case AArch64::TBL_ZZZ_S:
    case AArch64::TRN1_ZZZ_B:
    case AArch64::TRN1_ZZZ_D:
    case AArch64::TRN1_ZZZ_H:
    case AArch64::TRN1_ZZZ_Q:
    case AArch64::TRN1_ZZZ_S:
    case AArch64::TRN2_ZZZ_B:
    case AArch64::TRN2_ZZZ_D:
    case AArch64::TRN2_ZZZ_H:
    case AArch64::TRN2_ZZZ_Q:
    case AArch64::TRN2_ZZZ_S:
    case AArch64::UMULH_ZZZ_B:
    case AArch64::UMULH_ZZZ_D:
    case AArch64::UMULH_ZZZ_H:
    case AArch64::UMULH_ZZZ_S:
    case AArch64::UQADD_ZZZ_B:
    case AArch64::UQADD_ZZZ_D:
    case AArch64::UQADD_ZZZ_H:
    case AArch64::UQADD_ZZZ_S:
    case AArch64::UQSUB_ZZZ_B:
    case AArch64::UQSUB_ZZZ_D:
    case AArch64::UQSUB_ZZZ_H:
    case AArch64::UQSUB_ZZZ_S:
    case AArch64::UZP1_ZZZ_B:
    case AArch64::UZP1_ZZZ_D:
    case AArch64::UZP1_ZZZ_H:
    case AArch64::UZP1_ZZZ_Q:
    case AArch64::UZP1_ZZZ_S:
    case AArch64::UZP2_ZZZ_B:
    case AArch64::UZP2_ZZZ_D:
    case AArch64::UZP2_ZZZ_H:
    case AArch64::UZP2_ZZZ_Q:
    case AArch64::UZP2_ZZZ_S:
    case AArch64::ZIP1_ZZZ_B:
    case AArch64::ZIP1_ZZZ_D:
    case AArch64::ZIP1_ZZZ_H:
    case AArch64::ZIP1_ZZZ_Q:
    case AArch64::ZIP1_ZZZ_S:
    case AArch64::ZIP2_ZZZ_B:
    case AArch64::ZIP2_ZZZ_D:
    case AArch64::ZIP2_ZZZ_H:
    case AArch64::ZIP2_ZZZ_Q:
    case AArch64::ZIP2_ZZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Zm
        return 16;
      case 1:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::HISTCNT_ZPzZZ_D:
    case AArch64::HISTCNT_ZPzZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::FCVTLT_ZPzZ_HtoS:
    case AArch64::FCVTLT_ZPzZ_StoD: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 1:
        // op: Pg
        return 10;
      }
      break;
    }
    case AArch64::ADDHNT_ZZZ_B:
    case AArch64::ADDHNT_ZZZ_H:
    case AArch64::ADDHNT_ZZZ_S:
    case AArch64::EORBT_ZZZ_B:
    case AArch64::EORBT_ZZZ_D:
    case AArch64::EORBT_ZZZ_H:
    case AArch64::EORBT_ZZZ_S:
    case AArch64::EORTB_ZZZ_B:
    case AArch64::EORTB_ZZZ_D:
    case AArch64::EORTB_ZZZ_H:
    case AArch64::EORTB_ZZZ_S:
    case AArch64::RADDHNT_ZZZ_B:
    case AArch64::RADDHNT_ZZZ_H:
    case AArch64::RADDHNT_ZZZ_S:
    case AArch64::RSUBHNT_ZZZ_B:
    case AArch64::RSUBHNT_ZZZ_H:
    case AArch64::RSUBHNT_ZZZ_S:
    case AArch64::SUBHNT_ZZZ_B:
    case AArch64::SUBHNT_ZZZ_H:
    case AArch64::SUBHNT_ZZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::RSHRNT_ZZI_B:
    case AArch64::RSHRNT_ZZI_H:
    case AArch64::RSHRNT_ZZI_S:
    case AArch64::SHRNT_ZZI_B:
    case AArch64::SHRNT_ZZI_H:
    case AArch64::SHRNT_ZZI_S:
    case AArch64::SLI_ZZI_B:
    case AArch64::SLI_ZZI_D:
    case AArch64::SLI_ZZI_H:
    case AArch64::SLI_ZZI_S:
    case AArch64::SQRSHRNT_ZZI_B:
    case AArch64::SQRSHRNT_ZZI_H:
    case AArch64::SQRSHRNT_ZZI_S:
    case AArch64::SQRSHRUNT_ZZI_B:
    case AArch64::SQRSHRUNT_ZZI_H:
    case AArch64::SQRSHRUNT_ZZI_S:
    case AArch64::SQSHRNT_ZZI_B:
    case AArch64::SQSHRNT_ZZI_H:
    case AArch64::SQSHRNT_ZZI_S:
    case AArch64::SQSHRUNT_ZZI_B:
    case AArch64::SQSHRUNT_ZZI_H:
    case AArch64::SQSHRUNT_ZZI_S:
    case AArch64::SRI_ZZI_B:
    case AArch64::SRI_ZZI_D:
    case AArch64::SRI_ZZI_H:
    case AArch64::SRI_ZZI_S:
    case AArch64::UQRSHRNT_ZZI_B:
    case AArch64::UQRSHRNT_ZZI_H:
    case AArch64::UQRSHRNT_ZZI_S:
    case AArch64::UQSHRNT_ZZI_B:
    case AArch64::UQSHRNT_ZZI_H:
    case AArch64::UQSHRNT_ZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: imm
        return 16;
      }
      break;
    }
    case AArch64::LUTI6_ZTZ:
    case AArch64::SQXTNT_ZZ_B:
    case AArch64::SQXTNT_ZZ_H:
    case AArch64::SQXTNT_ZZ_S:
    case AArch64::SQXTUNT_ZZ_B:
    case AArch64::SQXTUNT_ZZ_H:
    case AArch64::SQXTUNT_ZZ_S:
    case AArch64::UQXTNT_ZZ_B:
    case AArch64::UQXTNT_ZZ_H:
    case AArch64::UQXTNT_ZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::FCVTNT_Z2Z_StoB: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Zn
        return 6;
      }
      break;
    }
    case AArch64::LUTI6_S_4ZT3Z: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Zn
        return 7;
      }
      break;
    }
    case AArch64::PMOV_ZIP_D:
    case AArch64::PMOV_ZIP_H:
    case AArch64::PMOV_ZIP_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: Pn
        return 5;
      case 2:
        // op: index
        return 17;
      }
      break;
    }
    case AArch64::PMOV_ZIP_B: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: Pn
        return 5;
      }
      break;
    }
    case AArch64::TBXQ_ZZZ_B:
    case AArch64::TBXQ_ZZZ_D:
    case AArch64::TBXQ_ZZZ_H:
    case AArch64::TBXQ_ZZZ_S:
    case AArch64::TBX_ZZZ_B:
    case AArch64::TBX_ZZZ_D:
    case AArch64::TBX_ZZZ_H:
    case AArch64::TBX_ZZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: Zm
        return 16;
      case 2:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::BFCVTNT_ZPmZ:
    case AArch64::BFCVTNT_ZPzZ_StoH:
    case AArch64::FCVTLT_ZPmZ_HtoS:
    case AArch64::FCVTLT_ZPmZ_StoD:
    case AArch64::FCVTNT_ZPmZ_DtoS:
    case AArch64::FCVTNT_ZPmZ_StoH:
    case AArch64::FCVTNT_ZPzZ_DtoS:
    case AArch64::FCVTNT_ZPzZ_StoH:
    case AArch64::FCVTXNT_ZPmZ_DtoS:
    case AArch64::FCVTXNT_ZPzZ_StoD: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: Zn
        return 5;
      case 2:
        // op: Pg
        return 10;
      }
      break;
    }
    case AArch64::BFMUL_2Z2Z:
    case AArch64::BFMUL_2ZZ:
    case AArch64::FMUL_2Z2Z_D:
    case AArch64::FMUL_2Z2Z_H:
    case AArch64::FMUL_2Z2Z_S:
    case AArch64::FMUL_2ZZ_D:
    case AArch64::FMUL_2ZZ_H:
    case AArch64::FMUL_2ZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 1:
        // op: Zn
        return 6;
      case 2:
        // op: Zm
        return 17;
      }
      break;
    }
    case AArch64::MOVA_2ZMXI_H_D:
    case AArch64::MOVA_2ZMXI_V_D: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 2:
        // op: Rs
        return 13;
      case 1:
        // op: ZAn
        return 5;
      }
      break;
    }
    case AArch64::MOVA_2ZMXI_H_S:
    case AArch64::MOVA_2ZMXI_V_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 2:
        // op: Rs
        return 13;
      case 1:
        // op: ZAn
        return 6;
      case 3:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVA_2ZMXI_H_H:
    case AArch64::MOVA_2ZMXI_V_H: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 2:
        // op: Rs
        return 13;
      case 1:
        // op: ZAn
        return 7;
      case 3:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVA_2ZMXI_H_B:
    case AArch64::MOVA_2ZMXI_V_B: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 2:
        // op: Rs
        return 13;
      case 3:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::UZP_VG2_2ZZZ_B:
    case AArch64::UZP_VG2_2ZZZ_D:
    case AArch64::UZP_VG2_2ZZZ_H:
    case AArch64::UZP_VG2_2ZZZ_Q:
    case AArch64::UZP_VG2_2ZZZ_S:
    case AArch64::ZIP_VG2_2ZZZ_B:
    case AArch64::ZIP_VG2_2ZZZ_D:
    case AArch64::ZIP_VG2_2ZZZ_H:
    case AArch64::ZIP_VG2_2ZZZ_Q:
    case AArch64::ZIP_VG2_2ZZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 2:
        // op: Zm
        return 16;
      case 1:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_2ZMI_H_D:
    case AArch64::MOVAZ_2ZMI_V_D: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 3:
        // op: Rs
        return 13;
      case 2:
        // op: ZAn
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_2ZMI_H_S:
    case AArch64::MOVAZ_2ZMI_V_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 3:
        // op: Rs
        return 13;
      case 2:
        // op: ZAn
        return 6;
      case 4:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_2ZMI_H_H:
    case AArch64::MOVAZ_2ZMI_V_H: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 3:
        // op: Rs
        return 13;
      case 2:
        // op: ZAn
        return 7;
      case 4:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_2ZMI_H_B:
    case AArch64::MOVAZ_2ZMI_V_B: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 1;
      case 3:
        // op: Rs
        return 13;
      case 4:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::LUTI6_4Z2Z2ZI: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 1:
        // op: Zn
        return 5;
      case 2:
        // op: Zm
        return 16;
      case 3:
        // op: i1
        return 22;
      }
      break;
    }
    case AArch64::BFMUL_4ZZ:
    case AArch64::FMUL_4ZZ_D:
    case AArch64::FMUL_4ZZ_H:
    case AArch64::FMUL_4ZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 1:
        // op: Zn
        return 7;
      case 2:
        // op: Zm
        return 17;
      }
      break;
    }
    case AArch64::BFMUL_4Z4Z:
    case AArch64::FMUL_4Z4Z_D:
    case AArch64::FMUL_4Z4Z_H:
    case AArch64::FMUL_4Z4Z_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 1:
        // op: Zn
        return 7;
      case 2:
        // op: Zm
        return 18;
      }
      break;
    }
    case AArch64::MOVA_4ZMXI_H_D:
    case AArch64::MOVA_4ZMXI_H_S:
    case AArch64::MOVA_4ZMXI_V_D:
    case AArch64::MOVA_4ZMXI_V_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 2:
        // op: Rs
        return 13;
      case 1:
        // op: ZAn
        return 5;
      }
      break;
    }
    case AArch64::MOVA_4ZMXI_H_H:
    case AArch64::MOVA_4ZMXI_V_H: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 2:
        // op: Rs
        return 13;
      case 1:
        // op: ZAn
        return 6;
      case 3:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVA_4ZMXI_H_B:
    case AArch64::MOVA_4ZMXI_V_B: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 2:
        // op: Rs
        return 13;
      case 3:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::LUTI6_4ZT3Z: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 2:
        // op: Zn
        return 7;
      }
      break;
    }
    case AArch64::MOVAZ_4ZMI_H_D:
    case AArch64::MOVAZ_4ZMI_H_S:
    case AArch64::MOVAZ_4ZMI_V_D:
    case AArch64::MOVAZ_4ZMI_V_S: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 3:
        // op: Rs
        return 13;
      case 2:
        // op: ZAn
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_4ZMI_H_H:
    case AArch64::MOVAZ_4ZMI_V_H: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 3:
        // op: Rs
        return 13;
      case 2:
        // op: ZAn
        return 6;
      case 4:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_4ZMI_H_B:
    case AArch64::MOVAZ_4ZMI_V_B: {
      switch (OpNum) {
      case 0:
        // op: Zd
        return 2;
      case 3:
        // op: Rs
        return 13;
      case 4:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::FCMLA_ZPmZZ_D:
    case AArch64::FCMLA_ZPmZZ_H:
    case AArch64::FCMLA_ZPmZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Zn
        return 5;
      case 4:
        // op: Zm
        return 16;
      case 5:
        // op: imm
        return 13;
      }
      break;
    }
    case AArch64::SDOT_ZZZI_HtoS:
    case AArch64::UDOT_ZZZI_HtoS: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: i2
        return 19;
      }
      break;
    }
    case AArch64::SUDOT_ZZZI:
    case AArch64::USDOT_ZZZI: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: idx
        return 19;
      }
      break;
    }
    case AArch64::FMLALB_ZZZI:
    case AArch64::FMLALLBB_ZZZI:
    case AArch64::FMLALLBT_ZZZI:
    case AArch64::FMLALLTB_ZZZI:
    case AArch64::FMLALLTT_ZZZI:
    case AArch64::FMLALT_ZZZI: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: imm4
        return 10;
      }
      break;
    }
    case AArch64::BFMLALB_ZZZI:
    case AArch64::BFMLALT_ZZZI:
    case AArch64::BFMLSLB_ZZZI_S:
    case AArch64::BFMLSLT_ZZZI_S:
    case AArch64::FDOT_ZZZI_BtoH:
    case AArch64::FMLALB_ZZZI_SHH:
    case AArch64::FMLALT_ZZZI_SHH:
    case AArch64::FMLSLB_ZZZI_SHH:
    case AArch64::FMLSLT_ZZZI_SHH:
    case AArch64::SMLALB_ZZZI_D:
    case AArch64::SMLALB_ZZZI_S:
    case AArch64::SMLALT_ZZZI_D:
    case AArch64::SMLALT_ZZZI_S:
    case AArch64::SMLSLB_ZZZI_D:
    case AArch64::SMLSLB_ZZZI_S:
    case AArch64::SMLSLT_ZZZI_D:
    case AArch64::SMLSLT_ZZZI_S:
    case AArch64::SQDMLALB_ZZZI_D:
    case AArch64::SQDMLALB_ZZZI_S:
    case AArch64::SQDMLALT_ZZZI_D:
    case AArch64::SQDMLALT_ZZZI_S:
    case AArch64::SQDMLSLB_ZZZI_D:
    case AArch64::SQDMLSLB_ZZZI_S:
    case AArch64::SQDMLSLT_ZZZI_D:
    case AArch64::SQDMLSLT_ZZZI_S:
    case AArch64::UMLALB_ZZZI_D:
    case AArch64::UMLALB_ZZZI_S:
    case AArch64::UMLALT_ZZZI_D:
    case AArch64::UMLALT_ZZZI_S:
    case AArch64::UMLSLB_ZZZI_D:
    case AArch64::UMLSLB_ZZZI_S:
    case AArch64::UMLSLT_ZZZI_D:
    case AArch64::UMLSLT_ZZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: iop
        return 11;
      }
      break;
    }
    case AArch64::BFDOT_ZZI:
    case AArch64::BFMLA_ZZZI:
    case AArch64::BFMLS_ZZZI:
    case AArch64::FDOT_ZZZI_BtoS:
    case AArch64::FDOT_ZZZI_S:
    case AArch64::FMLA_ZZZI_H:
    case AArch64::FMLA_ZZZI_S:
    case AArch64::FMLS_ZZZI_H:
    case AArch64::FMLS_ZZZI_S:
    case AArch64::MLA_ZZZI_H:
    case AArch64::MLA_ZZZI_S:
    case AArch64::MLS_ZZZI_H:
    case AArch64::MLS_ZZZI_S:
    case AArch64::SQRDMLAH_ZZZI_H:
    case AArch64::SQRDMLAH_ZZZI_S:
    case AArch64::SQRDMLSH_ZZZI_H:
    case AArch64::SQRDMLSH_ZZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: iop
        return 19;
      }
      break;
    }
    case AArch64::FMLA_ZZZI_D:
    case AArch64::FMLS_ZZZI_D:
    case AArch64::MLA_ZZZI_D:
    case AArch64::MLS_ZZZI_D:
    case AArch64::SQRDMLAH_ZZZI_D:
    case AArch64::SQRDMLSH_ZZZI_D: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: iop
        return 20;
      }
      break;
    }
    case AArch64::CDOT_ZZZ_D:
    case AArch64::CDOT_ZZZ_S:
    case AArch64::CMLA_ZZZ_B:
    case AArch64::CMLA_ZZZ_D:
    case AArch64::CMLA_ZZZ_H:
    case AArch64::CMLA_ZZZ_S:
    case AArch64::SQRDCMLAH_ZZZ_B:
    case AArch64::SQRDCMLAH_ZZZ_D:
    case AArch64::SQRDCMLAH_ZZZ_H:
    case AArch64::SQRDCMLAH_ZZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: rot
        return 10;
      }
      break;
    }
    case AArch64::ADCLB_ZZZ_D:
    case AArch64::ADCLB_ZZZ_S:
    case AArch64::ADCLT_ZZZ_D:
    case AArch64::ADCLT_ZZZ_S:
    case AArch64::BFDOT_ZZZ:
    case AArch64::BFMLALB_ZZZ:
    case AArch64::BFMLALT_ZZZ:
    case AArch64::BFMLSLB_ZZZ_S:
    case AArch64::BFMLSLT_ZZZ_S:
    case AArch64::BFMMLA_ZZZ_H:
    case AArch64::BFMMLA_ZZZ_HtoS:
    case AArch64::FDOT_ZZZ_BtoH:
    case AArch64::FDOT_ZZZ_BtoS:
    case AArch64::FDOT_ZZZ_S:
    case AArch64::FMLALB_ZZZ:
    case AArch64::FMLALB_ZZZ_SHH:
    case AArch64::FMLALLBB_ZZZ:
    case AArch64::FMLALLBT_ZZZ:
    case AArch64::FMLALLTB_ZZZ:
    case AArch64::FMLALLTT_ZZZ:
    case AArch64::FMLALT_ZZZ:
    case AArch64::FMLALT_ZZZ_SHH:
    case AArch64::FMLLA_ZZZ_HtoS:
    case AArch64::FMLSLB_ZZZ_SHH:
    case AArch64::FMLSLT_ZZZ_SHH:
    case AArch64::FMMLA_ZZZ_BtoH:
    case AArch64::FMMLA_ZZZ_BtoS:
    case AArch64::FMMLA_ZZZ_D:
    case AArch64::FMMLA_ZZZ_H:
    case AArch64::FMMLA_ZZZ_S:
    case AArch64::MLA_CPA:
    case AArch64::SABALB_ZZZ_D:
    case AArch64::SABALB_ZZZ_H:
    case AArch64::SABALB_ZZZ_S:
    case AArch64::SABALT_ZZZ_D:
    case AArch64::SABALT_ZZZ_H:
    case AArch64::SABALT_ZZZ_S:
    case AArch64::SABAL_ZZZ_BtoH:
    case AArch64::SABAL_ZZZ_HtoS:
    case AArch64::SABAL_ZZZ_StoD:
    case AArch64::SABA_ZZZ_B:
    case AArch64::SABA_ZZZ_D:
    case AArch64::SABA_ZZZ_H:
    case AArch64::SABA_ZZZ_S:
    case AArch64::SBCLB_ZZZ_D:
    case AArch64::SBCLB_ZZZ_S:
    case AArch64::SBCLT_ZZZ_D:
    case AArch64::SBCLT_ZZZ_S:
    case AArch64::SDOT_ZZZ_BtoH:
    case AArch64::SDOT_ZZZ_BtoS:
    case AArch64::SDOT_ZZZ_HtoD:
    case AArch64::SDOT_ZZZ_HtoS:
    case AArch64::SMLALB_ZZZ_D:
    case AArch64::SMLALB_ZZZ_H:
    case AArch64::SMLALB_ZZZ_S:
    case AArch64::SMLALT_ZZZ_D:
    case AArch64::SMLALT_ZZZ_H:
    case AArch64::SMLALT_ZZZ_S:
    case AArch64::SMLSLB_ZZZ_D:
    case AArch64::SMLSLB_ZZZ_H:
    case AArch64::SMLSLB_ZZZ_S:
    case AArch64::SMLSLT_ZZZ_D:
    case AArch64::SMLSLT_ZZZ_H:
    case AArch64::SMLSLT_ZZZ_S:
    case AArch64::SMMLA_ZZZ:
    case AArch64::SQDMLALBT_ZZZ_D:
    case AArch64::SQDMLALBT_ZZZ_H:
    case AArch64::SQDMLALBT_ZZZ_S:
    case AArch64::SQDMLALB_ZZZ_D:
    case AArch64::SQDMLALB_ZZZ_H:
    case AArch64::SQDMLALB_ZZZ_S:
    case AArch64::SQDMLALT_ZZZ_D:
    case AArch64::SQDMLALT_ZZZ_H:
    case AArch64::SQDMLALT_ZZZ_S:
    case AArch64::SQDMLSLBT_ZZZ_D:
    case AArch64::SQDMLSLBT_ZZZ_H:
    case AArch64::SQDMLSLBT_ZZZ_S:
    case AArch64::SQDMLSLB_ZZZ_D:
    case AArch64::SQDMLSLB_ZZZ_H:
    case AArch64::SQDMLSLB_ZZZ_S:
    case AArch64::SQDMLSLT_ZZZ_D:
    case AArch64::SQDMLSLT_ZZZ_H:
    case AArch64::SQDMLSLT_ZZZ_S:
    case AArch64::SQRDMLAH_ZZZ_B:
    case AArch64::SQRDMLAH_ZZZ_D:
    case AArch64::SQRDMLAH_ZZZ_H:
    case AArch64::SQRDMLAH_ZZZ_S:
    case AArch64::SQRDMLSH_ZZZ_B:
    case AArch64::SQRDMLSH_ZZZ_D:
    case AArch64::SQRDMLSH_ZZZ_H:
    case AArch64::SQRDMLSH_ZZZ_S:
    case AArch64::UABALB_ZZZ_D:
    case AArch64::UABALB_ZZZ_H:
    case AArch64::UABALB_ZZZ_S:
    case AArch64::UABALT_ZZZ_D:
    case AArch64::UABALT_ZZZ_H:
    case AArch64::UABALT_ZZZ_S:
    case AArch64::UABAL_ZZZ_BtoH:
    case AArch64::UABAL_ZZZ_HtoS:
    case AArch64::UABAL_ZZZ_StoD:
    case AArch64::UABA_ZZZ_B:
    case AArch64::UABA_ZZZ_D:
    case AArch64::UABA_ZZZ_H:
    case AArch64::UABA_ZZZ_S:
    case AArch64::UDOT_ZZZ_BtoH:
    case AArch64::UDOT_ZZZ_BtoS:
    case AArch64::UDOT_ZZZ_HtoD:
    case AArch64::UDOT_ZZZ_HtoS:
    case AArch64::UMLALB_ZZZ_D:
    case AArch64::UMLALB_ZZZ_H:
    case AArch64::UMLALB_ZZZ_S:
    case AArch64::UMLALT_ZZZ_D:
    case AArch64::UMLALT_ZZZ_H:
    case AArch64::UMLALT_ZZZ_S:
    case AArch64::UMLSLB_ZZZ_D:
    case AArch64::UMLSLB_ZZZ_H:
    case AArch64::UMLSLB_ZZZ_S:
    case AArch64::UMLSLT_ZZZ_D:
    case AArch64::UMLSLT_ZZZ_H:
    case AArch64::UMLSLT_ZZZ_S:
    case AArch64::UMMLA_ZZZ:
    case AArch64::USDOT_ZZZ:
    case AArch64::USMMLA_ZZZ: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::SRSRA_ZZI_B:
    case AArch64::SRSRA_ZZI_D:
    case AArch64::SRSRA_ZZI_H:
    case AArch64::SRSRA_ZZI_S:
    case AArch64::SSRA_ZZI_B:
    case AArch64::SSRA_ZZI_D:
    case AArch64::SSRA_ZZI_H:
    case AArch64::SSRA_ZZI_S:
    case AArch64::URSRA_ZZI_B:
    case AArch64::URSRA_ZZI_D:
    case AArch64::URSRA_ZZI_H:
    case AArch64::URSRA_ZZI_S:
    case AArch64::USRA_ZZI_B:
    case AArch64::USRA_ZZI_D:
    case AArch64::USRA_ZZI_H:
    case AArch64::USRA_ZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: imm
        return 16;
      }
      break;
    }
    case AArch64::SDOT_ZZZI_BtoH:
    case AArch64::SDOT_ZZZI_BtoS:
    case AArch64::UDOT_ZZZI_BtoH:
    case AArch64::UDOT_ZZZI_BtoS: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 4:
        // op: iop
        return 19;
      case 3:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::SDOT_ZZZI_HtoD:
    case AArch64::UDOT_ZZZI_HtoD: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 4:
        // op: iop
        return 20;
      case 3:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::FCMLA_ZZZI_H: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 5:
        // op: imm
        return 10;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: iop
        return 19;
      }
      break;
    }
    case AArch64::FCMLA_ZZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 5:
        // op: imm
        return 10;
      case 3:
        // op: Zm
        return 16;
      case 4:
        // op: iop
        return 20;
      }
      break;
    }
    case AArch64::CDOT_ZZZI_S:
    case AArch64::CMLA_ZZZI_H:
    case AArch64::SQRDCMLAH_ZZZI_H: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 5:
        // op: rot
        return 10;
      case 4:
        // op: iop
        return 19;
      case 3:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::CDOT_ZZZI_D:
    case AArch64::CMLA_ZZZI_S:
    case AArch64::SQRDCMLAH_ZZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zda
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 5:
        // op: rot
        return 10;
      case 4:
        // op: iop
        return 20;
      case 3:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::MAD_CPA: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: Zm
        return 16;
      case 3:
        // op: Za
        return 5;
      }
      break;
    }
    case AArch64::XAR_ZZZI_B:
    case AArch64::XAR_ZZZI_D:
    case AArch64::XAR_ZZZI_H:
    case AArch64::XAR_ZZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: Zm
        return 5;
      case 3:
        // op: imm
        return 16;
      }
      break;
    }
    case AArch64::FTMAD_ZZI_D:
    case AArch64::FTMAD_ZZI_H:
    case AArch64::FTMAD_ZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: Zm
        return 5;
      case 3:
        // op: imm3
        return 16;
      }
      break;
    }
    case AArch64::EXTQ_ZZI: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: Zm
        return 5;
      case 3:
        // op: imm4
        return 16;
      }
      break;
    }
    case AArch64::EXT_ZZI: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: Zm
        return 5;
      case 3:
        // op: imm8
        return 10;
      }
      break;
    }
    case AArch64::CADD_ZZI_B:
    case AArch64::CADD_ZZI_D:
    case AArch64::CADD_ZZI_H:
    case AArch64::CADD_ZZI_S:
    case AArch64::SQCADD_ZZI_B:
    case AArch64::SQCADD_ZZI_D:
    case AArch64::SQCADD_ZZI_H:
    case AArch64::SQCADD_ZZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: Zm
        return 5;
      case 3:
        // op: rot
        return 10;
      }
      break;
    }
    case AArch64::AESD_ZZZ_B:
    case AArch64::AESE_ZZZ_B:
    case AArch64::SM4E_ZZZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: Zm
        return 5;
      }
      break;
    }
    case AArch64::ADD_ZI_B:
    case AArch64::ADD_ZI_D:
    case AArch64::ADD_ZI_H:
    case AArch64::ADD_ZI_S:
    case AArch64::MUL_ZI_B:
    case AArch64::MUL_ZI_D:
    case AArch64::MUL_ZI_H:
    case AArch64::MUL_ZI_S:
    case AArch64::SMAX_ZI_B:
    case AArch64::SMAX_ZI_D:
    case AArch64::SMAX_ZI_H:
    case AArch64::SMAX_ZI_S:
    case AArch64::SMIN_ZI_B:
    case AArch64::SMIN_ZI_D:
    case AArch64::SMIN_ZI_H:
    case AArch64::SMIN_ZI_S:
    case AArch64::SQADD_ZI_B:
    case AArch64::SQADD_ZI_D:
    case AArch64::SQADD_ZI_H:
    case AArch64::SQADD_ZI_S:
    case AArch64::SQSUB_ZI_B:
    case AArch64::SQSUB_ZI_D:
    case AArch64::SQSUB_ZI_H:
    case AArch64::SQSUB_ZI_S:
    case AArch64::SUBR_ZI_B:
    case AArch64::SUBR_ZI_D:
    case AArch64::SUBR_ZI_H:
    case AArch64::SUBR_ZI_S:
    case AArch64::SUB_ZI_B:
    case AArch64::SUB_ZI_D:
    case AArch64::SUB_ZI_H:
    case AArch64::SUB_ZI_S:
    case AArch64::UMAX_ZI_B:
    case AArch64::UMAX_ZI_D:
    case AArch64::UMAX_ZI_H:
    case AArch64::UMAX_ZI_S:
    case AArch64::UMIN_ZI_B:
    case AArch64::UMIN_ZI_D:
    case AArch64::UMIN_ZI_H:
    case AArch64::UMIN_ZI_S:
    case AArch64::UQADD_ZI_B:
    case AArch64::UQADD_ZI_D:
    case AArch64::UQADD_ZI_H:
    case AArch64::UQADD_ZI_S:
    case AArch64::UQSUB_ZI_B:
    case AArch64::UQSUB_ZI_D:
    case AArch64::UQSUB_ZI_H:
    case AArch64::UQSUB_ZI_S: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::AND_ZI:
    case AArch64::EOR_ZI:
    case AArch64::ORR_ZI: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: imms13
        return 5;
      }
      break;
    }
    case AArch64::DECD_ZPiI:
    case AArch64::DECH_ZPiI:
    case AArch64::DECW_ZPiI:
    case AArch64::INCD_ZPiI:
    case AArch64::INCH_ZPiI:
    case AArch64::INCW_ZPiI:
    case AArch64::SQDECD_ZPiI:
    case AArch64::SQDECH_ZPiI:
    case AArch64::SQDECW_ZPiI:
    case AArch64::SQINCD_ZPiI:
    case AArch64::SQINCH_ZPiI:
    case AArch64::SQINCW_ZPiI:
    case AArch64::UQDECD_ZPiI:
    case AArch64::UQDECH_ZPiI:
    case AArch64::UQDECW_ZPiI:
    case AArch64::UQINCD_ZPiI:
    case AArch64::UQINCH_ZPiI:
    case AArch64::UQINCW_ZPiI: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 2:
        // op: pattern
        return 5;
      case 3:
        // op: imm4
        return 16;
      }
      break;
    }
    case AArch64::BCAX_ZZZZ:
    case AArch64::BSL1N_ZZZZ:
    case AArch64::BSL2N_ZZZZ:
    case AArch64::BSL_ZZZZ:
    case AArch64::EOR3_ZZZZ:
    case AArch64::NBSL_ZZZZ: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 3:
        // op: Zk
        return 5;
      case 2:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::FCADD_ZPmZ_D:
    case AArch64::FCADD_ZPmZ_H:
    case AArch64::FCADD_ZPmZ_S: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      case 3:
        // op: Zm
        return 5;
      case 1:
        // op: Pg
        return 10;
      case 4:
        // op: imm
        return 16;
      }
      break;
    }
    case AArch64::AESIMC_ZZ_B:
    case AArch64::AESMC_ZZ_B: {
      switch (OpNum) {
      case 0:
        // op: Zdn
        return 0;
      }
      break;
    }
    case AArch64::LD1RO_B:
    case AArch64::LD1RO_D:
    case AArch64::LD1RO_H:
    case AArch64::LD1RO_W:
    case AArch64::LD1RQ_B:
    case AArch64::LD1RQ_D:
    case AArch64::LD1RQ_H:
    case AArch64::LD1RQ_W: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: Rm
        return 16;
      }
      break;
    }
    case AArch64::LD2B_IMM:
    case AArch64::LD2D_IMM:
    case AArch64::LD2H_IMM:
    case AArch64::LD2Q_IMM:
    case AArch64::LD2W_IMM:
    case AArch64::LD3B_IMM:
    case AArch64::LD3D_IMM:
    case AArch64::LD3H_IMM:
    case AArch64::LD3Q_IMM:
    case AArch64::LD3W_IMM:
    case AArch64::LD4B_IMM:
    case AArch64::LD4D_IMM:
    case AArch64::LD4H_IMM:
    case AArch64::LD4Q_IMM:
    case AArch64::LD4W_IMM:
    case AArch64::LDNT1B_ZRI:
    case AArch64::LDNT1D_ZRI:
    case AArch64::LDNT1H_ZRI:
    case AArch64::LDNT1W_ZRI: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: imm4
        return 16;
      }
      break;
    }
    case AArch64::LD1B:
    case AArch64::LD1B_D:
    case AArch64::LD1B_H:
    case AArch64::LD1B_S:
    case AArch64::LD1D:
    case AArch64::LD1H:
    case AArch64::LD1H_D:
    case AArch64::LD1H_S:
    case AArch64::LD1SB_D:
    case AArch64::LD1SB_H:
    case AArch64::LD1SB_S:
    case AArch64::LD1SH_D:
    case AArch64::LD1SH_S:
    case AArch64::LD1SW_D:
    case AArch64::LD1W:
    case AArch64::LD1W_D:
    case AArch64::LDFF1B:
    case AArch64::LDFF1B_D:
    case AArch64::LDFF1B_H:
    case AArch64::LDFF1B_S:
    case AArch64::LDFF1D:
    case AArch64::LDFF1H:
    case AArch64::LDFF1H_D:
    case AArch64::LDFF1H_S:
    case AArch64::LDFF1SB_D:
    case AArch64::LDFF1SB_H:
    case AArch64::LDFF1SB_S:
    case AArch64::LDFF1SH_D:
    case AArch64::LDFF1SH_S:
    case AArch64::LDFF1SW_D:
    case AArch64::LDFF1W:
    case AArch64::LDFF1W_D: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 0;
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Rm
        return 16;
      case 2:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::LD1D_Q:
    case AArch64::LD1W_Q:
    case AArch64::ST2Q:
    case AArch64::ST3Q:
    case AArch64::ST4Q: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Rm
        return 16;
      }
      break;
    }
    case AArch64::LD1D_Q_IMM:
    case AArch64::LD1RO_B_IMM:
    case AArch64::LD1RO_D_IMM:
    case AArch64::LD1RO_H_IMM:
    case AArch64::LD1RO_W_IMM:
    case AArch64::LD1RQ_B_IMM:
    case AArch64::LD1RQ_D_IMM:
    case AArch64::LD1RQ_H_IMM:
    case AArch64::LD1RQ_W_IMM:
    case AArch64::LD1W_Q_IMM:
    case AArch64::ST2Q_IMM:
    case AArch64::ST3Q_IMM:
    case AArch64::ST4Q_IMM: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: imm4
        return 16;
      }
      break;
    }
    case AArch64::GLD1Q:
    case AArch64::SST1Q: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 0;
      case 2:
        // op: Zn
        return 5;
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Rm
        return 16;
      }
      break;
    }
    case AArch64::LD1B_2Z_IMM:
    case AArch64::LD1D_2Z_IMM:
    case AArch64::LD1H_2Z_IMM:
    case AArch64::LD1W_2Z_IMM:
    case AArch64::LDNT1B_2Z_IMM:
    case AArch64::LDNT1D_2Z_IMM:
    case AArch64::LDNT1H_2Z_IMM:
    case AArch64::LDNT1W_2Z_IMM:
    case AArch64::ST1B_2Z_IMM:
    case AArch64::ST1D_2Z_IMM:
    case AArch64::ST1H_2Z_IMM:
    case AArch64::ST1W_2Z_IMM:
    case AArch64::STNT1B_2Z_IMM:
    case AArch64::STNT1D_2Z_IMM:
    case AArch64::STNT1H_2Z_IMM:
    case AArch64::STNT1W_2Z_IMM: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 1;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: PNg
        return 10;
      case 3:
        // op: imm4
        return 16;
      }
      break;
    }
    case AArch64::LD1B_2Z:
    case AArch64::LD1D_2Z:
    case AArch64::LD1H_2Z:
    case AArch64::LD1W_2Z:
    case AArch64::LDNT1B_2Z:
    case AArch64::LDNT1D_2Z:
    case AArch64::LDNT1H_2Z:
    case AArch64::LDNT1W_2Z:
    case AArch64::ST1B_2Z:
    case AArch64::ST1D_2Z:
    case AArch64::ST1H_2Z:
    case AArch64::ST1W_2Z:
    case AArch64::STNT1B_2Z:
    case AArch64::STNT1D_2Z:
    case AArch64::STNT1H_2Z:
    case AArch64::STNT1W_2Z: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 1;
      case 3:
        // op: Rm
        return 16;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: PNg
        return 10;
      }
      break;
    }
    case AArch64::LD1B_4Z_IMM:
    case AArch64::LD1D_4Z_IMM:
    case AArch64::LD1H_4Z_IMM:
    case AArch64::LD1W_4Z_IMM:
    case AArch64::LDNT1B_4Z_IMM:
    case AArch64::LDNT1D_4Z_IMM:
    case AArch64::LDNT1H_4Z_IMM:
    case AArch64::LDNT1W_4Z_IMM:
    case AArch64::ST1B_4Z_IMM:
    case AArch64::ST1D_4Z_IMM:
    case AArch64::ST1H_4Z_IMM:
    case AArch64::ST1W_4Z_IMM:
    case AArch64::STNT1B_4Z_IMM:
    case AArch64::STNT1D_4Z_IMM:
    case AArch64::STNT1H_4Z_IMM:
    case AArch64::STNT1W_4Z_IMM: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 2;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: PNg
        return 10;
      case 3:
        // op: imm4
        return 16;
      }
      break;
    }
    case AArch64::LD1B_4Z:
    case AArch64::LD1D_4Z:
    case AArch64::LD1H_4Z:
    case AArch64::LD1W_4Z:
    case AArch64::LDNT1B_4Z:
    case AArch64::LDNT1D_4Z:
    case AArch64::LDNT1H_4Z:
    case AArch64::LDNT1W_4Z:
    case AArch64::ST1B_4Z:
    case AArch64::ST1D_4Z:
    case AArch64::ST1H_4Z:
    case AArch64::ST1W_4Z:
    case AArch64::STNT1B_4Z:
    case AArch64::STNT1D_4Z:
    case AArch64::STNT1H_4Z:
    case AArch64::STNT1W_4Z: {
      switch (OpNum) {
      case 0:
        // op: Zt
        return 2;
      case 3:
        // op: Rm
        return 16;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: PNg
        return 10;
      }
      break;
    }
    case AArch64::B:
    case AArch64::BL: {
      switch (OpNum) {
      case 0:
        // op: addr
        return 0;
      }
      break;
    }
    case AArch64::BCcc:
    case AArch64::Bcc: {
      switch (OpNum) {
      case 0:
        // op: cond
        return 0;
      case 1:
        // op: target
        return 5;
      }
      break;
    }
    case AArch64::DUPi8: {
      switch (OpNum) {
      case 0:
        // op: dst
        return 0;
      case 1:
        // op: src
        return 5;
      case 2:
        // op: idx
        return 17;
      }
      break;
    }
    case AArch64::DUPi16: {
      switch (OpNum) {
      case 0:
        // op: dst
        return 0;
      case 1:
        // op: src
        return 5;
      case 2:
        // op: idx
        return 18;
      }
      break;
    }
    case AArch64::DUPi32: {
      switch (OpNum) {
      case 0:
        // op: dst
        return 0;
      case 1:
        // op: src
        return 5;
      case 2:
        // op: idx
        return 19;
      }
      break;
    }
    case AArch64::DUPi64: {
      switch (OpNum) {
      case 0:
        // op: dst
        return 0;
      case 1:
        // op: src
        return 5;
      case 2:
        // op: idx
        return 20;
      }
      break;
    }
    case AArch64::UDF:
    case AArch64::ZERO_M: {
      switch (OpNum) {
      case 0:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::TENTER: {
      switch (OpNum) {
      case 0:
        // op: imm
        return 5;
      case 1:
        // op: nb
        return 17;
      }
      break;
    }
    case AArch64::BRK:
    case AArch64::DCPS1:
    case AArch64::DCPS2:
    case AArch64::DCPS3:
    case AArch64::HINT:
    case AArch64::HLT:
    case AArch64::HVC:
    case AArch64::SMC:
    case AArch64::SVC: {
      switch (OpNum) {
      case 0:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::AUTIASPPCi:
    case AArch64::AUTIBSPPCi:
    case AArch64::RETAASPPCi:
    case AArch64::RETABSPPCi: {
      switch (OpNum) {
      case 0:
        // op: label
        return 5;
      }
      break;
    }
    case AArch64::TEXIT: {
      switch (OpNum) {
      case 0:
        // op: nb
        return 10;
      }
      break;
    }
    case AArch64::SYSPxt_XZR: {
      switch (OpNum) {
      case 0:
        // op: op1
        return 16;
      case 1:
        // op: Cn
        return 12;
      case 2:
        // op: Cm
        return 8;
      case 3:
        // op: op2
        return 5;
      }
      break;
    }
    case AArch64::STSHH: {
      switch (OpNum) {
      case 0:
        // op: policy
        return 5;
      }
      break;
    }
    case AArch64::SHUH: {
      switch (OpNum) {
      case 0:
        // op: priority
        return 5;
      }
      break;
    }
    case AArch64::MSRpstateImm1:
    case AArch64::MSRpstateImm4: {
      switch (OpNum) {
      case 0:
        // op: pstatefield
        return 5;
      case 1:
        // op: imm
        return 8;
      }
      break;
    }
    case AArch64::MSRpstatesvcrImm1: {
      switch (OpNum) {
      case 0:
        // op: pstatefield
        return 9;
      case 1:
        // op: imm
        return 8;
      }
      break;
    }
    case AArch64::SEL_VG2_2ZC2Z2Z_B:
    case AArch64::SEL_VG2_2ZC2Z2Z_D:
    case AArch64::SEL_VG2_2ZC2Z2Z_H:
    case AArch64::SEL_VG2_2ZC2Z2Z_S: {
      switch (OpNum) {
      case 1:
        // op: PNg
        return 10;
      case 3:
        // op: Zm
        return 17;
      case 2:
        // op: Zn
        return 6;
      case 0:
        // op: Zd
        return 1;
      }
      break;
    }
    case AArch64::SEL_VG4_4ZC4Z4Z_B:
    case AArch64::SEL_VG4_4ZC4Z4Z_D:
    case AArch64::SEL_VG4_4ZC4Z4Z_H:
    case AArch64::SEL_VG4_4ZC4Z4Z_S: {
      switch (OpNum) {
      case 1:
        // op: PNg
        return 10;
      case 3:
        // op: Zm
        return 18;
      case 2:
        // op: Zn
        return 7;
      case 0:
        // op: Zd
        return 2;
      }
      break;
    }
    case AArch64::LASTA_RPZ_B:
    case AArch64::LASTA_RPZ_D:
    case AArch64::LASTA_RPZ_H:
    case AArch64::LASTA_RPZ_S:
    case AArch64::LASTB_RPZ_B:
    case AArch64::LASTB_RPZ_D:
    case AArch64::LASTB_RPZ_H:
    case AArch64::LASTB_RPZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Rd
        return 0;
      case 2:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::CLASTA_RPZ_B:
    case AArch64::CLASTA_RPZ_D:
    case AArch64::CLASTA_RPZ_H:
    case AArch64::CLASTA_RPZ_S:
    case AArch64::CLASTB_RPZ_B:
    case AArch64::CLASTB_RPZ_D:
    case AArch64::CLASTB_RPZ_H:
    case AArch64::CLASTB_RPZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Rdn
        return 0;
      case 3:
        // op: Zm
        return 5;
      }
      break;
    }
    case AArch64::ANDV_VPZ_B:
    case AArch64::ANDV_VPZ_D:
    case AArch64::ANDV_VPZ_H:
    case AArch64::ANDV_VPZ_S:
    case AArch64::EORV_VPZ_B:
    case AArch64::EORV_VPZ_D:
    case AArch64::EORV_VPZ_H:
    case AArch64::EORV_VPZ_S:
    case AArch64::LASTA_VPZ_B:
    case AArch64::LASTA_VPZ_D:
    case AArch64::LASTA_VPZ_H:
    case AArch64::LASTA_VPZ_S:
    case AArch64::LASTB_VPZ_B:
    case AArch64::LASTB_VPZ_D:
    case AArch64::LASTB_VPZ_H:
    case AArch64::LASTB_VPZ_S:
    case AArch64::ORV_VPZ_B:
    case AArch64::ORV_VPZ_D:
    case AArch64::ORV_VPZ_H:
    case AArch64::ORV_VPZ_S:
    case AArch64::SADDV_VPZ_B:
    case AArch64::SADDV_VPZ_H:
    case AArch64::SADDV_VPZ_S:
    case AArch64::SMAXV_VPZ_B:
    case AArch64::SMAXV_VPZ_D:
    case AArch64::SMAXV_VPZ_H:
    case AArch64::SMAXV_VPZ_S:
    case AArch64::SMINV_VPZ_B:
    case AArch64::SMINV_VPZ_D:
    case AArch64::SMINV_VPZ_H:
    case AArch64::SMINV_VPZ_S:
    case AArch64::UADDV_VPZ_B:
    case AArch64::UADDV_VPZ_D:
    case AArch64::UADDV_VPZ_H:
    case AArch64::UADDV_VPZ_S:
    case AArch64::UMAXV_VPZ_B:
    case AArch64::UMAXV_VPZ_D:
    case AArch64::UMAXV_VPZ_H:
    case AArch64::UMAXV_VPZ_S:
    case AArch64::UMINV_VPZ_B:
    case AArch64::UMINV_VPZ_D:
    case AArch64::UMINV_VPZ_H:
    case AArch64::UMINV_VPZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Vd
        return 0;
      case 2:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::CLASTA_VPZ_B:
    case AArch64::CLASTA_VPZ_D:
    case AArch64::CLASTA_VPZ_H:
    case AArch64::CLASTA_VPZ_S:
    case AArch64::CLASTB_VPZ_B:
    case AArch64::CLASTB_VPZ_D:
    case AArch64::CLASTB_VPZ_H:
    case AArch64::CLASTB_VPZ_S:
    case AArch64::FADDA_VPZ_D:
    case AArch64::FADDA_VPZ_H:
    case AArch64::FADDA_VPZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Vdn
        return 0;
      case 3:
        // op: Zm
        return 5;
      }
      break;
    }
    case AArch64::ABS_ZPzZ_B:
    case AArch64::ABS_ZPzZ_D:
    case AArch64::ABS_ZPzZ_H:
    case AArch64::ABS_ZPzZ_S:
    case AArch64::BFCVT_ZPzZ_StoH:
    case AArch64::CLS_ZPzZ_B:
    case AArch64::CLS_ZPzZ_D:
    case AArch64::CLS_ZPzZ_H:
    case AArch64::CLS_ZPzZ_S:
    case AArch64::CLZ_ZPzZ_B:
    case AArch64::CLZ_ZPzZ_D:
    case AArch64::CLZ_ZPzZ_H:
    case AArch64::CLZ_ZPzZ_S:
    case AArch64::CNOT_ZPzZ_B:
    case AArch64::CNOT_ZPzZ_D:
    case AArch64::CNOT_ZPzZ_H:
    case AArch64::CNOT_ZPzZ_S:
    case AArch64::CNT_ZPzZ_B:
    case AArch64::CNT_ZPzZ_D:
    case AArch64::CNT_ZPzZ_H:
    case AArch64::CNT_ZPzZ_S:
    case AArch64::COMPACT_ZPZ_B:
    case AArch64::COMPACT_ZPZ_D:
    case AArch64::COMPACT_ZPZ_H:
    case AArch64::COMPACT_ZPZ_S:
    case AArch64::FABS_ZPzZ_D:
    case AArch64::FABS_ZPzZ_H:
    case AArch64::FABS_ZPzZ_S:
    case AArch64::FCVTX_ZPzZ_DtoS:
    case AArch64::FCVTZS_ZPzZ_DtoD:
    case AArch64::FCVTZS_ZPzZ_DtoS:
    case AArch64::FCVTZS_ZPzZ_HtoD:
    case AArch64::FCVTZS_ZPzZ_HtoH:
    case AArch64::FCVTZS_ZPzZ_HtoS:
    case AArch64::FCVTZS_ZPzZ_StoD:
    case AArch64::FCVTZS_ZPzZ_StoS:
    case AArch64::FCVTZU_ZPzZ_DtoD:
    case AArch64::FCVTZU_ZPzZ_DtoS:
    case AArch64::FCVTZU_ZPzZ_HtoD:
    case AArch64::FCVTZU_ZPzZ_HtoH:
    case AArch64::FCVTZU_ZPzZ_HtoS:
    case AArch64::FCVTZU_ZPzZ_StoD:
    case AArch64::FCVTZU_ZPzZ_StoS:
    case AArch64::FCVT_ZPzZ_DtoH:
    case AArch64::FCVT_ZPzZ_DtoS:
    case AArch64::FCVT_ZPzZ_HtoD:
    case AArch64::FCVT_ZPzZ_HtoS:
    case AArch64::FCVT_ZPzZ_StoD:
    case AArch64::FCVT_ZPzZ_StoH:
    case AArch64::FLOGB_ZPzZ_D:
    case AArch64::FLOGB_ZPzZ_H:
    case AArch64::FLOGB_ZPzZ_S:
    case AArch64::FNEG_ZPzZ_D:
    case AArch64::FNEG_ZPzZ_H:
    case AArch64::FNEG_ZPzZ_S:
    case AArch64::FRECPX_ZPzZ_D:
    case AArch64::FRECPX_ZPzZ_H:
    case AArch64::FRECPX_ZPzZ_S:
    case AArch64::FRINT32X_ZPzZ_D:
    case AArch64::FRINT32X_ZPzZ_S:
    case AArch64::FRINT32Z_ZPzZ_D:
    case AArch64::FRINT32Z_ZPzZ_S:
    case AArch64::FRINT64X_ZPzZ_D:
    case AArch64::FRINT64X_ZPzZ_S:
    case AArch64::FRINT64Z_ZPzZ_D:
    case AArch64::FRINT64Z_ZPzZ_S:
    case AArch64::FRINTA_ZPzZ_D:
    case AArch64::FRINTA_ZPzZ_H:
    case AArch64::FRINTA_ZPzZ_S:
    case AArch64::FRINTI_ZPzZ_D:
    case AArch64::FRINTI_ZPzZ_H:
    case AArch64::FRINTI_ZPzZ_S:
    case AArch64::FRINTM_ZPzZ_D:
    case AArch64::FRINTM_ZPzZ_H:
    case AArch64::FRINTM_ZPzZ_S:
    case AArch64::FRINTN_ZPzZ_D:
    case AArch64::FRINTN_ZPzZ_H:
    case AArch64::FRINTN_ZPzZ_S:
    case AArch64::FRINTP_ZPzZ_D:
    case AArch64::FRINTP_ZPzZ_H:
    case AArch64::FRINTP_ZPzZ_S:
    case AArch64::FRINTX_ZPzZ_D:
    case AArch64::FRINTX_ZPzZ_H:
    case AArch64::FRINTX_ZPzZ_S:
    case AArch64::FRINTZ_ZPzZ_D:
    case AArch64::FRINTZ_ZPzZ_H:
    case AArch64::FRINTZ_ZPzZ_S:
    case AArch64::FSQRT_ZPZz_D:
    case AArch64::FSQRT_ZPZz_H:
    case AArch64::FSQRT_ZPZz_S:
    case AArch64::MOVPRFX_ZPzZ_B:
    case AArch64::MOVPRFX_ZPzZ_D:
    case AArch64::MOVPRFX_ZPzZ_H:
    case AArch64::MOVPRFX_ZPzZ_S:
    case AArch64::NEG_ZPzZ_B:
    case AArch64::NEG_ZPzZ_D:
    case AArch64::NEG_ZPzZ_H:
    case AArch64::NEG_ZPzZ_S:
    case AArch64::NOT_ZPzZ_B:
    case AArch64::NOT_ZPzZ_D:
    case AArch64::NOT_ZPzZ_H:
    case AArch64::NOT_ZPzZ_S:
    case AArch64::SCVTF_ZPzZ_DtoD:
    case AArch64::SCVTF_ZPzZ_DtoH:
    case AArch64::SCVTF_ZPzZ_DtoS:
    case AArch64::SCVTF_ZPzZ_HtoH:
    case AArch64::SCVTF_ZPzZ_StoD:
    case AArch64::SCVTF_ZPzZ_StoH:
    case AArch64::SCVTF_ZPzZ_StoS:
    case AArch64::SQABS_ZPzZ_B:
    case AArch64::SQABS_ZPzZ_D:
    case AArch64::SQABS_ZPzZ_H:
    case AArch64::SQABS_ZPzZ_S:
    case AArch64::SQNEG_ZPzZ_B:
    case AArch64::SQNEG_ZPzZ_D:
    case AArch64::SQNEG_ZPzZ_H:
    case AArch64::SQNEG_ZPzZ_S:
    case AArch64::SXTB_ZPzZ_D:
    case AArch64::SXTB_ZPzZ_H:
    case AArch64::SXTB_ZPzZ_S:
    case AArch64::SXTH_ZPzZ_D:
    case AArch64::SXTH_ZPzZ_S:
    case AArch64::SXTW_ZPzZ_D:
    case AArch64::UCVTF_ZPzZ_DtoD:
    case AArch64::UCVTF_ZPzZ_DtoH:
    case AArch64::UCVTF_ZPzZ_DtoS:
    case AArch64::UCVTF_ZPzZ_HtoH:
    case AArch64::UCVTF_ZPzZ_StoD:
    case AArch64::UCVTF_ZPzZ_StoH:
    case AArch64::UCVTF_ZPzZ_StoS:
    case AArch64::URECPE_ZPzZ_S:
    case AArch64::URSQRTE_ZPzZ_S:
    case AArch64::UXTB_ZPzZ_D:
    case AArch64::UXTB_ZPzZ_H:
    case AArch64::UXTB_ZPzZ_S:
    case AArch64::UXTH_ZPzZ_D:
    case AArch64::UXTH_ZPzZ_S:
    case AArch64::UXTW_ZPzZ_D: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::SEL_ZPZZ_B:
    case AArch64::SEL_ZPZZ_D:
    case AArch64::SEL_ZPZZ_H:
    case AArch64::SEL_ZPZZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: Zm
        return 16;
      case 2:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::BFMLA_ZPmZZ:
    case AArch64::BFMLS_ZPmZZ:
    case AArch64::FMLA_ZPmZZ_D:
    case AArch64::FMLA_ZPmZZ_H:
    case AArch64::FMLA_ZPmZZ_S:
    case AArch64::FMLS_ZPmZZ_D:
    case AArch64::FMLS_ZPmZZ_H:
    case AArch64::FMLS_ZPmZZ_S:
    case AArch64::FNMLA_ZPmZZ_D:
    case AArch64::FNMLA_ZPmZZ_H:
    case AArch64::FNMLA_ZPmZZ_S:
    case AArch64::FNMLS_ZPmZZ_D:
    case AArch64::FNMLS_ZPmZZ_H:
    case AArch64::FNMLS_ZPmZZ_S:
    case AArch64::MLA_ZPmZZ_B:
    case AArch64::MLA_ZPmZZ_D:
    case AArch64::MLA_ZPmZZ_H:
    case AArch64::MLA_ZPmZZ_S:
    case AArch64::MLS_ZPmZZ_B:
    case AArch64::MLS_ZPmZZ_D:
    case AArch64::MLS_ZPmZZ_H:
    case AArch64::MLS_ZPmZZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Zda
        return 0;
      case 4:
        // op: Zm
        return 16;
      case 3:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::ADD_ZPmZ_B:
    case AArch64::ADD_ZPmZ_CPA:
    case AArch64::ADD_ZPmZ_D:
    case AArch64::ADD_ZPmZ_H:
    case AArch64::ADD_ZPmZ_S:
    case AArch64::AND_ZPmZ_B:
    case AArch64::AND_ZPmZ_D:
    case AArch64::AND_ZPmZ_H:
    case AArch64::AND_ZPmZ_S:
    case AArch64::ASRR_ZPmZ_B:
    case AArch64::ASRR_ZPmZ_D:
    case AArch64::ASRR_ZPmZ_H:
    case AArch64::ASRR_ZPmZ_S:
    case AArch64::ASR_WIDE_ZPmZ_B:
    case AArch64::ASR_WIDE_ZPmZ_H:
    case AArch64::ASR_WIDE_ZPmZ_S:
    case AArch64::ASR_ZPmZ_B:
    case AArch64::ASR_ZPmZ_D:
    case AArch64::ASR_ZPmZ_H:
    case AArch64::ASR_ZPmZ_S:
    case AArch64::BFADD_ZPmZZ:
    case AArch64::BFMAXNM_ZPmZZ:
    case AArch64::BFMAX_ZPmZZ:
    case AArch64::BFMINNM_ZPmZZ:
    case AArch64::BFMIN_ZPmZZ:
    case AArch64::BFMUL_ZPmZZ:
    case AArch64::BFSCALE_ZPZZ_H:
    case AArch64::BFSUB_ZPmZZ:
    case AArch64::BIC_ZPmZ_B:
    case AArch64::BIC_ZPmZ_D:
    case AArch64::BIC_ZPmZ_H:
    case AArch64::BIC_ZPmZ_S:
    case AArch64::CLASTA_ZPZ_B:
    case AArch64::CLASTA_ZPZ_D:
    case AArch64::CLASTA_ZPZ_H:
    case AArch64::CLASTA_ZPZ_S:
    case AArch64::CLASTB_ZPZ_B:
    case AArch64::CLASTB_ZPZ_D:
    case AArch64::CLASTB_ZPZ_H:
    case AArch64::CLASTB_ZPZ_S:
    case AArch64::EOR_ZPmZ_B:
    case AArch64::EOR_ZPmZ_D:
    case AArch64::EOR_ZPmZ_H:
    case AArch64::EOR_ZPmZ_S:
    case AArch64::FABD_ZPmZ_D:
    case AArch64::FABD_ZPmZ_H:
    case AArch64::FABD_ZPmZ_S:
    case AArch64::FADD_ZPmZ_D:
    case AArch64::FADD_ZPmZ_H:
    case AArch64::FADD_ZPmZ_S:
    case AArch64::FAMAX_ZPmZ_D:
    case AArch64::FAMAX_ZPmZ_H:
    case AArch64::FAMAX_ZPmZ_S:
    case AArch64::FAMIN_ZPmZ_D:
    case AArch64::FAMIN_ZPmZ_H:
    case AArch64::FAMIN_ZPmZ_S:
    case AArch64::FDIVR_ZPmZ_D:
    case AArch64::FDIVR_ZPmZ_H:
    case AArch64::FDIVR_ZPmZ_S:
    case AArch64::FDIV_ZPmZ_D:
    case AArch64::FDIV_ZPmZ_H:
    case AArch64::FDIV_ZPmZ_S:
    case AArch64::FMAXNM_ZPmZ_D:
    case AArch64::FMAXNM_ZPmZ_H:
    case AArch64::FMAXNM_ZPmZ_S:
    case AArch64::FMAX_ZPmZ_D:
    case AArch64::FMAX_ZPmZ_H:
    case AArch64::FMAX_ZPmZ_S:
    case AArch64::FMINNM_ZPmZ_D:
    case AArch64::FMINNM_ZPmZ_H:
    case AArch64::FMINNM_ZPmZ_S:
    case AArch64::FMIN_ZPmZ_D:
    case AArch64::FMIN_ZPmZ_H:
    case AArch64::FMIN_ZPmZ_S:
    case AArch64::FMULX_ZPmZ_D:
    case AArch64::FMULX_ZPmZ_H:
    case AArch64::FMULX_ZPmZ_S:
    case AArch64::FMUL_ZPmZ_D:
    case AArch64::FMUL_ZPmZ_H:
    case AArch64::FMUL_ZPmZ_S:
    case AArch64::FSCALE_ZPmZ_D:
    case AArch64::FSCALE_ZPmZ_H:
    case AArch64::FSCALE_ZPmZ_S:
    case AArch64::FSUBR_ZPmZ_D:
    case AArch64::FSUBR_ZPmZ_H:
    case AArch64::FSUBR_ZPmZ_S:
    case AArch64::FSUB_ZPmZ_D:
    case AArch64::FSUB_ZPmZ_H:
    case AArch64::FSUB_ZPmZ_S:
    case AArch64::LSLR_ZPmZ_B:
    case AArch64::LSLR_ZPmZ_D:
    case AArch64::LSLR_ZPmZ_H:
    case AArch64::LSLR_ZPmZ_S:
    case AArch64::LSL_WIDE_ZPmZ_B:
    case AArch64::LSL_WIDE_ZPmZ_H:
    case AArch64::LSL_WIDE_ZPmZ_S:
    case AArch64::LSL_ZPmZ_B:
    case AArch64::LSL_ZPmZ_D:
    case AArch64::LSL_ZPmZ_H:
    case AArch64::LSL_ZPmZ_S:
    case AArch64::LSRR_ZPmZ_B:
    case AArch64::LSRR_ZPmZ_D:
    case AArch64::LSRR_ZPmZ_H:
    case AArch64::LSRR_ZPmZ_S:
    case AArch64::LSR_WIDE_ZPmZ_B:
    case AArch64::LSR_WIDE_ZPmZ_H:
    case AArch64::LSR_WIDE_ZPmZ_S:
    case AArch64::LSR_ZPmZ_B:
    case AArch64::LSR_ZPmZ_D:
    case AArch64::LSR_ZPmZ_H:
    case AArch64::LSR_ZPmZ_S:
    case AArch64::MUL_ZPmZ_B:
    case AArch64::MUL_ZPmZ_D:
    case AArch64::MUL_ZPmZ_H:
    case AArch64::MUL_ZPmZ_S:
    case AArch64::ORR_ZPmZ_B:
    case AArch64::ORR_ZPmZ_D:
    case AArch64::ORR_ZPmZ_H:
    case AArch64::ORR_ZPmZ_S:
    case AArch64::SABD_ZPmZ_B:
    case AArch64::SABD_ZPmZ_D:
    case AArch64::SABD_ZPmZ_H:
    case AArch64::SABD_ZPmZ_S:
    case AArch64::SDIVR_ZPmZ_D:
    case AArch64::SDIVR_ZPmZ_S:
    case AArch64::SDIV_ZPmZ_D:
    case AArch64::SDIV_ZPmZ_S:
    case AArch64::SMAX_ZPmZ_B:
    case AArch64::SMAX_ZPmZ_D:
    case AArch64::SMAX_ZPmZ_H:
    case AArch64::SMAX_ZPmZ_S:
    case AArch64::SMIN_ZPmZ_B:
    case AArch64::SMIN_ZPmZ_D:
    case AArch64::SMIN_ZPmZ_H:
    case AArch64::SMIN_ZPmZ_S:
    case AArch64::SMULH_ZPmZ_B:
    case AArch64::SMULH_ZPmZ_D:
    case AArch64::SMULH_ZPmZ_H:
    case AArch64::SMULH_ZPmZ_S:
    case AArch64::SPLICE_ZPZ_B:
    case AArch64::SPLICE_ZPZ_D:
    case AArch64::SPLICE_ZPZ_H:
    case AArch64::SPLICE_ZPZ_S:
    case AArch64::SUBR_ZPmZ_B:
    case AArch64::SUBR_ZPmZ_D:
    case AArch64::SUBR_ZPmZ_H:
    case AArch64::SUBR_ZPmZ_S:
    case AArch64::SUB_ZPmZ_B:
    case AArch64::SUB_ZPmZ_CPA:
    case AArch64::SUB_ZPmZ_D:
    case AArch64::SUB_ZPmZ_H:
    case AArch64::SUB_ZPmZ_S:
    case AArch64::UABD_ZPmZ_B:
    case AArch64::UABD_ZPmZ_D:
    case AArch64::UABD_ZPmZ_H:
    case AArch64::UABD_ZPmZ_S:
    case AArch64::UDIVR_ZPmZ_D:
    case AArch64::UDIVR_ZPmZ_S:
    case AArch64::UDIV_ZPmZ_D:
    case AArch64::UDIV_ZPmZ_S:
    case AArch64::UMAX_ZPmZ_B:
    case AArch64::UMAX_ZPmZ_D:
    case AArch64::UMAX_ZPmZ_H:
    case AArch64::UMAX_ZPmZ_S:
    case AArch64::UMIN_ZPmZ_B:
    case AArch64::UMIN_ZPmZ_D:
    case AArch64::UMIN_ZPmZ_H:
    case AArch64::UMIN_ZPmZ_S:
    case AArch64::UMULH_ZPmZ_B:
    case AArch64::UMULH_ZPmZ_D:
    case AArch64::UMULH_ZPmZ_H:
    case AArch64::UMULH_ZPmZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Zdn
        return 0;
      case 3:
        // op: Zm
        return 5;
      }
      break;
    }
    case AArch64::FADD_ZPmI_D:
    case AArch64::FADD_ZPmI_H:
    case AArch64::FADD_ZPmI_S:
    case AArch64::FMAXNM_ZPmI_D:
    case AArch64::FMAXNM_ZPmI_H:
    case AArch64::FMAXNM_ZPmI_S:
    case AArch64::FMAX_ZPmI_D:
    case AArch64::FMAX_ZPmI_H:
    case AArch64::FMAX_ZPmI_S:
    case AArch64::FMINNM_ZPmI_D:
    case AArch64::FMINNM_ZPmI_H:
    case AArch64::FMINNM_ZPmI_S:
    case AArch64::FMIN_ZPmI_D:
    case AArch64::FMIN_ZPmI_H:
    case AArch64::FMIN_ZPmI_S:
    case AArch64::FMUL_ZPmI_D:
    case AArch64::FMUL_ZPmI_H:
    case AArch64::FMUL_ZPmI_S:
    case AArch64::FSUBR_ZPmI_D:
    case AArch64::FSUBR_ZPmI_H:
    case AArch64::FSUBR_ZPmI_S:
    case AArch64::FSUB_ZPmI_D:
    case AArch64::FSUB_ZPmI_H:
    case AArch64::FSUB_ZPmI_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Zdn
        return 0;
      case 3:
        // op: i1
        return 5;
      }
      break;
    }
    case AArch64::ASRD_ZPmI_B:
    case AArch64::ASRD_ZPmI_D:
    case AArch64::ASRD_ZPmI_H:
    case AArch64::ASRD_ZPmI_S:
    case AArch64::ASR_ZPmI_B:
    case AArch64::ASR_ZPmI_D:
    case AArch64::ASR_ZPmI_H:
    case AArch64::ASR_ZPmI_S:
    case AArch64::LSL_ZPmI_B:
    case AArch64::LSL_ZPmI_D:
    case AArch64::LSL_ZPmI_H:
    case AArch64::LSL_ZPmI_S:
    case AArch64::LSR_ZPmI_B:
    case AArch64::LSR_ZPmI_D:
    case AArch64::LSR_ZPmI_H:
    case AArch64::LSR_ZPmI_S:
    case AArch64::SQSHLU_ZPmI_B:
    case AArch64::SQSHLU_ZPmI_D:
    case AArch64::SQSHLU_ZPmI_H:
    case AArch64::SQSHLU_ZPmI_S:
    case AArch64::SQSHL_ZPmI_B:
    case AArch64::SQSHL_ZPmI_D:
    case AArch64::SQSHL_ZPmI_H:
    case AArch64::SQSHL_ZPmI_S:
    case AArch64::SRSHR_ZPmI_B:
    case AArch64::SRSHR_ZPmI_D:
    case AArch64::SRSHR_ZPmI_H:
    case AArch64::SRSHR_ZPmI_S:
    case AArch64::UQSHL_ZPmI_B:
    case AArch64::UQSHL_ZPmI_D:
    case AArch64::UQSHL_ZPmI_H:
    case AArch64::UQSHL_ZPmI_S:
    case AArch64::URSHR_ZPmI_B:
    case AArch64::URSHR_ZPmI_D:
    case AArch64::URSHR_ZPmI_H:
    case AArch64::URSHR_ZPmI_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Zdn
        return 0;
      case 3:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MAD_ZPmZZ_B:
    case AArch64::MAD_ZPmZZ_D:
    case AArch64::MAD_ZPmZZ_H:
    case AArch64::MAD_ZPmZZ_S:
    case AArch64::MSB_ZPmZZ_B:
    case AArch64::MSB_ZPmZZ_D:
    case AArch64::MSB_ZPmZZ_H:
    case AArch64::MSB_ZPmZZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: Zdn
        return 0;
      case 4:
        // op: Za
        return 5;
      case 3:
        // op: Zm
        return 16;
      }
      break;
    }
    case AArch64::CNTP_XPP_B:
    case AArch64::CNTP_XPP_D:
    case AArch64::CNTP_XPP_H:
    case AArch64::CNTP_XPP_S:
    case AArch64::FIRSTP_XPP_B:
    case AArch64::FIRSTP_XPP_D:
    case AArch64::FIRSTP_XPP_H:
    case AArch64::FIRSTP_XPP_S:
    case AArch64::LASTP_XPP_B:
    case AArch64::LASTP_XPP_D:
    case AArch64::LASTP_XPP_H:
    case AArch64::LASTP_XPP_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Pn
        return 5;
      case 0:
        // op: Rd
        return 0;
      }
      break;
    }
    case AArch64::LD1B_D_IMM:
    case AArch64::LD1B_H_IMM:
    case AArch64::LD1B_IMM:
    case AArch64::LD1B_S_IMM:
    case AArch64::LD1D_IMM:
    case AArch64::LD1H_D_IMM:
    case AArch64::LD1H_IMM:
    case AArch64::LD1H_S_IMM:
    case AArch64::LD1SB_D_IMM:
    case AArch64::LD1SB_H_IMM:
    case AArch64::LD1SB_S_IMM:
    case AArch64::LD1SH_D_IMM:
    case AArch64::LD1SH_S_IMM:
    case AArch64::LD1SW_D_IMM:
    case AArch64::LD1W_D_IMM:
    case AArch64::LD1W_IMM:
    case AArch64::LDNF1B_D_IMM:
    case AArch64::LDNF1B_H_IMM:
    case AArch64::LDNF1B_IMM:
    case AArch64::LDNF1B_S_IMM:
    case AArch64::LDNF1D_IMM:
    case AArch64::LDNF1H_D_IMM:
    case AArch64::LDNF1H_IMM:
    case AArch64::LDNF1H_S_IMM:
    case AArch64::LDNF1SB_D_IMM:
    case AArch64::LDNF1SB_H_IMM:
    case AArch64::LDNF1SB_S_IMM:
    case AArch64::LDNF1SH_D_IMM:
    case AArch64::LDNF1SH_S_IMM:
    case AArch64::LDNF1SW_D_IMM:
    case AArch64::LDNF1W_D_IMM:
    case AArch64::LDNF1W_IMM:
    case AArch64::ST1B_D_IMM:
    case AArch64::ST1B_H_IMM:
    case AArch64::ST1B_IMM:
    case AArch64::ST1B_S_IMM:
    case AArch64::ST1D_IMM:
    case AArch64::ST1D_Q_IMM:
    case AArch64::ST1H_D_IMM:
    case AArch64::ST1H_IMM:
    case AArch64::ST1H_S_IMM:
    case AArch64::ST1W_D_IMM:
    case AArch64::ST1W_IMM:
    case AArch64::ST1W_Q_IMM:
    case AArch64::ST2B_IMM:
    case AArch64::ST2D_IMM:
    case AArch64::ST2H_IMM:
    case AArch64::ST2W_IMM:
    case AArch64::ST3B_IMM:
    case AArch64::ST3D_IMM:
    case AArch64::ST3H_IMM:
    case AArch64::ST3W_IMM:
    case AArch64::ST4B_IMM:
    case AArch64::ST4D_IMM:
    case AArch64::ST4H_IMM:
    case AArch64::ST4W_IMM:
    case AArch64::STNT1B_ZRI:
    case AArch64::STNT1D_ZRI:
    case AArch64::STNT1H_ZRI:
    case AArch64::STNT1W_ZRI: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Rn
        return 5;
      case 0:
        // op: Zt
        return 0;
      case 3:
        // op: imm4
        return 16;
      }
      break;
    }
    case AArch64::LD1RB_D_IMM:
    case AArch64::LD1RB_H_IMM:
    case AArch64::LD1RB_IMM:
    case AArch64::LD1RB_S_IMM:
    case AArch64::LD1RD_IMM:
    case AArch64::LD1RH_D_IMM:
    case AArch64::LD1RH_IMM:
    case AArch64::LD1RH_S_IMM:
    case AArch64::LD1RSB_D_IMM:
    case AArch64::LD1RSB_H_IMM:
    case AArch64::LD1RSB_S_IMM:
    case AArch64::LD1RSH_D_IMM:
    case AArch64::LD1RSH_S_IMM:
    case AArch64::LD1RSW_IMM:
    case AArch64::LD1RW_D_IMM:
    case AArch64::LD1RW_IMM: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Rn
        return 5;
      case 0:
        // op: Zt
        return 0;
      case 3:
        // op: imm6
        return 16;
      }
      break;
    }
    case AArch64::GLD1B_D:
    case AArch64::GLD1B_D_SXTW:
    case AArch64::GLD1B_D_UXTW:
    case AArch64::GLD1B_S_SXTW:
    case AArch64::GLD1B_S_UXTW:
    case AArch64::GLD1D:
    case AArch64::GLD1D_SCALED:
    case AArch64::GLD1D_SXTW:
    case AArch64::GLD1D_SXTW_SCALED:
    case AArch64::GLD1D_UXTW:
    case AArch64::GLD1D_UXTW_SCALED:
    case AArch64::GLD1H_D:
    case AArch64::GLD1H_D_SCALED:
    case AArch64::GLD1H_D_SXTW:
    case AArch64::GLD1H_D_SXTW_SCALED:
    case AArch64::GLD1H_D_UXTW:
    case AArch64::GLD1H_D_UXTW_SCALED:
    case AArch64::GLD1H_S_SXTW:
    case AArch64::GLD1H_S_SXTW_SCALED:
    case AArch64::GLD1H_S_UXTW:
    case AArch64::GLD1H_S_UXTW_SCALED:
    case AArch64::GLD1SB_D:
    case AArch64::GLD1SB_D_SXTW:
    case AArch64::GLD1SB_D_UXTW:
    case AArch64::GLD1SB_S_SXTW:
    case AArch64::GLD1SB_S_UXTW:
    case AArch64::GLD1SH_D:
    case AArch64::GLD1SH_D_SCALED:
    case AArch64::GLD1SH_D_SXTW:
    case AArch64::GLD1SH_D_SXTW_SCALED:
    case AArch64::GLD1SH_D_UXTW:
    case AArch64::GLD1SH_D_UXTW_SCALED:
    case AArch64::GLD1SH_S_SXTW:
    case AArch64::GLD1SH_S_SXTW_SCALED:
    case AArch64::GLD1SH_S_UXTW:
    case AArch64::GLD1SH_S_UXTW_SCALED:
    case AArch64::GLD1SW_D:
    case AArch64::GLD1SW_D_SCALED:
    case AArch64::GLD1SW_D_SXTW:
    case AArch64::GLD1SW_D_SXTW_SCALED:
    case AArch64::GLD1SW_D_UXTW:
    case AArch64::GLD1SW_D_UXTW_SCALED:
    case AArch64::GLD1W_D:
    case AArch64::GLD1W_D_SCALED:
    case AArch64::GLD1W_D_SXTW:
    case AArch64::GLD1W_D_SXTW_SCALED:
    case AArch64::GLD1W_D_UXTW:
    case AArch64::GLD1W_D_UXTW_SCALED:
    case AArch64::GLD1W_SXTW:
    case AArch64::GLD1W_SXTW_SCALED:
    case AArch64::GLD1W_UXTW:
    case AArch64::GLD1W_UXTW_SCALED:
    case AArch64::GLDFF1B_D:
    case AArch64::GLDFF1B_D_SXTW:
    case AArch64::GLDFF1B_D_UXTW:
    case AArch64::GLDFF1B_S_SXTW:
    case AArch64::GLDFF1B_S_UXTW:
    case AArch64::GLDFF1D:
    case AArch64::GLDFF1D_SCALED:
    case AArch64::GLDFF1D_SXTW:
    case AArch64::GLDFF1D_SXTW_SCALED:
    case AArch64::GLDFF1D_UXTW:
    case AArch64::GLDFF1D_UXTW_SCALED:
    case AArch64::GLDFF1H_D:
    case AArch64::GLDFF1H_D_SCALED:
    case AArch64::GLDFF1H_D_SXTW:
    case AArch64::GLDFF1H_D_SXTW_SCALED:
    case AArch64::GLDFF1H_D_UXTW:
    case AArch64::GLDFF1H_D_UXTW_SCALED:
    case AArch64::GLDFF1H_S_SXTW:
    case AArch64::GLDFF1H_S_SXTW_SCALED:
    case AArch64::GLDFF1H_S_UXTW:
    case AArch64::GLDFF1H_S_UXTW_SCALED:
    case AArch64::GLDFF1SB_D:
    case AArch64::GLDFF1SB_D_SXTW:
    case AArch64::GLDFF1SB_D_UXTW:
    case AArch64::GLDFF1SB_S_SXTW:
    case AArch64::GLDFF1SB_S_UXTW:
    case AArch64::GLDFF1SH_D:
    case AArch64::GLDFF1SH_D_SCALED:
    case AArch64::GLDFF1SH_D_SXTW:
    case AArch64::GLDFF1SH_D_SXTW_SCALED:
    case AArch64::GLDFF1SH_D_UXTW:
    case AArch64::GLDFF1SH_D_UXTW_SCALED:
    case AArch64::GLDFF1SH_S_SXTW:
    case AArch64::GLDFF1SH_S_SXTW_SCALED:
    case AArch64::GLDFF1SH_S_UXTW:
    case AArch64::GLDFF1SH_S_UXTW_SCALED:
    case AArch64::GLDFF1SW_D:
    case AArch64::GLDFF1SW_D_SCALED:
    case AArch64::GLDFF1SW_D_SXTW:
    case AArch64::GLDFF1SW_D_SXTW_SCALED:
    case AArch64::GLDFF1SW_D_UXTW:
    case AArch64::GLDFF1SW_D_UXTW_SCALED:
    case AArch64::GLDFF1W_D:
    case AArch64::GLDFF1W_D_SCALED:
    case AArch64::GLDFF1W_D_SXTW:
    case AArch64::GLDFF1W_D_SXTW_SCALED:
    case AArch64::GLDFF1W_D_UXTW:
    case AArch64::GLDFF1W_D_UXTW_SCALED:
    case AArch64::GLDFF1W_SXTW:
    case AArch64::GLDFF1W_SXTW_SCALED:
    case AArch64::GLDFF1W_UXTW:
    case AArch64::GLDFF1W_UXTW_SCALED:
    case AArch64::SST1B_D:
    case AArch64::SST1B_D_SXTW:
    case AArch64::SST1B_D_UXTW:
    case AArch64::SST1B_S_SXTW:
    case AArch64::SST1B_S_UXTW:
    case AArch64::SST1D:
    case AArch64::SST1D_SCALED:
    case AArch64::SST1D_SXTW:
    case AArch64::SST1D_SXTW_SCALED:
    case AArch64::SST1D_UXTW:
    case AArch64::SST1D_UXTW_SCALED:
    case AArch64::SST1H_D:
    case AArch64::SST1H_D_SCALED:
    case AArch64::SST1H_D_SXTW:
    case AArch64::SST1H_D_SXTW_SCALED:
    case AArch64::SST1H_D_UXTW:
    case AArch64::SST1H_D_UXTW_SCALED:
    case AArch64::SST1H_S_SXTW:
    case AArch64::SST1H_S_SXTW_SCALED:
    case AArch64::SST1H_S_UXTW:
    case AArch64::SST1H_S_UXTW_SCALED:
    case AArch64::SST1W_D:
    case AArch64::SST1W_D_SCALED:
    case AArch64::SST1W_D_SXTW:
    case AArch64::SST1W_D_SXTW_SCALED:
    case AArch64::SST1W_D_UXTW:
    case AArch64::SST1W_D_UXTW_SCALED:
    case AArch64::SST1W_SXTW:
    case AArch64::SST1W_SXTW_SCALED:
    case AArch64::SST1W_UXTW:
    case AArch64::SST1W_UXTW_SCALED: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: Zm
        return 16;
      case 0:
        // op: Zt
        return 0;
      }
      break;
    }
    case AArch64::PRFB_D_SCALED:
    case AArch64::PRFB_D_SXTW_SCALED:
    case AArch64::PRFB_D_UXTW_SCALED:
    case AArch64::PRFB_S_SXTW_SCALED:
    case AArch64::PRFB_S_UXTW_SCALED:
    case AArch64::PRFD_D_SCALED:
    case AArch64::PRFD_D_SXTW_SCALED:
    case AArch64::PRFD_D_UXTW_SCALED:
    case AArch64::PRFD_S_SXTW_SCALED:
    case AArch64::PRFD_S_UXTW_SCALED:
    case AArch64::PRFH_D_SCALED:
    case AArch64::PRFH_D_SXTW_SCALED:
    case AArch64::PRFH_D_UXTW_SCALED:
    case AArch64::PRFH_S_SXTW_SCALED:
    case AArch64::PRFH_S_UXTW_SCALED:
    case AArch64::PRFW_D_SCALED:
    case AArch64::PRFW_D_SXTW_SCALED:
    case AArch64::PRFW_D_UXTW_SCALED:
    case AArch64::PRFW_S_SXTW_SCALED:
    case AArch64::PRFW_S_UXTW_SCALED: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: Zm
        return 16;
      case 0:
        // op: prfop
        return 0;
      }
      break;
    }
    case AArch64::EXPAND_ZPZ_B:
    case AArch64::EXPAND_ZPZ_D:
    case AArch64::EXPAND_ZPZ_H:
    case AArch64::EXPAND_ZPZ_S:
    case AArch64::SPLICE_ZPZZ_B:
    case AArch64::SPLICE_ZPZZ_D:
    case AArch64::SPLICE_ZPZZ_H:
    case AArch64::SPLICE_ZPZZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 0;
      }
      break;
    }
    case AArch64::GLD1B_D_IMM:
    case AArch64::GLD1B_S_IMM:
    case AArch64::GLD1D_IMM:
    case AArch64::GLD1H_D_IMM:
    case AArch64::GLD1H_S_IMM:
    case AArch64::GLD1SB_D_IMM:
    case AArch64::GLD1SB_S_IMM:
    case AArch64::GLD1SH_D_IMM:
    case AArch64::GLD1SH_S_IMM:
    case AArch64::GLD1SW_D_IMM:
    case AArch64::GLD1W_D_IMM:
    case AArch64::GLD1W_IMM:
    case AArch64::GLDFF1B_D_IMM:
    case AArch64::GLDFF1B_S_IMM:
    case AArch64::GLDFF1D_IMM:
    case AArch64::GLDFF1H_D_IMM:
    case AArch64::GLDFF1H_S_IMM:
    case AArch64::GLDFF1SB_D_IMM:
    case AArch64::GLDFF1SB_S_IMM:
    case AArch64::GLDFF1SH_D_IMM:
    case AArch64::GLDFF1SH_S_IMM:
    case AArch64::GLDFF1SW_D_IMM:
    case AArch64::GLDFF1W_D_IMM:
    case AArch64::GLDFF1W_IMM: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zt
        return 0;
      case 3:
        // op: imm5
        return 16;
      }
      break;
    }
    case AArch64::PRFB_D_PZI:
    case AArch64::PRFB_S_PZI:
    case AArch64::PRFD_D_PZI:
    case AArch64::PRFD_S_PZI:
    case AArch64::PRFH_D_PZI:
    case AArch64::PRFH_S_PZI:
    case AArch64::PRFW_D_PZI:
    case AArch64::PRFW_S_PZI: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 2:
        // op: Zn
        return 5;
      case 3:
        // op: imm5
        return 16;
      case 0:
        // op: prfop
        return 0;
      }
      break;
    }
    case AArch64::LD2B:
    case AArch64::LD2D:
    case AArch64::LD2H:
    case AArch64::LD2Q:
    case AArch64::LD2W:
    case AArch64::LD3B:
    case AArch64::LD3D:
    case AArch64::LD3H:
    case AArch64::LD3Q:
    case AArch64::LD3W:
    case AArch64::LD4B:
    case AArch64::LD4D:
    case AArch64::LD4H:
    case AArch64::LD4Q:
    case AArch64::LD4W:
    case AArch64::LDNT1B_ZRR:
    case AArch64::LDNT1D_ZRR:
    case AArch64::LDNT1H_ZRR:
    case AArch64::LDNT1W_ZRR:
    case AArch64::ST1B:
    case AArch64::ST1B_D:
    case AArch64::ST1B_H:
    case AArch64::ST1B_S:
    case AArch64::ST1D:
    case AArch64::ST1D_Q:
    case AArch64::ST1H:
    case AArch64::ST1H_D:
    case AArch64::ST1H_S:
    case AArch64::ST1W:
    case AArch64::ST1W_D:
    case AArch64::ST1W_Q:
    case AArch64::ST2B:
    case AArch64::ST2D:
    case AArch64::ST2H:
    case AArch64::ST2W:
    case AArch64::ST3B:
    case AArch64::ST3D:
    case AArch64::ST3H:
    case AArch64::ST3W:
    case AArch64::ST4B:
    case AArch64::ST4D:
    case AArch64::ST4H:
    case AArch64::ST4W:
    case AArch64::STNT1B_ZRR:
    case AArch64::STNT1D_ZRR:
    case AArch64::STNT1H_ZRR:
    case AArch64::STNT1W_ZRR: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Rm
        return 16;
      case 2:
        // op: Rn
        return 5;
      case 0:
        // op: Zt
        return 0;
      }
      break;
    }
    case AArch64::LDNT1B_ZZR_D:
    case AArch64::LDNT1B_ZZR_S:
    case AArch64::LDNT1D_ZZR_D:
    case AArch64::LDNT1H_ZZR_D:
    case AArch64::LDNT1H_ZZR_S:
    case AArch64::LDNT1SB_ZZR_D:
    case AArch64::LDNT1SB_ZZR_S:
    case AArch64::LDNT1SH_ZZR_D:
    case AArch64::LDNT1SH_ZZR_S:
    case AArch64::LDNT1SW_ZZR_D:
    case AArch64::LDNT1W_ZZR_D:
    case AArch64::LDNT1W_ZZR_S:
    case AArch64::STNT1B_ZZR_D:
    case AArch64::STNT1B_ZZR_S:
    case AArch64::STNT1D_ZZR_D:
    case AArch64::STNT1H_ZZR_D:
    case AArch64::STNT1H_ZZR_S:
    case AArch64::STNT1W_ZZR_D:
    case AArch64::STNT1W_ZZR_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Rm
        return 16;
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zt
        return 0;
      }
      break;
    }
    case AArch64::ADDP_ZPmZ_B:
    case AArch64::ADDP_ZPmZ_D:
    case AArch64::ADDP_ZPmZ_H:
    case AArch64::ADDP_ZPmZ_S:
    case AArch64::FADDP_ZPmZZ_D:
    case AArch64::FADDP_ZPmZZ_H:
    case AArch64::FADDP_ZPmZZ_S:
    case AArch64::FMAXNMP_ZPmZZ_D:
    case AArch64::FMAXNMP_ZPmZZ_H:
    case AArch64::FMAXNMP_ZPmZZ_S:
    case AArch64::FMAXP_ZPmZZ_D:
    case AArch64::FMAXP_ZPmZZ_H:
    case AArch64::FMAXP_ZPmZZ_S:
    case AArch64::FMINNMP_ZPmZZ_D:
    case AArch64::FMINNMP_ZPmZZ_H:
    case AArch64::FMINNMP_ZPmZZ_S:
    case AArch64::FMINP_ZPmZZ_D:
    case AArch64::FMINP_ZPmZZ_H:
    case AArch64::FMINP_ZPmZZ_S:
    case AArch64::SHADD_ZPmZ_B:
    case AArch64::SHADD_ZPmZ_D:
    case AArch64::SHADD_ZPmZ_H:
    case AArch64::SHADD_ZPmZ_S:
    case AArch64::SHSUBR_ZPmZ_B:
    case AArch64::SHSUBR_ZPmZ_D:
    case AArch64::SHSUBR_ZPmZ_H:
    case AArch64::SHSUBR_ZPmZ_S:
    case AArch64::SHSUB_ZPmZ_B:
    case AArch64::SHSUB_ZPmZ_D:
    case AArch64::SHSUB_ZPmZ_H:
    case AArch64::SHSUB_ZPmZ_S:
    case AArch64::SMAXP_ZPmZ_B:
    case AArch64::SMAXP_ZPmZ_D:
    case AArch64::SMAXP_ZPmZ_H:
    case AArch64::SMAXP_ZPmZ_S:
    case AArch64::SMINP_ZPmZ_B:
    case AArch64::SMINP_ZPmZ_D:
    case AArch64::SMINP_ZPmZ_H:
    case AArch64::SMINP_ZPmZ_S:
    case AArch64::SQADD_ZPmZ_B:
    case AArch64::SQADD_ZPmZ_D:
    case AArch64::SQADD_ZPmZ_H:
    case AArch64::SQADD_ZPmZ_S:
    case AArch64::SQRSHLR_ZPmZ_B:
    case AArch64::SQRSHLR_ZPmZ_D:
    case AArch64::SQRSHLR_ZPmZ_H:
    case AArch64::SQRSHLR_ZPmZ_S:
    case AArch64::SQRSHL_ZPmZ_B:
    case AArch64::SQRSHL_ZPmZ_D:
    case AArch64::SQRSHL_ZPmZ_H:
    case AArch64::SQRSHL_ZPmZ_S:
    case AArch64::SQSHLR_ZPmZ_B:
    case AArch64::SQSHLR_ZPmZ_D:
    case AArch64::SQSHLR_ZPmZ_H:
    case AArch64::SQSHLR_ZPmZ_S:
    case AArch64::SQSHL_ZPmZ_B:
    case AArch64::SQSHL_ZPmZ_D:
    case AArch64::SQSHL_ZPmZ_H:
    case AArch64::SQSHL_ZPmZ_S:
    case AArch64::SQSUBR_ZPmZ_B:
    case AArch64::SQSUBR_ZPmZ_D:
    case AArch64::SQSUBR_ZPmZ_H:
    case AArch64::SQSUBR_ZPmZ_S:
    case AArch64::SQSUB_ZPmZ_B:
    case AArch64::SQSUB_ZPmZ_D:
    case AArch64::SQSUB_ZPmZ_H:
    case AArch64::SQSUB_ZPmZ_S:
    case AArch64::SRHADD_ZPmZ_B:
    case AArch64::SRHADD_ZPmZ_D:
    case AArch64::SRHADD_ZPmZ_H:
    case AArch64::SRHADD_ZPmZ_S:
    case AArch64::SRSHLR_ZPmZ_B:
    case AArch64::SRSHLR_ZPmZ_D:
    case AArch64::SRSHLR_ZPmZ_H:
    case AArch64::SRSHLR_ZPmZ_S:
    case AArch64::SRSHL_ZPmZ_B:
    case AArch64::SRSHL_ZPmZ_D:
    case AArch64::SRSHL_ZPmZ_H:
    case AArch64::SRSHL_ZPmZ_S:
    case AArch64::SUBP_ZPmZZ_B:
    case AArch64::SUBP_ZPmZZ_D:
    case AArch64::SUBP_ZPmZZ_H:
    case AArch64::SUBP_ZPmZZ_S:
    case AArch64::SUQADD_ZPmZ_B:
    case AArch64::SUQADD_ZPmZ_D:
    case AArch64::SUQADD_ZPmZ_H:
    case AArch64::SUQADD_ZPmZ_S:
    case AArch64::UHADD_ZPmZ_B:
    case AArch64::UHADD_ZPmZ_D:
    case AArch64::UHADD_ZPmZ_H:
    case AArch64::UHADD_ZPmZ_S:
    case AArch64::UHSUBR_ZPmZ_B:
    case AArch64::UHSUBR_ZPmZ_D:
    case AArch64::UHSUBR_ZPmZ_H:
    case AArch64::UHSUBR_ZPmZ_S:
    case AArch64::UHSUB_ZPmZ_B:
    case AArch64::UHSUB_ZPmZ_D:
    case AArch64::UHSUB_ZPmZ_H:
    case AArch64::UHSUB_ZPmZ_S:
    case AArch64::UMAXP_ZPmZ_B:
    case AArch64::UMAXP_ZPmZ_D:
    case AArch64::UMAXP_ZPmZ_H:
    case AArch64::UMAXP_ZPmZ_S:
    case AArch64::UMINP_ZPmZ_B:
    case AArch64::UMINP_ZPmZ_D:
    case AArch64::UMINP_ZPmZ_H:
    case AArch64::UMINP_ZPmZ_S:
    case AArch64::UQADD_ZPmZ_B:
    case AArch64::UQADD_ZPmZ_D:
    case AArch64::UQADD_ZPmZ_H:
    case AArch64::UQADD_ZPmZ_S:
    case AArch64::UQRSHLR_ZPmZ_B:
    case AArch64::UQRSHLR_ZPmZ_D:
    case AArch64::UQRSHLR_ZPmZ_H:
    case AArch64::UQRSHLR_ZPmZ_S:
    case AArch64::UQRSHL_ZPmZ_B:
    case AArch64::UQRSHL_ZPmZ_D:
    case AArch64::UQRSHL_ZPmZ_H:
    case AArch64::UQRSHL_ZPmZ_S:
    case AArch64::UQSHLR_ZPmZ_B:
    case AArch64::UQSHLR_ZPmZ_D:
    case AArch64::UQSHLR_ZPmZ_H:
    case AArch64::UQSHLR_ZPmZ_S:
    case AArch64::UQSHL_ZPmZ_B:
    case AArch64::UQSHL_ZPmZ_D:
    case AArch64::UQSHL_ZPmZ_H:
    case AArch64::UQSHL_ZPmZ_S:
    case AArch64::UQSUBR_ZPmZ_B:
    case AArch64::UQSUBR_ZPmZ_D:
    case AArch64::UQSUBR_ZPmZ_H:
    case AArch64::UQSUBR_ZPmZ_S:
    case AArch64::UQSUB_ZPmZ_B:
    case AArch64::UQSUB_ZPmZ_D:
    case AArch64::UQSUB_ZPmZ_H:
    case AArch64::UQSUB_ZPmZ_S:
    case AArch64::URHADD_ZPmZ_B:
    case AArch64::URHADD_ZPmZ_D:
    case AArch64::URHADD_ZPmZ_H:
    case AArch64::URHADD_ZPmZ_S:
    case AArch64::URSHLR_ZPmZ_B:
    case AArch64::URSHLR_ZPmZ_D:
    case AArch64::URSHLR_ZPmZ_H:
    case AArch64::URSHLR_ZPmZ_S:
    case AArch64::URSHL_ZPmZ_B:
    case AArch64::URSHL_ZPmZ_D:
    case AArch64::URSHL_ZPmZ_H:
    case AArch64::URSHL_ZPmZ_S:
    case AArch64::USQADD_ZPmZ_B:
    case AArch64::USQADD_ZPmZ_D:
    case AArch64::USQADD_ZPmZ_H:
    case AArch64::USQADD_ZPmZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Zm
        return 5;
      case 0:
        // op: Zdn
        return 0;
      }
      break;
    }
    case AArch64::SADALP_ZPmZ_D:
    case AArch64::SADALP_ZPmZ_H:
    case AArch64::SADALP_ZPmZ_S:
    case AArch64::UADALP_ZPmZ_D:
    case AArch64::UADALP_ZPmZ_H:
    case AArch64::UADALP_ZPmZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: Zn
        return 5;
      case 0:
        // op: Zda
        return 0;
      }
      break;
    }
    case AArch64::SST1B_D_IMM:
    case AArch64::SST1B_S_IMM:
    case AArch64::SST1D_IMM:
    case AArch64::SST1H_D_IMM:
    case AArch64::SST1H_S_IMM:
    case AArch64::SST1W_D_IMM:
    case AArch64::SST1W_IMM: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: imm5
        return 16;
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zt
        return 0;
      }
      break;
    }
    case AArch64::FMAD_ZPmZZ_D:
    case AArch64::FMAD_ZPmZZ_H:
    case AArch64::FMAD_ZPmZZ_S:
    case AArch64::FMSB_ZPmZZ_D:
    case AArch64::FMSB_ZPmZZ_H:
    case AArch64::FMSB_ZPmZZ_S:
    case AArch64::FNMAD_ZPmZZ_D:
    case AArch64::FNMAD_ZPmZZ_H:
    case AArch64::FNMAD_ZPmZZ_S:
    case AArch64::FNMSB_ZPmZZ_D:
    case AArch64::FNMSB_ZPmZZ_H:
    case AArch64::FNMSB_ZPmZZ_S: {
      switch (OpNum) {
      case 1:
        // op: Pg
        return 10;
      case 4:
        // op: Za
        return 16;
      case 0:
        // op: Zdn
        return 0;
      case 3:
        // op: Zm
        return 5;
      }
      break;
    }
    case AArch64::BF16DOTlanev4bf16:
    case AArch64::BF16DOTlanev8bf16:
    case AArch64::BFMLALBIdx:
    case AArch64::BFMLALTIdx:
    case AArch64::FDOTlanev2f32:
    case AArch64::FDOTlanev4f16:
    case AArch64::FDOTlanev4f16_v2f32:
    case AArch64::FDOTlanev4f32:
    case AArch64::FDOTlanev8f16:
    case AArch64::FDOTlanev8f16_v4f32:
    case AArch64::FMLAL2lanev4f16:
    case AArch64::FMLAL2lanev8f16:
    case AArch64::FMLALBlanev8f16:
    case AArch64::FMLALLBBlanev4f32:
    case AArch64::FMLALLBTlanev4f32:
    case AArch64::FMLALLTBlanev4f32:
    case AArch64::FMLALLTTlanev4f32:
    case AArch64::FMLALTlanev8f16:
    case AArch64::FMLALlanev4f16:
    case AArch64::FMLALlanev8f16:
    case AArch64::FMLAv1i16_indexed:
    case AArch64::FMLAv1i32_indexed:
    case AArch64::FMLAv1i64_indexed:
    case AArch64::FMLAv2i32_indexed:
    case AArch64::FMLAv2i64_indexed:
    case AArch64::FMLAv4i16_indexed:
    case AArch64::FMLAv4i32_indexed:
    case AArch64::FMLAv8i16_indexed:
    case AArch64::FMLSL2lanev4f16:
    case AArch64::FMLSL2lanev8f16:
    case AArch64::FMLSLlanev4f16:
    case AArch64::FMLSLlanev8f16:
    case AArch64::FMLSv1i16_indexed:
    case AArch64::FMLSv1i32_indexed:
    case AArch64::FMLSv1i64_indexed:
    case AArch64::FMLSv2i32_indexed:
    case AArch64::FMLSv2i64_indexed:
    case AArch64::FMLSv4i16_indexed:
    case AArch64::FMLSv4i32_indexed:
    case AArch64::FMLSv8i16_indexed:
    case AArch64::MLAv2i32_indexed:
    case AArch64::MLAv4i16_indexed:
    case AArch64::MLAv4i32_indexed:
    case AArch64::MLAv8i16_indexed:
    case AArch64::MLSv2i32_indexed:
    case AArch64::MLSv4i16_indexed:
    case AArch64::MLSv4i32_indexed:
    case AArch64::MLSv8i16_indexed:
    case AArch64::SDOTlanev16i8:
    case AArch64::SDOTlanev8i8:
    case AArch64::SMLALv2i32_indexed:
    case AArch64::SMLALv4i16_indexed:
    case AArch64::SMLALv4i32_indexed:
    case AArch64::SMLALv8i16_indexed:
    case AArch64::SMLSLv2i32_indexed:
    case AArch64::SMLSLv4i16_indexed:
    case AArch64::SMLSLv4i32_indexed:
    case AArch64::SMLSLv8i16_indexed:
    case AArch64::SQDMLALv1i32_indexed:
    case AArch64::SQDMLALv1i64_indexed:
    case AArch64::SQDMLALv2i32_indexed:
    case AArch64::SQDMLALv4i16_indexed:
    case AArch64::SQDMLALv4i32_indexed:
    case AArch64::SQDMLALv8i16_indexed:
    case AArch64::SQDMLSLv1i32_indexed:
    case AArch64::SQDMLSLv1i64_indexed:
    case AArch64::SQDMLSLv2i32_indexed:
    case AArch64::SQDMLSLv4i16_indexed:
    case AArch64::SQDMLSLv4i32_indexed:
    case AArch64::SQDMLSLv8i16_indexed:
    case AArch64::SQRDMLAHv1i16_indexed:
    case AArch64::SQRDMLAHv1i32_indexed:
    case AArch64::SQRDMLAHv2i32_indexed:
    case AArch64::SQRDMLAHv4i16_indexed:
    case AArch64::SQRDMLAHv4i32_indexed:
    case AArch64::SQRDMLAHv8i16_indexed:
    case AArch64::SQRDMLSHv1i16_indexed:
    case AArch64::SQRDMLSHv1i32_indexed:
    case AArch64::SQRDMLSHv2i32_indexed:
    case AArch64::SQRDMLSHv4i16_indexed:
    case AArch64::SQRDMLSHv4i32_indexed:
    case AArch64::SQRDMLSHv8i16_indexed:
    case AArch64::SUDOTlanev16i8:
    case AArch64::SUDOTlanev8i8:
    case AArch64::UDOTlanev16i8:
    case AArch64::UDOTlanev8i8:
    case AArch64::UMLALv2i32_indexed:
    case AArch64::UMLALv4i16_indexed:
    case AArch64::UMLALv4i32_indexed:
    case AArch64::UMLALv8i16_indexed:
    case AArch64::UMLSLv2i32_indexed:
    case AArch64::UMLSLv4i16_indexed:
    case AArch64::UMLSLv4i32_indexed:
    case AArch64::UMLSLv8i16_indexed:
    case AArch64::USDOTlanev16i8:
    case AArch64::USDOTlanev8i8: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: Rm
        return 16;
      case 4:
        // op: idx
        return 11;
      }
      break;
    }
    case AArch64::FCMLAv2f32:
    case AArch64::FCMLAv2f64:
    case AArch64::FCMLAv4f16:
    case AArch64::FCMLAv4f32:
    case AArch64::FCMLAv8f16: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: Rm
        return 16;
      case 4:
        // op: rot
        return 11;
      }
      break;
    }
    case AArch64::FCMLAv4f32_indexed:
    case AArch64::FCMLAv8f16_indexed: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: Rm
        return 16;
      case 5:
        // op: rot
        return 13;
      case 4:
        // op: idx
        return 11;
      }
      break;
    }
    case AArch64::FCMLAv4f16_indexed: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: Rm
        return 16;
      case 5:
        // op: rot
        return 13;
      case 4:
        // op: idx
        return 21;
      }
      break;
    }
    case AArch64::ADDHNv2i64_v4i32:
    case AArch64::ADDHNv4i32_v8i16:
    case AArch64::ADDHNv8i16_v16i8:
    case AArch64::BFDOTv4bf16:
    case AArch64::BFDOTv8bf16:
    case AArch64::BFMLALB:
    case AArch64::BFMLALT:
    case AArch64::BFMMLA:
    case AArch64::BIFv16i8:
    case AArch64::BIFv8i8:
    case AArch64::BITv16i8:
    case AArch64::BITv8i8:
    case AArch64::BSLv16i8:
    case AArch64::BSLv8i8:
    case AArch64::FCVTN_F322v16f8:
    case AArch64::FDOTv2f32:
    case AArch64::FDOTv4f16:
    case AArch64::FDOTv4f16_v2f32:
    case AArch64::FDOTv4f32:
    case AArch64::FDOTv8f16:
    case AArch64::FDOTv8f16_v4f32:
    case AArch64::FMLAL2v4f16:
    case AArch64::FMLAL2v8f16:
    case AArch64::FMLALBv16i8_v8f16:
    case AArch64::FMLALLBBv4f32:
    case AArch64::FMLALLBTv4f32:
    case AArch64::FMLALLTBv4f32:
    case AArch64::FMLALLTTv4f32:
    case AArch64::FMLALTv16i8_v8f16:
    case AArch64::FMLALv4f16:
    case AArch64::FMLALv8f16:
    case AArch64::FMLAv2f32:
    case AArch64::FMLAv2f64:
    case AArch64::FMLAv4f16:
    case AArch64::FMLAv4f32:
    case AArch64::FMLAv8f16:
    case AArch64::FMLSL2v4f16:
    case AArch64::FMLSL2v8f16:
    case AArch64::FMLSLv4f16:
    case AArch64::FMLSLv8f16:
    case AArch64::FMLSv2f32:
    case AArch64::FMLSv2f64:
    case AArch64::FMLSv4f16:
    case AArch64::FMLSv4f32:
    case AArch64::FMLSv8f16:
    case AArch64::FMMLAv4f32:
    case AArch64::FMMLAv8f16:
    case AArch64::FMMLAv8f16_v4f32:
    case AArch64::FMMLAv8f16_v8f16:
    case AArch64::MLAv16i8:
    case AArch64::MLAv2i32:
    case AArch64::MLAv4i16:
    case AArch64::MLAv4i32:
    case AArch64::MLAv8i16:
    case AArch64::MLAv8i8:
    case AArch64::MLSv16i8:
    case AArch64::MLSv2i32:
    case AArch64::MLSv4i16:
    case AArch64::MLSv4i32:
    case AArch64::MLSv8i16:
    case AArch64::MLSv8i8:
    case AArch64::RADDHNv2i64_v4i32:
    case AArch64::RADDHNv4i32_v8i16:
    case AArch64::RADDHNv8i16_v16i8:
    case AArch64::RSUBHNv2i64_v4i32:
    case AArch64::RSUBHNv4i32_v8i16:
    case AArch64::RSUBHNv8i16_v16i8:
    case AArch64::SABALv16i8_v8i16:
    case AArch64::SABALv2i32_v2i64:
    case AArch64::SABALv4i16_v4i32:
    case AArch64::SABALv4i32_v2i64:
    case AArch64::SABALv8i16_v4i32:
    case AArch64::SABALv8i8_v8i16:
    case AArch64::SABAv16i8:
    case AArch64::SABAv2i32:
    case AArch64::SABAv4i16:
    case AArch64::SABAv4i32:
    case AArch64::SABAv8i16:
    case AArch64::SABAv8i8:
    case AArch64::SDOTv16i8:
    case AArch64::SDOTv8i8:
    case AArch64::SHA1Crrr:
    case AArch64::SHA1Mrrr:
    case AArch64::SHA1Prrr:
    case AArch64::SHA1SU0rrr:
    case AArch64::SHA256H2rrr:
    case AArch64::SHA256Hrrr:
    case AArch64::SHA256SU1rrr:
    case AArch64::SMLALv16i8_v8i16:
    case AArch64::SMLALv2i32_v2i64:
    case AArch64::SMLALv4i16_v4i32:
    case AArch64::SMLALv4i32_v2i64:
    case AArch64::SMLALv8i16_v4i32:
    case AArch64::SMLALv8i8_v8i16:
    case AArch64::SMLSLv16i8_v8i16:
    case AArch64::SMLSLv2i32_v2i64:
    case AArch64::SMLSLv4i16_v4i32:
    case AArch64::SMLSLv4i32_v2i64:
    case AArch64::SMLSLv8i16_v4i32:
    case AArch64::SMLSLv8i8_v8i16:
    case AArch64::SMMLA:
    case AArch64::SQDMLALi16:
    case AArch64::SQDMLALi32:
    case AArch64::SQDMLALv2i32_v2i64:
    case AArch64::SQDMLALv4i16_v4i32:
    case AArch64::SQDMLALv4i32_v2i64:
    case AArch64::SQDMLALv8i16_v4i32:
    case AArch64::SQDMLSLi16:
    case AArch64::SQDMLSLi32:
    case AArch64::SQDMLSLv2i32_v2i64:
    case AArch64::SQDMLSLv4i16_v4i32:
    case AArch64::SQDMLSLv4i32_v2i64:
    case AArch64::SQDMLSLv8i16_v4i32:
    case AArch64::SQRDMLAHv1i16:
    case AArch64::SQRDMLAHv1i32:
    case AArch64::SQRDMLAHv2i32:
    case AArch64::SQRDMLAHv4i16:
    case AArch64::SQRDMLAHv4i32:
    case AArch64::SQRDMLAHv8i16:
    case AArch64::SQRDMLSHv1i16:
    case AArch64::SQRDMLSHv1i32:
    case AArch64::SQRDMLSHv2i32:
    case AArch64::SQRDMLSHv4i16:
    case AArch64::SQRDMLSHv4i32:
    case AArch64::SQRDMLSHv8i16:
    case AArch64::SUBHNv2i64_v4i32:
    case AArch64::SUBHNv4i32_v8i16:
    case AArch64::SUBHNv8i16_v16i8:
    case AArch64::UABALv16i8_v8i16:
    case AArch64::UABALv2i32_v2i64:
    case AArch64::UABALv4i16_v4i32:
    case AArch64::UABALv4i32_v2i64:
    case AArch64::UABALv8i16_v4i32:
    case AArch64::UABALv8i8_v8i16:
    case AArch64::UABAv16i8:
    case AArch64::UABAv2i32:
    case AArch64::UABAv4i16:
    case AArch64::UABAv4i32:
    case AArch64::UABAv8i16:
    case AArch64::UABAv8i8:
    case AArch64::UDOTv16i8:
    case AArch64::UDOTv8i8:
    case AArch64::UMLALv16i8_v8i16:
    case AArch64::UMLALv2i32_v2i64:
    case AArch64::UMLALv4i16_v4i32:
    case AArch64::UMLALv4i32_v2i64:
    case AArch64::UMLALv8i16_v4i32:
    case AArch64::UMLALv8i8_v8i16:
    case AArch64::UMLSLv16i8_v8i16:
    case AArch64::UMLSLv2i32_v2i64:
    case AArch64::UMLSLv4i16_v4i32:
    case AArch64::UMLSLv4i32_v2i64:
    case AArch64::UMLSLv8i16_v4i32:
    case AArch64::UMLSLv8i8_v8i16:
    case AArch64::UMMLA:
    case AArch64::USDOTv16i8:
    case AArch64::USDOTv8i8:
    case AArch64::USMMLA: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: Rm
        return 16;
      }
      break;
    }
    case AArch64::RSHRNv16i8_shift:
    case AArch64::RSHRNv4i32_shift:
    case AArch64::RSHRNv8i16_shift:
    case AArch64::SHRNv16i8_shift:
    case AArch64::SHRNv4i32_shift:
    case AArch64::SHRNv8i16_shift:
    case AArch64::SLId:
    case AArch64::SLIv16i8_shift:
    case AArch64::SLIv2i32_shift:
    case AArch64::SLIv2i64_shift:
    case AArch64::SLIv4i16_shift:
    case AArch64::SLIv4i32_shift:
    case AArch64::SLIv8i16_shift:
    case AArch64::SLIv8i8_shift:
    case AArch64::SQRSHRNv16i8_shift:
    case AArch64::SQRSHRNv4i32_shift:
    case AArch64::SQRSHRNv8i16_shift:
    case AArch64::SQRSHRUNv16i8_shift:
    case AArch64::SQRSHRUNv4i32_shift:
    case AArch64::SQRSHRUNv8i16_shift:
    case AArch64::SQSHRNv16i8_shift:
    case AArch64::SQSHRNv4i32_shift:
    case AArch64::SQSHRNv8i16_shift:
    case AArch64::SQSHRUNv16i8_shift:
    case AArch64::SQSHRUNv4i32_shift:
    case AArch64::SQSHRUNv8i16_shift:
    case AArch64::SRId:
    case AArch64::SRIv16i8_shift:
    case AArch64::SRIv2i32_shift:
    case AArch64::SRIv2i64_shift:
    case AArch64::SRIv4i16_shift:
    case AArch64::SRIv4i32_shift:
    case AArch64::SRIv8i16_shift:
    case AArch64::SRIv8i8_shift:
    case AArch64::SRSRAd:
    case AArch64::SRSRAv16i8_shift:
    case AArch64::SRSRAv2i32_shift:
    case AArch64::SRSRAv2i64_shift:
    case AArch64::SRSRAv4i16_shift:
    case AArch64::SRSRAv4i32_shift:
    case AArch64::SRSRAv8i16_shift:
    case AArch64::SRSRAv8i8_shift:
    case AArch64::SSRAd:
    case AArch64::SSRAv16i8_shift:
    case AArch64::SSRAv2i32_shift:
    case AArch64::SSRAv2i64_shift:
    case AArch64::SSRAv4i16_shift:
    case AArch64::SSRAv4i32_shift:
    case AArch64::SSRAv8i16_shift:
    case AArch64::SSRAv8i8_shift:
    case AArch64::UQRSHRNv16i8_shift:
    case AArch64::UQRSHRNv4i32_shift:
    case AArch64::UQRSHRNv8i16_shift:
    case AArch64::UQSHRNv16i8_shift:
    case AArch64::UQSHRNv4i32_shift:
    case AArch64::UQSHRNv8i16_shift:
    case AArch64::URSRAd:
    case AArch64::URSRAv16i8_shift:
    case AArch64::URSRAv2i32_shift:
    case AArch64::URSRAv2i64_shift:
    case AArch64::URSRAv4i16_shift:
    case AArch64::URSRAv4i32_shift:
    case AArch64::URSRAv8i16_shift:
    case AArch64::URSRAv8i8_shift:
    case AArch64::USRAd:
    case AArch64::USRAv16i8_shift:
    case AArch64::USRAv2i32_shift:
    case AArch64::USRAv2i64_shift:
    case AArch64::USRAv4i16_shift:
    case AArch64::USRAv4i32_shift:
    case AArch64::USRAv8i16_shift:
    case AArch64::USRAv8i8_shift: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: imm
        return 16;
      }
      break;
    }
    case AArch64::AESDrr:
    case AArch64::AESErr:
    case AArch64::AUTDA:
    case AArch64::AUTDB:
    case AArch64::AUTIA:
    case AArch64::AUTIB:
    case AArch64::BFCVTN2:
    case AArch64::FCVTNv4i32:
    case AArch64::FCVTNv8i16:
    case AArch64::FCVTXNv4f32:
    case AArch64::PACDA:
    case AArch64::PACDB:
    case AArch64::PACIA:
    case AArch64::PACIB:
    case AArch64::SADALPv16i8_v8i16:
    case AArch64::SADALPv2i32_v1i64:
    case AArch64::SADALPv4i16_v2i32:
    case AArch64::SADALPv4i32_v2i64:
    case AArch64::SADALPv8i16_v4i32:
    case AArch64::SADALPv8i8_v4i16:
    case AArch64::SHA1SU1rr:
    case AArch64::SHA256SU0rr:
    case AArch64::SQXTNv16i8:
    case AArch64::SQXTNv4i32:
    case AArch64::SQXTNv8i16:
    case AArch64::SQXTUNv16i8:
    case AArch64::SQXTUNv4i32:
    case AArch64::SQXTUNv8i16:
    case AArch64::SUQADDv16i8:
    case AArch64::SUQADDv1i16:
    case AArch64::SUQADDv1i32:
    case AArch64::SUQADDv1i64:
    case AArch64::SUQADDv1i8:
    case AArch64::SUQADDv2i32:
    case AArch64::SUQADDv2i64:
    case AArch64::SUQADDv4i16:
    case AArch64::SUQADDv4i32:
    case AArch64::SUQADDv8i16:
    case AArch64::SUQADDv8i8:
    case AArch64::UADALPv16i8_v8i16:
    case AArch64::UADALPv2i32_v1i64:
    case AArch64::UADALPv4i16_v2i32:
    case AArch64::UADALPv4i32_v2i64:
    case AArch64::UADALPv8i16_v4i32:
    case AArch64::UADALPv8i8_v4i16:
    case AArch64::UQXTNv16i8:
    case AArch64::UQXTNv4i32:
    case AArch64::UQXTNv8i16:
    case AArch64::USQADDv16i8:
    case AArch64::USQADDv1i16:
    case AArch64::USQADDv1i32:
    case AArch64::USQADDv1i64:
    case AArch64::USQADDv1i8:
    case AArch64::USQADDv2i32:
    case AArch64::USQADDv2i64:
    case AArch64::USQADDv4i16:
    case AArch64::USQADDv4i32:
    case AArch64::USQADDv8i16:
    case AArch64::USQADDv8i8:
    case AArch64::XTNv16i8:
    case AArch64::XTNv4i32:
    case AArch64::XTNv8i16: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 2:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::BICv2i32:
    case AArch64::BICv4i16:
    case AArch64::BICv4i32:
    case AArch64::BICv8i16:
    case AArch64::ORRv2i32:
    case AArch64::ORRv4i16:
    case AArch64::ORRv4i32:
    case AArch64::ORRv8i16: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 2:
        // op: imm8
        return 5;
      case 3:
        // op: shift
        return 13;
      }
      break;
    }
    case AArch64::INSvi8lane: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 17;
      case 4:
        // op: idx2
        return 11;
      }
      break;
    }
    case AArch64::INSvi8gpr: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 17;
      }
      break;
    }
    case AArch64::INSvi16lane: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 18;
      case 4:
        // op: idx2
        return 12;
      }
      break;
    }
    case AArch64::INSvi16gpr: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 18;
      }
      break;
    }
    case AArch64::INSvi32lane: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 19;
      case 4:
        // op: idx2
        return 13;
      }
      break;
    }
    case AArch64::INSvi32gpr: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 19;
      }
      break;
    }
    case AArch64::INSvi64lane: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 20;
      case 4:
        // op: idx2
        return 14;
      }
      break;
    }
    case AArch64::INSvi64gpr: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 20;
      }
      break;
    }
    case AArch64::AUTDZA:
    case AArch64::AUTDZB:
    case AArch64::AUTIZA:
    case AArch64::AUTIZB:
    case AArch64::PACDZA:
    case AArch64::PACDZB:
    case AArch64::PACIZA:
    case AArch64::PACIZB: {
      switch (OpNum) {
      case 1:
        // op: Rd
        return 0;
      }
      break;
    }
    case AArch64::CTERMEQ_WW:
    case AArch64::CTERMEQ_XX:
    case AArch64::CTERMNE_WW:
    case AArch64::CTERMNE_XX:
    case AArch64::FCMPDrr:
    case AArch64::FCMPEDrr:
    case AArch64::FCMPEHrr:
    case AArch64::FCMPESrr:
    case AArch64::FCMPHrr:
    case AArch64::FCMPSrr: {
      switch (OpNum) {
      case 1:
        // op: Rm
        return 16;
      case 0:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::CBBEQWrr:
    case AArch64::CBBGEWrr:
    case AArch64::CBBGTWrr:
    case AArch64::CBBHIWrr:
    case AArch64::CBBHSWrr:
    case AArch64::CBBNEWrr:
    case AArch64::CBEQWrr:
    case AArch64::CBEQXrr:
    case AArch64::CBGEWrr:
    case AArch64::CBGEXrr:
    case AArch64::CBGTWrr:
    case AArch64::CBGTXrr:
    case AArch64::CBHEQWrr:
    case AArch64::CBHGEWrr:
    case AArch64::CBHGTWrr:
    case AArch64::CBHHIWrr:
    case AArch64::CBHHSWrr:
    case AArch64::CBHIWrr:
    case AArch64::CBHIXrr:
    case AArch64::CBHNEWrr:
    case AArch64::CBHSWrr:
    case AArch64::CBHSXrr:
    case AArch64::CBNEWrr:
    case AArch64::CBNEXrr: {
      switch (OpNum) {
      case 1:
        // op: Rm
        return 16;
      case 0:
        // op: Rt
        return 0;
      case 2:
        // op: target
        return 5;
      }
      break;
    }
    case AArch64::ST2Gi:
    case AArch64::STGi:
    case AArch64::STZ2Gi:
    case AArch64::STZGi: {
      switch (OpNum) {
      case 1:
        // op: Rn
        return 5;
      case 0:
        // op: Rt
        return 0;
      case 2:
        // op: offset
        return 12;
      }
      break;
    }
    case AArch64::LDAPRB:
    case AArch64::LDAPRH:
    case AArch64::LDAPRW:
    case AArch64::LDAPRX:
    case AArch64::LDGM:
    case AArch64::STGM:
    case AArch64::STZGM: {
      switch (OpNum) {
      case 1:
        // op: Rn
        return 5;
      case 0:
        // op: Rt
        return 0;
      }
      break;
    }
    case AArch64::INDEX_RI_B:
    case AArch64::INDEX_RI_D:
    case AArch64::INDEX_RI_H:
    case AArch64::INDEX_RI_S: {
      switch (OpNum) {
      case 1:
        // op: Rn
        return 5;
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: imm5
        return 16;
      }
      break;
    }
    case AArch64::DUP_ZR_B:
    case AArch64::DUP_ZR_D:
    case AArch64::DUP_ZR_H:
    case AArch64::DUP_ZR_S: {
      switch (OpNum) {
      case 1:
        // op: Rn
        return 5;
      case 0:
        // op: Zd
        return 0;
      }
      break;
    }
    case AArch64::LDR_ZXI:
    case AArch64::STR_ZXI: {
      switch (OpNum) {
      case 1:
        // op: Rn
        return 5;
      case 0:
        // op: Zt
        return 0;
      case 2:
        // op: imm9
        return 10;
      }
      break;
    }
    case AArch64::LDR_TX:
    case AArch64::STR_TX: {
      switch (OpNum) {
      case 1:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::LDADDAB:
    case AArch64::LDADDAH:
    case AArch64::LDADDALB:
    case AArch64::LDADDALH:
    case AArch64::LDADDALW:
    case AArch64::LDADDALX:
    case AArch64::LDADDAW:
    case AArch64::LDADDAX:
    case AArch64::LDADDB:
    case AArch64::LDADDH:
    case AArch64::LDADDLB:
    case AArch64::LDADDLH:
    case AArch64::LDADDLW:
    case AArch64::LDADDLX:
    case AArch64::LDADDW:
    case AArch64::LDADDX:
    case AArch64::LDCLRAB:
    case AArch64::LDCLRAH:
    case AArch64::LDCLRALB:
    case AArch64::LDCLRALH:
    case AArch64::LDCLRALW:
    case AArch64::LDCLRALX:
    case AArch64::LDCLRAW:
    case AArch64::LDCLRAX:
    case AArch64::LDCLRB:
    case AArch64::LDCLRH:
    case AArch64::LDCLRLB:
    case AArch64::LDCLRLH:
    case AArch64::LDCLRLW:
    case AArch64::LDCLRLX:
    case AArch64::LDCLRW:
    case AArch64::LDCLRX:
    case AArch64::LDEORAB:
    case AArch64::LDEORAH:
    case AArch64::LDEORALB:
    case AArch64::LDEORALH:
    case AArch64::LDEORALW:
    case AArch64::LDEORALX:
    case AArch64::LDEORAW:
    case AArch64::LDEORAX:
    case AArch64::LDEORB:
    case AArch64::LDEORH:
    case AArch64::LDEORLB:
    case AArch64::LDEORLH:
    case AArch64::LDEORLW:
    case AArch64::LDEORLX:
    case AArch64::LDEORW:
    case AArch64::LDEORX:
    case AArch64::LDSETAB:
    case AArch64::LDSETAH:
    case AArch64::LDSETALB:
    case AArch64::LDSETALH:
    case AArch64::LDSETALW:
    case AArch64::LDSETALX:
    case AArch64::LDSETAW:
    case AArch64::LDSETAX:
    case AArch64::LDSETB:
    case AArch64::LDSETH:
    case AArch64::LDSETLB:
    case AArch64::LDSETLH:
    case AArch64::LDSETLW:
    case AArch64::LDSETLX:
    case AArch64::LDSETW:
    case AArch64::LDSETX:
    case AArch64::LDSMAXAB:
    case AArch64::LDSMAXAH:
    case AArch64::LDSMAXALB:
    case AArch64::LDSMAXALH:
    case AArch64::LDSMAXALW:
    case AArch64::LDSMAXALX:
    case AArch64::LDSMAXAW:
    case AArch64::LDSMAXAX:
    case AArch64::LDSMAXB:
    case AArch64::LDSMAXH:
    case AArch64::LDSMAXLB:
    case AArch64::LDSMAXLH:
    case AArch64::LDSMAXLW:
    case AArch64::LDSMAXLX:
    case AArch64::LDSMAXW:
    case AArch64::LDSMAXX:
    case AArch64::LDSMINAB:
    case AArch64::LDSMINAH:
    case AArch64::LDSMINALB:
    case AArch64::LDSMINALH:
    case AArch64::LDSMINALW:
    case AArch64::LDSMINALX:
    case AArch64::LDSMINAW:
    case AArch64::LDSMINAX:
    case AArch64::LDSMINB:
    case AArch64::LDSMINH:
    case AArch64::LDSMINLB:
    case AArch64::LDSMINLH:
    case AArch64::LDSMINLW:
    case AArch64::LDSMINLX:
    case AArch64::LDSMINW:
    case AArch64::LDSMINX:
    case AArch64::LDTADDALW:
    case AArch64::LDTADDALX:
    case AArch64::LDTADDAW:
    case AArch64::LDTADDAX:
    case AArch64::LDTADDLW:
    case AArch64::LDTADDLX:
    case AArch64::LDTADDW:
    case AArch64::LDTADDX:
    case AArch64::LDTCLRALW:
    case AArch64::LDTCLRALX:
    case AArch64::LDTCLRAW:
    case AArch64::LDTCLRAX:
    case AArch64::LDTCLRLW:
    case AArch64::LDTCLRLX:
    case AArch64::LDTCLRW:
    case AArch64::LDTCLRX:
    case AArch64::LDTSETALW:
    case AArch64::LDTSETALX:
    case AArch64::LDTSETAW:
    case AArch64::LDTSETAX:
    case AArch64::LDTSETLW:
    case AArch64::LDTSETLX:
    case AArch64::LDTSETW:
    case AArch64::LDTSETX:
    case AArch64::LDUMAXAB:
    case AArch64::LDUMAXAH:
    case AArch64::LDUMAXALB:
    case AArch64::LDUMAXALH:
    case AArch64::LDUMAXALW:
    case AArch64::LDUMAXALX:
    case AArch64::LDUMAXAW:
    case AArch64::LDUMAXAX:
    case AArch64::LDUMAXB:
    case AArch64::LDUMAXH:
    case AArch64::LDUMAXLB:
    case AArch64::LDUMAXLH:
    case AArch64::LDUMAXLW:
    case AArch64::LDUMAXLX:
    case AArch64::LDUMAXW:
    case AArch64::LDUMAXX:
    case AArch64::LDUMINAB:
    case AArch64::LDUMINAH:
    case AArch64::LDUMINALB:
    case AArch64::LDUMINALH:
    case AArch64::LDUMINALW:
    case AArch64::LDUMINALX:
    case AArch64::LDUMINAW:
    case AArch64::LDUMINAX:
    case AArch64::LDUMINB:
    case AArch64::LDUMINH:
    case AArch64::LDUMINLB:
    case AArch64::LDUMINLH:
    case AArch64::LDUMINLW:
    case AArch64::LDUMINLX:
    case AArch64::LDUMINW:
    case AArch64::LDUMINX:
    case AArch64::RCWCLR:
    case AArch64::RCWCLRA:
    case AArch64::RCWCLRAL:
    case AArch64::RCWCLRL:
    case AArch64::RCWCLRS:
    case AArch64::RCWCLRSA:
    case AArch64::RCWCLRSAL:
    case AArch64::RCWCLRSL:
    case AArch64::RCWSET:
    case AArch64::RCWSETA:
    case AArch64::RCWSETAL:
    case AArch64::RCWSETL:
    case AArch64::RCWSETS:
    case AArch64::RCWSETSA:
    case AArch64::RCWSETSAL:
    case AArch64::RCWSETSL:
    case AArch64::RCWSWP:
    case AArch64::RCWSWPA:
    case AArch64::RCWSWPAL:
    case AArch64::RCWSWPL:
    case AArch64::RCWSWPS:
    case AArch64::RCWSWPSA:
    case AArch64::RCWSWPSAL:
    case AArch64::RCWSWPSL:
    case AArch64::SWPAB:
    case AArch64::SWPAH:
    case AArch64::SWPALB:
    case AArch64::SWPALH:
    case AArch64::SWPALW:
    case AArch64::SWPALX:
    case AArch64::SWPAW:
    case AArch64::SWPAX:
    case AArch64::SWPB:
    case AArch64::SWPH:
    case AArch64::SWPLB:
    case AArch64::SWPLH:
    case AArch64::SWPLW:
    case AArch64::SWPLX:
    case AArch64::SWPTALW:
    case AArch64::SWPTALX:
    case AArch64::SWPTAW:
    case AArch64::SWPTAX:
    case AArch64::SWPTLW:
    case AArch64::SWPTLX:
    case AArch64::SWPTW:
    case AArch64::SWPTX:
    case AArch64::SWPW:
    case AArch64::SWPX: {
      switch (OpNum) {
      case 1:
        // op: Rs
        return 16;
      case 2:
        // op: Rn
        return 5;
      case 0:
        // op: Rt
        return 0;
      }
      break;
    }
    case AArch64::CASAB:
    case AArch64::CASAH:
    case AArch64::CASALB:
    case AArch64::CASALH:
    case AArch64::CASALTX:
    case AArch64::CASALW:
    case AArch64::CASALX:
    case AArch64::CASATX:
    case AArch64::CASAW:
    case AArch64::CASAX:
    case AArch64::CASB:
    case AArch64::CASH:
    case AArch64::CASLB:
    case AArch64::CASLH:
    case AArch64::CASLTX:
    case AArch64::CASLW:
    case AArch64::CASLX:
    case AArch64::CASPALTX:
    case AArch64::CASPALW:
    case AArch64::CASPALX:
    case AArch64::CASPATX:
    case AArch64::CASPAW:
    case AArch64::CASPAX:
    case AArch64::CASPLTX:
    case AArch64::CASPLW:
    case AArch64::CASPLX:
    case AArch64::CASPTX:
    case AArch64::CASPW:
    case AArch64::CASPX:
    case AArch64::CASTX:
    case AArch64::CASW:
    case AArch64::CASX:
    case AArch64::RCWCAS:
    case AArch64::RCWCASA:
    case AArch64::RCWCASAL:
    case AArch64::RCWCASL:
    case AArch64::RCWCASP:
    case AArch64::RCWCASPA:
    case AArch64::RCWCASPAL:
    case AArch64::RCWCASPL:
    case AArch64::RCWSCAS:
    case AArch64::RCWSCASA:
    case AArch64::RCWSCASAL:
    case AArch64::RCWSCASL:
    case AArch64::RCWSCASP:
    case AArch64::RCWSCASPA:
    case AArch64::RCWSCASPAL:
    case AArch64::RCWSCASPL: {
      switch (OpNum) {
      case 1:
        // op: Rs
        return 16;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: Rt
        return 0;
      }
      break;
    }
    case AArch64::MSR:
    case AArch64::MSRR: {
      switch (OpNum) {
      case 1:
        // op: Rt
        return 0;
      case 0:
        // op: systemreg
        return 5;
      }
      break;
    }
    case AArch64::ST64BV:
    case AArch64::ST64BV0: {
      switch (OpNum) {
      case 1:
        // op: Rt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 0:
        // op: Rs
        return 16;
      }
      break;
    }
    case AArch64::STTXRWr:
    case AArch64::STTXRXr: {
      switch (OpNum) {
      case 1:
        // op: Rt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 0:
        // op: Ws
        return 16;
      }
      break;
    }
    case AArch64::LDRBBpost:
    case AArch64::LDRBBpre:
    case AArch64::LDRBpost:
    case AArch64::LDRBpre:
    case AArch64::LDRDpost:
    case AArch64::LDRDpre:
    case AArch64::LDRHHpost:
    case AArch64::LDRHHpre:
    case AArch64::LDRHpost:
    case AArch64::LDRHpre:
    case AArch64::LDRQpost:
    case AArch64::LDRQpre:
    case AArch64::LDRSBWpost:
    case AArch64::LDRSBWpre:
    case AArch64::LDRSBXpost:
    case AArch64::LDRSBXpre:
    case AArch64::LDRSHWpost:
    case AArch64::LDRSHWpre:
    case AArch64::LDRSHXpost:
    case AArch64::LDRSHXpre:
    case AArch64::LDRSWpost:
    case AArch64::LDRSWpre:
    case AArch64::LDRSpost:
    case AArch64::LDRSpre:
    case AArch64::LDRWpost:
    case AArch64::LDRWpre:
    case AArch64::LDRXpost:
    case AArch64::LDRXpre:
    case AArch64::STRBBpost:
    case AArch64::STRBBpre:
    case AArch64::STRBpost:
    case AArch64::STRBpre:
    case AArch64::STRDpost:
    case AArch64::STRDpre:
    case AArch64::STRHHpost:
    case AArch64::STRHHpre:
    case AArch64::STRHpost:
    case AArch64::STRHpre:
    case AArch64::STRQpost:
    case AArch64::STRQpre:
    case AArch64::STRSpost:
    case AArch64::STRSpre:
    case AArch64::STRWpost:
    case AArch64::STRWpre:
    case AArch64::STRXpost:
    case AArch64::STRXpre: {
      switch (OpNum) {
      case 1:
        // op: Rt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: offset
        return 12;
      }
      break;
    }
    case AArch64::LDAPRWpost:
    case AArch64::LDAPRXpost:
    case AArch64::STLRWpre:
    case AArch64::STLRXpre: {
      switch (OpNum) {
      case 1:
        // op: Rt
        return 0;
      case 2:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::LDPDpost:
    case AArch64::LDPDpre:
    case AArch64::LDPQpost:
    case AArch64::LDPQpre:
    case AArch64::LDPSWpost:
    case AArch64::LDPSWpre:
    case AArch64::LDPSpost:
    case AArch64::LDPSpre:
    case AArch64::LDPWpost:
    case AArch64::LDPWpre:
    case AArch64::LDPXpost:
    case AArch64::LDPXpre:
    case AArch64::LDTPQpost:
    case AArch64::LDTPQpre:
    case AArch64::LDTPpost:
    case AArch64::LDTPpre:
    case AArch64::STGPpost:
    case AArch64::STGPpre:
    case AArch64::STPDpost:
    case AArch64::STPDpre:
    case AArch64::STPQpost:
    case AArch64::STPQpre:
    case AArch64::STPSpost:
    case AArch64::STPSpre:
    case AArch64::STPWpost:
    case AArch64::STPWpre:
    case AArch64::STPXpost:
    case AArch64::STPXpre:
    case AArch64::STTPQpost:
    case AArch64::STTPQpre:
    case AArch64::STTPpost:
    case AArch64::STTPpre: {
      switch (OpNum) {
      case 1:
        // op: Rt
        return 0;
      case 2:
        // op: Rt2
        return 10;
      case 3:
        // op: Rn
        return 5;
      case 4:
        // op: offset
        return 15;
      }
      break;
    }
    case AArch64::LDIAPPWpost:
    case AArch64::LDIAPPXpost:
    case AArch64::STILPWpre:
    case AArch64::STILPXpre: {
      switch (OpNum) {
      case 1:
        // op: Rt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: Rt2
        return 16;
      }
      break;
    }
    case AArch64::LDR_ZA:
    case AArch64::STR_ZA: {
      switch (OpNum) {
      case 1:
        // op: Rv
        return 13;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: imm4
        return 0;
      }
      break;
    }
    case AArch64::SHA512H:
    case AArch64::SHA512H2:
    case AArch64::SHA512SU1:
    case AArch64::SM3PARTW1:
    case AArch64::SM3PARTW2:
    case AArch64::TBXv16i8Four:
    case AArch64::TBXv16i8One:
    case AArch64::TBXv16i8Three:
    case AArch64::TBXv16i8Two:
    case AArch64::TBXv8i8Four:
    case AArch64::TBXv8i8One:
    case AArch64::TBXv8i8Three:
    case AArch64::TBXv8i8Two: {
      switch (OpNum) {
      case 1:
        // op: Vd
        return 0;
      case 2:
        // op: Vn
        return 5;
      case 3:
        // op: Vm
        return 16;
      }
      break;
    }
    case AArch64::SM3TT1A:
    case AArch64::SM3TT1B:
    case AArch64::SM3TT2A:
    case AArch64::SM3TT2B: {
      switch (OpNum) {
      case 1:
        // op: Vd
        return 0;
      case 2:
        // op: Vn
        return 5;
      case 4:
        // op: imm
        return 12;
      case 3:
        // op: Vm
        return 16;
      }
      break;
    }
    case AArch64::SHA512SU0:
    case AArch64::SM4E: {
      switch (OpNum) {
      case 1:
        // op: Vd
        return 0;
      case 2:
        // op: Vn
        return 5;
      }
      break;
    }
    case AArch64::LD1Fourv16b_POST:
    case AArch64::LD1Fourv1d_POST:
    case AArch64::LD1Fourv2d_POST:
    case AArch64::LD1Fourv2s_POST:
    case AArch64::LD1Fourv4h_POST:
    case AArch64::LD1Fourv4s_POST:
    case AArch64::LD1Fourv8b_POST:
    case AArch64::LD1Fourv8h_POST:
    case AArch64::LD1Onev16b_POST:
    case AArch64::LD1Onev1d_POST:
    case AArch64::LD1Onev2d_POST:
    case AArch64::LD1Onev2s_POST:
    case AArch64::LD1Onev4h_POST:
    case AArch64::LD1Onev4s_POST:
    case AArch64::LD1Onev8b_POST:
    case AArch64::LD1Onev8h_POST:
    case AArch64::LD1Rv16b_POST:
    case AArch64::LD1Rv1d_POST:
    case AArch64::LD1Rv2d_POST:
    case AArch64::LD1Rv2s_POST:
    case AArch64::LD1Rv4h_POST:
    case AArch64::LD1Rv4s_POST:
    case AArch64::LD1Rv8b_POST:
    case AArch64::LD1Rv8h_POST:
    case AArch64::LD1Threev16b_POST:
    case AArch64::LD1Threev1d_POST:
    case AArch64::LD1Threev2d_POST:
    case AArch64::LD1Threev2s_POST:
    case AArch64::LD1Threev4h_POST:
    case AArch64::LD1Threev4s_POST:
    case AArch64::LD1Threev8b_POST:
    case AArch64::LD1Threev8h_POST:
    case AArch64::LD1Twov16b_POST:
    case AArch64::LD1Twov1d_POST:
    case AArch64::LD1Twov2d_POST:
    case AArch64::LD1Twov2s_POST:
    case AArch64::LD1Twov4h_POST:
    case AArch64::LD1Twov4s_POST:
    case AArch64::LD1Twov8b_POST:
    case AArch64::LD1Twov8h_POST:
    case AArch64::LD2Rv16b_POST:
    case AArch64::LD2Rv1d_POST:
    case AArch64::LD2Rv2d_POST:
    case AArch64::LD2Rv2s_POST:
    case AArch64::LD2Rv4h_POST:
    case AArch64::LD2Rv4s_POST:
    case AArch64::LD2Rv8b_POST:
    case AArch64::LD2Rv8h_POST:
    case AArch64::LD2Twov16b_POST:
    case AArch64::LD2Twov2d_POST:
    case AArch64::LD2Twov2s_POST:
    case AArch64::LD2Twov4h_POST:
    case AArch64::LD2Twov4s_POST:
    case AArch64::LD2Twov8b_POST:
    case AArch64::LD2Twov8h_POST:
    case AArch64::LD3Rv16b_POST:
    case AArch64::LD3Rv1d_POST:
    case AArch64::LD3Rv2d_POST:
    case AArch64::LD3Rv2s_POST:
    case AArch64::LD3Rv4h_POST:
    case AArch64::LD3Rv4s_POST:
    case AArch64::LD3Rv8b_POST:
    case AArch64::LD3Rv8h_POST:
    case AArch64::LD3Threev16b_POST:
    case AArch64::LD3Threev2d_POST:
    case AArch64::LD3Threev2s_POST:
    case AArch64::LD3Threev4h_POST:
    case AArch64::LD3Threev4s_POST:
    case AArch64::LD3Threev8b_POST:
    case AArch64::LD3Threev8h_POST:
    case AArch64::LD4Fourv16b_POST:
    case AArch64::LD4Fourv2d_POST:
    case AArch64::LD4Fourv2s_POST:
    case AArch64::LD4Fourv4h_POST:
    case AArch64::LD4Fourv4s_POST:
    case AArch64::LD4Fourv8b_POST:
    case AArch64::LD4Fourv8h_POST:
    case AArch64::LD4Rv16b_POST:
    case AArch64::LD4Rv1d_POST:
    case AArch64::LD4Rv2d_POST:
    case AArch64::LD4Rv2s_POST:
    case AArch64::LD4Rv4h_POST:
    case AArch64::LD4Rv4s_POST:
    case AArch64::LD4Rv8b_POST:
    case AArch64::LD4Rv8h_POST:
    case AArch64::ST1Fourv16b_POST:
    case AArch64::ST1Fourv1d_POST:
    case AArch64::ST1Fourv2d_POST:
    case AArch64::ST1Fourv2s_POST:
    case AArch64::ST1Fourv4h_POST:
    case AArch64::ST1Fourv4s_POST:
    case AArch64::ST1Fourv8b_POST:
    case AArch64::ST1Fourv8h_POST:
    case AArch64::ST1Onev16b_POST:
    case AArch64::ST1Onev1d_POST:
    case AArch64::ST1Onev2d_POST:
    case AArch64::ST1Onev2s_POST:
    case AArch64::ST1Onev4h_POST:
    case AArch64::ST1Onev4s_POST:
    case AArch64::ST1Onev8b_POST:
    case AArch64::ST1Onev8h_POST:
    case AArch64::ST1Threev16b_POST:
    case AArch64::ST1Threev1d_POST:
    case AArch64::ST1Threev2d_POST:
    case AArch64::ST1Threev2s_POST:
    case AArch64::ST1Threev4h_POST:
    case AArch64::ST1Threev4s_POST:
    case AArch64::ST1Threev8b_POST:
    case AArch64::ST1Threev8h_POST:
    case AArch64::ST1Twov16b_POST:
    case AArch64::ST1Twov1d_POST:
    case AArch64::ST1Twov2d_POST:
    case AArch64::ST1Twov2s_POST:
    case AArch64::ST1Twov4h_POST:
    case AArch64::ST1Twov4s_POST:
    case AArch64::ST1Twov8b_POST:
    case AArch64::ST1Twov8h_POST:
    case AArch64::ST2Twov16b_POST:
    case AArch64::ST2Twov2d_POST:
    case AArch64::ST2Twov2s_POST:
    case AArch64::ST2Twov4h_POST:
    case AArch64::ST2Twov4s_POST:
    case AArch64::ST2Twov8b_POST:
    case AArch64::ST2Twov8h_POST:
    case AArch64::ST3Threev16b_POST:
    case AArch64::ST3Threev2d_POST:
    case AArch64::ST3Threev2s_POST:
    case AArch64::ST3Threev4h_POST:
    case AArch64::ST3Threev4s_POST:
    case AArch64::ST3Threev8b_POST:
    case AArch64::ST3Threev8h_POST:
    case AArch64::ST4Fourv16b_POST:
    case AArch64::ST4Fourv2d_POST:
    case AArch64::ST4Fourv2s_POST:
    case AArch64::ST4Fourv4h_POST:
    case AArch64::ST4Fourv4s_POST:
    case AArch64::ST4Fourv8b_POST:
    case AArch64::ST4Fourv8h_POST: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 2:
        // op: Rn
        return 5;
      case 3:
        // op: Xm
        return 16;
      }
      break;
    }
    case AArch64::LDAP1: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: Q
        return 30;
      }
      break;
    }
    case AArch64::ST1i8_POST:
    case AArch64::ST2i8_POST:
    case AArch64::ST3i8_POST:
    case AArch64::ST4i8_POST: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 10;
      case 4:
        // op: Xm
        return 16;
      }
      break;
    }
    case AArch64::LD1i8:
    case AArch64::LD2i8:
    case AArch64::LD3i8:
    case AArch64::LD4i8: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 10;
      }
      break;
    }
    case AArch64::ST1i16_POST:
    case AArch64::ST2i16_POST:
    case AArch64::ST3i16_POST:
    case AArch64::ST4i16_POST: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 11;
      case 4:
        // op: Xm
        return 16;
      }
      break;
    }
    case AArch64::LD1i16:
    case AArch64::LD2i16:
    case AArch64::LD3i16:
    case AArch64::LD4i16: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 11;
      }
      break;
    }
    case AArch64::ST1i32_POST:
    case AArch64::ST2i32_POST:
    case AArch64::ST3i32_POST:
    case AArch64::ST4i32_POST: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 12;
      case 4:
        // op: Xm
        return 16;
      }
      break;
    }
    case AArch64::LD1i32:
    case AArch64::LD2i32:
    case AArch64::LD3i32:
    case AArch64::LD4i32: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 12;
      }
      break;
    }
    case AArch64::ST1i64_POST:
    case AArch64::ST2i64_POST:
    case AArch64::ST3i64_POST:
    case AArch64::ST4i64_POST: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 30;
      case 4:
        // op: Xm
        return 16;
      }
      break;
    }
    case AArch64::LD1i64:
    case AArch64::LD2i64:
    case AArch64::LD3i64:
    case AArch64::LD4i64: {
      switch (OpNum) {
      case 1:
        // op: Vt
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 2:
        // op: idx
        return 30;
      }
      break;
    }
    case AArch64::BF1CVTL_2ZZ_BtoH:
    case AArch64::BF1CVT_2ZZ_BtoH:
    case AArch64::BF2CVTL_2ZZ_BtoH:
    case AArch64::BF2CVT_2ZZ_BtoH:
    case AArch64::F1CVTL_2ZZ_BtoH:
    case AArch64::F1CVT_2ZZ_BtoH:
    case AArch64::F2CVTL_2ZZ_BtoH:
    case AArch64::F2CVT_2ZZ_BtoH:
    case AArch64::FCVTL_2ZZ_H_S:
    case AArch64::FCVT_2ZZ_H_S:
    case AArch64::SUNPK_VG2_2ZZ_D:
    case AArch64::SUNPK_VG2_2ZZ_H:
    case AArch64::SUNPK_VG2_2ZZ_S:
    case AArch64::UUNPK_VG2_2ZZ_D:
    case AArch64::UUNPK_VG2_2ZZ_H:
    case AArch64::UUNPK_VG2_2ZZ_S: {
      switch (OpNum) {
      case 1:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 1;
      }
      break;
    }
    case AArch64::BFCVTN_Z2Z_StoH:
    case AArch64::BFCVT_Z2Z_HtoB:
    case AArch64::BFCVT_Z2Z_StoH:
    case AArch64::FCVTN_Z2Z_StoH:
    case AArch64::FCVT_Z2Z_HtoB:
    case AArch64::FCVT_Z2Z_StoH:
    case AArch64::SQCVTU_Z2Z_StoH:
    case AArch64::SQCVT_Z2Z_StoH:
    case AArch64::UQCVT_Z2Z_StoH: {
      switch (OpNum) {
      case 1:
        // op: Zn
        return 6;
      case 0:
        // op: Zd
        return 0;
      }
      break;
    }
    case AArch64::FCVTZS_2Z2Z_StoS:
    case AArch64::FCVTZU_2Z2Z_StoS:
    case AArch64::FRINTA_2Z2Z_S:
    case AArch64::FRINTM_2Z2Z_S:
    case AArch64::FRINTN_2Z2Z_S:
    case AArch64::FRINTP_2Z2Z_S:
    case AArch64::SCVTF_2Z2Z_StoS:
    case AArch64::UCVTF_2Z2Z_StoS: {
      switch (OpNum) {
      case 1:
        // op: Zn
        return 6;
      case 0:
        // op: Zd
        return 1;
      }
      break;
    }
    case AArch64::SUNPK_VG4_4Z2Z_D:
    case AArch64::SUNPK_VG4_4Z2Z_H:
    case AArch64::SUNPK_VG4_4Z2Z_S:
    case AArch64::UUNPK_VG4_4Z2Z_D:
    case AArch64::UUNPK_VG4_4Z2Z_H:
    case AArch64::UUNPK_VG4_4Z2Z_S: {
      switch (OpNum) {
      case 1:
        // op: Zn
        return 6;
      case 0:
        // op: Zd
        return 2;
      }
      break;
    }
    case AArch64::SQRSHRN_VG4_Z4ZI_B:
    case AArch64::SQRSHRN_VG4_Z4ZI_H:
    case AArch64::SQRSHRUN_VG4_Z4ZI_B:
    case AArch64::SQRSHRUN_VG4_Z4ZI_H:
    case AArch64::SQRSHRU_VG4_Z4ZI_B:
    case AArch64::SQRSHRU_VG4_Z4ZI_H:
    case AArch64::SQRSHR_VG4_Z4ZI_B:
    case AArch64::SQRSHR_VG4_Z4ZI_H:
    case AArch64::UQRSHRN_VG4_Z4ZI_B:
    case AArch64::UQRSHRN_VG4_Z4ZI_H:
    case AArch64::UQRSHR_VG4_Z4ZI_B:
    case AArch64::UQRSHR_VG4_Z4ZI_H: {
      switch (OpNum) {
      case 1:
        // op: Zn
        return 7;
      case 0:
        // op: Zd
        return 0;
      case 2:
        // op: imm
        return 16;
      }
      break;
    }
    case AArch64::FCVTN_Z4Z_StoB:
    case AArch64::FCVT_Z4Z_StoB:
    case AArch64::SQCVTN_Z4Z_DtoH:
    case AArch64::SQCVTN_Z4Z_StoB:
    case AArch64::SQCVTUN_Z4Z_DtoH:
    case AArch64::SQCVTUN_Z4Z_StoB:
    case AArch64::SQCVTU_Z4Z_DtoH:
    case AArch64::SQCVTU_Z4Z_StoB:
    case AArch64::SQCVT_Z4Z_DtoH:
    case AArch64::SQCVT_Z4Z_StoB:
    case AArch64::UQCVTN_Z4Z_DtoH:
    case AArch64::UQCVTN_Z4Z_StoB:
    case AArch64::UQCVT_Z4Z_DtoH:
    case AArch64::UQCVT_Z4Z_StoB: {
      switch (OpNum) {
      case 1:
        // op: Zn
        return 7;
      case 0:
        // op: Zd
        return 0;
      }
      break;
    }
    case AArch64::FCVTZS_4Z4Z_StoS:
    case AArch64::FCVTZU_4Z4Z_StoS:
    case AArch64::FRINTA_4Z4Z_S:
    case AArch64::FRINTM_4Z4Z_S:
    case AArch64::FRINTN_4Z4Z_S:
    case AArch64::FRINTP_4Z4Z_S:
    case AArch64::SCVTF_4Z4Z_StoS:
    case AArch64::UCVTF_4Z4Z_StoS:
    case AArch64::UZP_VG4_4Z4Z_B:
    case AArch64::UZP_VG4_4Z4Z_D:
    case AArch64::UZP_VG4_4Z4Z_H:
    case AArch64::UZP_VG4_4Z4Z_Q:
    case AArch64::UZP_VG4_4Z4Z_S:
    case AArch64::ZIP_VG4_4Z4Z_B:
    case AArch64::ZIP_VG4_4Z4Z_D:
    case AArch64::ZIP_VG4_4Z4Z_H:
    case AArch64::ZIP_VG4_4Z4Z_Q:
    case AArch64::ZIP_VG4_4Z4Z_S: {
      switch (OpNum) {
      case 1:
        // op: Zn
        return 7;
      case 0:
        // op: Zd
        return 2;
      }
      break;
    }
    case AArch64::MOVT_TIX: {
      switch (OpNum) {
      case 1:
        // op: imm3
        return 12;
      case 2:
        // op: Rt
        return 0;
      }
      break;
    }
    case AArch64::ABS_ZPmZ_B:
    case AArch64::ABS_ZPmZ_D:
    case AArch64::ABS_ZPmZ_H:
    case AArch64::ABS_ZPmZ_S:
    case AArch64::BFCVT_ZPmZ:
    case AArch64::CLS_ZPmZ_B:
    case AArch64::CLS_ZPmZ_D:
    case AArch64::CLS_ZPmZ_H:
    case AArch64::CLS_ZPmZ_S:
    case AArch64::CLZ_ZPmZ_B:
    case AArch64::CLZ_ZPmZ_D:
    case AArch64::CLZ_ZPmZ_H:
    case AArch64::CLZ_ZPmZ_S:
    case AArch64::CNOT_ZPmZ_B:
    case AArch64::CNOT_ZPmZ_D:
    case AArch64::CNOT_ZPmZ_H:
    case AArch64::CNOT_ZPmZ_S:
    case AArch64::CNT_ZPmZ_B:
    case AArch64::CNT_ZPmZ_D:
    case AArch64::CNT_ZPmZ_H:
    case AArch64::CNT_ZPmZ_S:
    case AArch64::FABS_ZPmZ_D:
    case AArch64::FABS_ZPmZ_H:
    case AArch64::FABS_ZPmZ_S:
    case AArch64::FCVTX_ZPmZ_DtoS:
    case AArch64::FCVTZS_ZPmZ_DtoD:
    case AArch64::FCVTZS_ZPmZ_DtoS:
    case AArch64::FCVTZS_ZPmZ_HtoD:
    case AArch64::FCVTZS_ZPmZ_HtoH:
    case AArch64::FCVTZS_ZPmZ_HtoS:
    case AArch64::FCVTZS_ZPmZ_StoD:
    case AArch64::FCVTZS_ZPmZ_StoS:
    case AArch64::FCVTZU_ZPmZ_DtoD:
    case AArch64::FCVTZU_ZPmZ_DtoS:
    case AArch64::FCVTZU_ZPmZ_HtoD:
    case AArch64::FCVTZU_ZPmZ_HtoH:
    case AArch64::FCVTZU_ZPmZ_HtoS:
    case AArch64::FCVTZU_ZPmZ_StoD:
    case AArch64::FCVTZU_ZPmZ_StoS:
    case AArch64::FCVT_ZPmZ_DtoH:
    case AArch64::FCVT_ZPmZ_DtoS:
    case AArch64::FCVT_ZPmZ_HtoD:
    case AArch64::FCVT_ZPmZ_HtoS:
    case AArch64::FCVT_ZPmZ_StoD:
    case AArch64::FCVT_ZPmZ_StoH:
    case AArch64::FLOGB_ZPmZ_D:
    case AArch64::FLOGB_ZPmZ_H:
    case AArch64::FLOGB_ZPmZ_S:
    case AArch64::FNEG_ZPmZ_D:
    case AArch64::FNEG_ZPmZ_H:
    case AArch64::FNEG_ZPmZ_S:
    case AArch64::FRECPX_ZPmZ_D:
    case AArch64::FRECPX_ZPmZ_H:
    case AArch64::FRECPX_ZPmZ_S:
    case AArch64::FRINT32X_ZPmZ_D:
    case AArch64::FRINT32X_ZPmZ_S:
    case AArch64::FRINT32Z_ZPmZ_D:
    case AArch64::FRINT32Z_ZPmZ_S:
    case AArch64::FRINT64X_ZPmZ_D:
    case AArch64::FRINT64X_ZPmZ_S:
    case AArch64::FRINT64Z_ZPmZ_D:
    case AArch64::FRINT64Z_ZPmZ_S:
    case AArch64::FRINTA_ZPmZ_D:
    case AArch64::FRINTA_ZPmZ_H:
    case AArch64::FRINTA_ZPmZ_S:
    case AArch64::FRINTI_ZPmZ_D:
    case AArch64::FRINTI_ZPmZ_H:
    case AArch64::FRINTI_ZPmZ_S:
    case AArch64::FRINTM_ZPmZ_D:
    case AArch64::FRINTM_ZPmZ_H:
    case AArch64::FRINTM_ZPmZ_S:
    case AArch64::FRINTN_ZPmZ_D:
    case AArch64::FRINTN_ZPmZ_H:
    case AArch64::FRINTN_ZPmZ_S:
    case AArch64::FRINTP_ZPmZ_D:
    case AArch64::FRINTP_ZPmZ_H:
    case AArch64::FRINTP_ZPmZ_S:
    case AArch64::FRINTX_ZPmZ_D:
    case AArch64::FRINTX_ZPmZ_H:
    case AArch64::FRINTX_ZPmZ_S:
    case AArch64::FRINTZ_ZPmZ_D:
    case AArch64::FRINTZ_ZPmZ_H:
    case AArch64::FRINTZ_ZPmZ_S:
    case AArch64::FSQRT_ZPmZ_D:
    case AArch64::FSQRT_ZPmZ_H:
    case AArch64::FSQRT_ZPmZ_S:
    case AArch64::MOVPRFX_ZPmZ_B:
    case AArch64::MOVPRFX_ZPmZ_D:
    case AArch64::MOVPRFX_ZPmZ_H:
    case AArch64::MOVPRFX_ZPmZ_S:
    case AArch64::NEG_ZPmZ_B:
    case AArch64::NEG_ZPmZ_D:
    case AArch64::NEG_ZPmZ_H:
    case AArch64::NEG_ZPmZ_S:
    case AArch64::NOT_ZPmZ_B:
    case AArch64::NOT_ZPmZ_D:
    case AArch64::NOT_ZPmZ_H:
    case AArch64::NOT_ZPmZ_S:
    case AArch64::SCVTF_ZPmZ_DtoD:
    case AArch64::SCVTF_ZPmZ_DtoH:
    case AArch64::SCVTF_ZPmZ_DtoS:
    case AArch64::SCVTF_ZPmZ_HtoH:
    case AArch64::SCVTF_ZPmZ_StoD:
    case AArch64::SCVTF_ZPmZ_StoH:
    case AArch64::SCVTF_ZPmZ_StoS:
    case AArch64::SQABS_ZPmZ_B:
    case AArch64::SQABS_ZPmZ_D:
    case AArch64::SQABS_ZPmZ_H:
    case AArch64::SQABS_ZPmZ_S:
    case AArch64::SQNEG_ZPmZ_B:
    case AArch64::SQNEG_ZPmZ_D:
    case AArch64::SQNEG_ZPmZ_H:
    case AArch64::SQNEG_ZPmZ_S:
    case AArch64::SXTB_ZPmZ_D:
    case AArch64::SXTB_ZPmZ_H:
    case AArch64::SXTB_ZPmZ_S:
    case AArch64::SXTH_ZPmZ_D:
    case AArch64::SXTH_ZPmZ_S:
    case AArch64::SXTW_ZPmZ_D:
    case AArch64::UCVTF_ZPmZ_DtoD:
    case AArch64::UCVTF_ZPmZ_DtoH:
    case AArch64::UCVTF_ZPmZ_DtoS:
    case AArch64::UCVTF_ZPmZ_HtoH:
    case AArch64::UCVTF_ZPmZ_StoD:
    case AArch64::UCVTF_ZPmZ_StoH:
    case AArch64::UCVTF_ZPmZ_StoS:
    case AArch64::URECPE_ZPmZ_S:
    case AArch64::URSQRTE_ZPmZ_S:
    case AArch64::UXTB_ZPmZ_D:
    case AArch64::UXTB_ZPmZ_H:
    case AArch64::UXTB_ZPmZ_S:
    case AArch64::UXTH_ZPmZ_D:
    case AArch64::UXTH_ZPmZ_S:
    case AArch64::UXTW_ZPmZ_D: {
      switch (OpNum) {
      case 2:
        // op: Pg
        return 10;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: Zn
        return 5;
      }
      break;
    }
    case AArch64::CPY_ZPmR_B:
    case AArch64::CPY_ZPmR_D:
    case AArch64::CPY_ZPmR_H:
    case AArch64::CPY_ZPmR_S: {
      switch (OpNum) {
      case 2:
        // op: Pg
        return 10;
      case 3:
        // op: Rn
        return 5;
      case 0:
        // op: Zd
        return 0;
      }
      break;
    }
    case AArch64::CPY_ZPmV_B:
    case AArch64::CPY_ZPmV_D:
    case AArch64::CPY_ZPmV_H:
    case AArch64::CPY_ZPmV_S: {
      switch (OpNum) {
      case 2:
        // op: Pg
        return 10;
      case 3:
        // op: Vn
        return 5;
      case 0:
        // op: Zd
        return 0;
      }
      break;
    }
    case AArch64::FCPY_ZPmI_D:
    case AArch64::FCPY_ZPmI_H:
    case AArch64::FCPY_ZPmI_S: {
      switch (OpNum) {
      case 2:
        // op: Pg
        return 16;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: imm8
        return 5;
      }
      break;
    }
    case AArch64::DECP_ZP_D:
    case AArch64::DECP_ZP_H:
    case AArch64::DECP_ZP_S:
    case AArch64::INCP_ZP_D:
    case AArch64::INCP_ZP_H:
    case AArch64::INCP_ZP_S:
    case AArch64::SQDECP_ZP_D:
    case AArch64::SQDECP_ZP_H:
    case AArch64::SQDECP_ZP_S:
    case AArch64::SQINCP_ZP_D:
    case AArch64::SQINCP_ZP_H:
    case AArch64::SQINCP_ZP_S:
    case AArch64::UQDECP_ZP_D:
    case AArch64::UQDECP_ZP_H:
    case AArch64::UQDECP_ZP_S:
    case AArch64::UQINCP_ZP_D:
    case AArch64::UQINCP_ZP_H:
    case AArch64::UQINCP_ZP_S: {
      switch (OpNum) {
      case 2:
        // op: Pm
        return 5;
      case 0:
        // op: Zdn
        return 0;
      }
      break;
    }
    case AArch64::MOPSSETGE:
    case AArch64::MOPSSETGEN:
    case AArch64::MOPSSETGET:
    case AArch64::MOPSSETGETN:
    case AArch64::SETE:
    case AArch64::SETEN:
    case AArch64::SETET:
    case AArch64::SETETN:
    case AArch64::SETGM:
    case AArch64::SETGMN:
    case AArch64::SETGMT:
    case AArch64::SETGMTN:
    case AArch64::SETGP:
    case AArch64::SETGPN:
    case AArch64::SETGPT:
    case AArch64::SETGPTN:
    case AArch64::SETM:
    case AArch64::SETMN:
    case AArch64::SETMT:
    case AArch64::SETMTN:
    case AArch64::SETP:
    case AArch64::SETPN:
    case AArch64::SETPT:
    case AArch64::SETPTN: {
      switch (OpNum) {
      case 2:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      case 4:
        // op: Rm
        return 16;
      }
      break;
    }
    case AArch64::SETGOE:
    case AArch64::SETGOEN:
    case AArch64::SETGOET:
    case AArch64::SETGOETN:
    case AArch64::SETGOM:
    case AArch64::SETGOMN:
    case AArch64::SETGOMT:
    case AArch64::SETGOMTN:
    case AArch64::SETGOP:
    case AArch64::SETGOPN:
    case AArch64::SETGOPT:
    case AArch64::SETGOPTN: {
      switch (OpNum) {
      case 2:
        // op: Rd
        return 0;
      case 3:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::INDEX_IR_B:
    case AArch64::INDEX_IR_D:
    case AArch64::INDEX_IR_H:
    case AArch64::INDEX_IR_S: {
      switch (OpNum) {
      case 2:
        // op: Rm
        return 16;
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: imm5
        return 5;
      }
      break;
    }
    case AArch64::INSR_ZR_B:
    case AArch64::INSR_ZR_D:
    case AArch64::INSR_ZR_H:
    case AArch64::INSR_ZR_S: {
      switch (OpNum) {
      case 2:
        // op: Rm
        return 5;
      case 0:
        // op: Zdn
        return 0;
      }
      break;
    }
    case AArch64::PRFB_PRI:
    case AArch64::PRFD_PRI:
    case AArch64::PRFH_PRI:
    case AArch64::PRFW_PRI: {
      switch (OpNum) {
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: Pg
        return 10;
      case 3:
        // op: imm6
        return 16;
      case 0:
        // op: prfop
        return 0;
      }
      break;
    }
    case AArch64::LDG:
    case AArch64::ST2GPostIndex:
    case AArch64::ST2GPreIndex:
    case AArch64::STGPostIndex:
    case AArch64::STGPreIndex:
    case AArch64::STZ2GPostIndex:
    case AArch64::STZ2GPreIndex:
    case AArch64::STZGPostIndex:
    case AArch64::STZGPreIndex: {
      switch (OpNum) {
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: Rt
        return 0;
      case 3:
        // op: offset
        return 12;
      }
      break;
    }
    case AArch64::MOVA_VG2_MXI2Z: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 3:
        // op: imm
        return 0;
      case 4:
        // op: Zn
        return 6;
      }
      break;
    }
    case AArch64::MOVA_VG4_MXI4Z: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 3:
        // op: imm
        return 0;
      case 4:
        // op: Zn
        return 7;
      }
      break;
    }
    case AArch64::MOVA_VG2_2ZMXI: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 3:
        // op: imm
        return 5;
      case 0:
        // op: Zd
        return 1;
      }
      break;
    }
    case AArch64::MOVA_VG4_4ZMXI: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 3:
        // op: imm
        return 5;
      case 0:
        // op: Zd
        return 2;
      }
      break;
    }
    case AArch64::MOVA_MXI2Z_H_D:
    case AArch64::MOVA_MXI2Z_V_D: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 4:
        // op: Zn
        return 6;
      case 0:
        // op: ZAd
        return 0;
      }
      break;
    }
    case AArch64::MOVA_MXI2Z_H_S:
    case AArch64::MOVA_MXI2Z_V_S: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 4:
        // op: Zn
        return 6;
      case 0:
        // op: ZAd
        return 1;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::MOVA_MXI2Z_H_H:
    case AArch64::MOVA_MXI2Z_V_H: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 4:
        // op: Zn
        return 6;
      case 0:
        // op: ZAd
        return 2;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::MOVA_MXI2Z_H_B:
    case AArch64::MOVA_MXI2Z_V_B: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 4:
        // op: Zn
        return 6;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::MOVA_MXI4Z_H_D:
    case AArch64::MOVA_MXI4Z_H_S:
    case AArch64::MOVA_MXI4Z_V_D:
    case AArch64::MOVA_MXI4Z_V_S: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 4:
        // op: Zn
        return 7;
      case 0:
        // op: ZAd
        return 0;
      }
      break;
    }
    case AArch64::MOVA_MXI4Z_H_H:
    case AArch64::MOVA_MXI4Z_V_H: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 4:
        // op: Zn
        return 7;
      case 0:
        // op: ZAd
        return 1;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::MOVA_MXI4Z_H_B:
    case AArch64::MOVA_MXI4Z_V_B: {
      switch (OpNum) {
      case 2:
        // op: Rs
        return 13;
      case 4:
        // op: Zn
        return 7;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::LDCLRP:
    case AArch64::LDCLRPA:
    case AArch64::LDCLRPAL:
    case AArch64::LDCLRPL:
    case AArch64::LDSETP:
    case AArch64::LDSETPA:
    case AArch64::LDSETPAL:
    case AArch64::LDSETPL:
    case AArch64::SWPP:
    case AArch64::SWPPA:
    case AArch64::SWPPAL:
    case AArch64::SWPPL: {
      switch (OpNum) {
      case 2:
        // op: Rt
        return 0;
      case 3:
        // op: Rt2
        return 16;
      case 4:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::ZERO_MXI_2Z:
    case AArch64::ZERO_MXI_4Z:
    case AArch64::ZERO_MXI_VG2_2Z:
    case AArch64::ZERO_MXI_VG2_4Z:
    case AArch64::ZERO_MXI_VG2_Z:
    case AArch64::ZERO_MXI_VG4_2Z:
    case AArch64::ZERO_MXI_VG4_4Z:
    case AArch64::ZERO_MXI_VG4_Z: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::ADD_VG2_M2Z_D:
    case AArch64::ADD_VG2_M2Z_S:
    case AArch64::BFADD_VG2_M2Z_H:
    case AArch64::BFSUB_VG2_M2Z_H:
    case AArch64::FADD_VG2_M2Z_D:
    case AArch64::FADD_VG2_M2Z_H:
    case AArch64::FADD_VG2_M2Z_S:
    case AArch64::FSUB_VG2_M2Z_D:
    case AArch64::FSUB_VG2_M2Z_H:
    case AArch64::FSUB_VG2_M2Z_S:
    case AArch64::SUB_VG2_M2Z_D:
    case AArch64::SUB_VG2_M2Z_S: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 3:
        // op: imm3
        return 0;
      case 4:
        // op: Zm
        return 6;
      }
      break;
    }
    case AArch64::ADD_VG4_M4Z_D:
    case AArch64::ADD_VG4_M4Z_S:
    case AArch64::BFADD_VG4_M4Z_H:
    case AArch64::BFSUB_VG4_M4Z_H:
    case AArch64::FADD_VG4_M4Z_D:
    case AArch64::FADD_VG4_M4Z_H:
    case AArch64::FADD_VG4_M4Z_S:
    case AArch64::FSUB_VG4_M4Z_D:
    case AArch64::FSUB_VG4_M4Z_H:
    case AArch64::FSUB_VG4_M4Z_S:
    case AArch64::SUB_VG4_M4Z_D:
    case AArch64::SUB_VG4_M4Z_S: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 3:
        // op: imm3
        return 0;
      case 4:
        // op: Zm
        return 7;
      }
      break;
    }
    case AArch64::INSERT_MXIPZ_H_Q:
    case AArch64::INSERT_MXIPZ_V_Q: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Pg
        return 10;
      case 5:
        // op: Zn
        return 5;
      case 0:
        // op: ZAd
        return 0;
      }
      break;
    }
    case AArch64::INSERT_MXIPZ_H_D:
    case AArch64::INSERT_MXIPZ_V_D: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Pg
        return 10;
      case 5:
        // op: Zn
        return 5;
      case 0:
        // op: ZAd
        return 1;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::INSERT_MXIPZ_H_S:
    case AArch64::INSERT_MXIPZ_V_S: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Pg
        return 10;
      case 5:
        // op: Zn
        return 5;
      case 0:
        // op: ZAd
        return 2;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::INSERT_MXIPZ_H_H:
    case AArch64::INSERT_MXIPZ_V_H: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Pg
        return 10;
      case 5:
        // op: Zn
        return 5;
      case 0:
        // op: ZAd
        return 3;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::INSERT_MXIPZ_H_B:
    case AArch64::INSERT_MXIPZ_V_B: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Pg
        return 10;
      case 5:
        // op: Zn
        return 5;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::BFMLAL_MZZ_HtoS:
    case AArch64::BFMLAL_VG2_M2ZZ_HtoS:
    case AArch64::BFMLAL_VG4_M4ZZ_HtoS:
    case AArch64::BFMLSL_MZZ_HtoS:
    case AArch64::BFMLSL_VG2_M2ZZ_HtoS:
    case AArch64::BFMLSL_VG4_M4ZZ_HtoS:
    case AArch64::FMLAL_MZZ_HtoS:
    case AArch64::FMLAL_VG2_M2ZZ_BtoH:
    case AArch64::FMLAL_VG2_M2ZZ_HtoS:
    case AArch64::FMLAL_VG2_MZZ_BtoH:
    case AArch64::FMLAL_VG4_M4ZZ_BtoH:
    case AArch64::FMLAL_VG4_M4ZZ_HtoS:
    case AArch64::FMLSL_MZZ_HtoS:
    case AArch64::FMLSL_VG2_M2ZZ_HtoS:
    case AArch64::FMLSL_VG4_M4ZZ_HtoS:
    case AArch64::SMLAL_MZZ_HtoS:
    case AArch64::SMLAL_VG2_M2ZZ_HtoS:
    case AArch64::SMLAL_VG4_M4ZZ_HtoS:
    case AArch64::SMLSL_MZZ_HtoS:
    case AArch64::SMLSL_VG2_M2ZZ_HtoS:
    case AArch64::SMLSL_VG4_M4ZZ_HtoS:
    case AArch64::UMLAL_MZZ_HtoS:
    case AArch64::UMLAL_VG2_M2ZZ_HtoS:
    case AArch64::UMLAL_VG4_M4ZZ_HtoS:
    case AArch64::UMLSL_MZZ_HtoS:
    case AArch64::UMLSL_VG2_M2ZZ_HtoS:
    case AArch64::UMLSL_VG4_M4ZZ_HtoS: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 5:
        // op: Zm
        return 16;
      case 4:
        // op: Zn
        return 5;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::BFMLAL_VG2_M2Z2Z_HtoS:
    case AArch64::BFMLSL_VG2_M2Z2Z_HtoS:
    case AArch64::FMLAL_VG2_M2Z2Z_BtoH:
    case AArch64::FMLAL_VG2_M2Z2Z_HtoS:
    case AArch64::FMLSL_VG2_M2Z2Z_HtoS:
    case AArch64::SMLAL_VG2_M2Z2Z_HtoS:
    case AArch64::SMLSL_VG2_M2Z2Z_HtoS:
    case AArch64::UMLAL_VG2_M2Z2Z_HtoS:
    case AArch64::UMLSL_VG2_M2Z2Z_HtoS: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 5:
        // op: Zm
        return 17;
      case 4:
        // op: Zn
        return 6;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::BFMLAL_VG4_M4Z4Z_HtoS:
    case AArch64::BFMLSL_VG4_M4Z4Z_HtoS:
    case AArch64::FMLAL_VG4_M4Z4Z_BtoH:
    case AArch64::FMLAL_VG4_M4Z4Z_HtoS:
    case AArch64::FMLSL_VG4_M4Z4Z_HtoS:
    case AArch64::SMLAL_VG4_M4Z4Z_HtoS:
    case AArch64::SMLSL_VG4_M4Z4Z_HtoS:
    case AArch64::UMLAL_VG4_M4Z4Z_HtoS:
    case AArch64::UMLSL_VG4_M4Z4Z_HtoS: {
      switch (OpNum) {
      case 2:
        // op: Rv
        return 13;
      case 5:
        // op: Zm
        return 18;
      case 4:
        // op: Zn
        return 7;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::INSR_ZV_B:
    case AArch64::INSR_ZV_D:
    case AArch64::INSR_ZV_H:
    case AArch64::INSR_ZV_S: {
      switch (OpNum) {
      case 2:
        // op: Vm
        return 5;
      case 0:
        // op: Zdn
        return 0;
      }
      break;
    }
    case AArch64::LD1i8_POST:
    case AArch64::LD2i8_POST:
    case AArch64::LD3i8_POST:
    case AArch64::LD4i8_POST: {
      switch (OpNum) {
      case 2:
        // op: Vt
        return 0;
      case 4:
        // op: Rn
        return 5;
      case 3:
        // op: idx
        return 10;
      case 5:
        // op: Xm
        return 16;
      }
      break;
    }
    case AArch64::LD1i16_POST:
    case AArch64::LD2i16_POST:
    case AArch64::LD3i16_POST:
    case AArch64::LD4i16_POST: {
      switch (OpNum) {
      case 2:
        // op: Vt
        return 0;
      case 4:
        // op: Rn
        return 5;
      case 3:
        // op: idx
        return 11;
      case 5:
        // op: Xm
        return 16;
      }
      break;
    }
    case AArch64::LD1i32_POST:
    case AArch64::LD2i32_POST:
    case AArch64::LD3i32_POST:
    case AArch64::LD4i32_POST: {
      switch (OpNum) {
      case 2:
        // op: Vt
        return 0;
      case 4:
        // op: Rn
        return 5;
      case 3:
        // op: idx
        return 12;
      case 5:
        // op: Xm
        return 16;
      }
      break;
    }
    case AArch64::LD1i64_POST:
    case AArch64::LD2i64_POST:
    case AArch64::LD3i64_POST:
    case AArch64::LD4i64_POST: {
      switch (OpNum) {
      case 2:
        // op: Vt
        return 0;
      case 4:
        // op: Rn
        return 5;
      case 3:
        // op: idx
        return 30;
      case 5:
        // op: Xm
        return 16;
      }
      break;
    }
    case AArch64::ADD_VG2_2ZZ_B:
    case AArch64::ADD_VG2_2ZZ_D:
    case AArch64::ADD_VG2_2ZZ_H:
    case AArch64::ADD_VG2_2ZZ_S:
    case AArch64::BFMAXNM_VG2_2ZZ_H:
    case AArch64::BFMAX_VG2_2ZZ_H:
    case AArch64::BFMINNM_VG2_2ZZ_H:
    case AArch64::BFMIN_VG2_2ZZ_H:
    case AArch64::BFSCALE_2ZZ:
    case AArch64::FMAXNM_VG2_2ZZ_D:
    case AArch64::FMAXNM_VG2_2ZZ_H:
    case AArch64::FMAXNM_VG2_2ZZ_S:
    case AArch64::FMAX_VG2_2ZZ_D:
    case AArch64::FMAX_VG2_2ZZ_H:
    case AArch64::FMAX_VG2_2ZZ_S:
    case AArch64::FMINNM_VG2_2ZZ_D:
    case AArch64::FMINNM_VG2_2ZZ_H:
    case AArch64::FMINNM_VG2_2ZZ_S:
    case AArch64::FMIN_VG2_2ZZ_D:
    case AArch64::FMIN_VG2_2ZZ_H:
    case AArch64::FMIN_VG2_2ZZ_S:
    case AArch64::FSCALE_2ZZ_D:
    case AArch64::FSCALE_2ZZ_H:
    case AArch64::FSCALE_2ZZ_S:
    case AArch64::SMAX_VG2_2ZZ_B:
    case AArch64::SMAX_VG2_2ZZ_D:
    case AArch64::SMAX_VG2_2ZZ_H:
    case AArch64::SMAX_VG2_2ZZ_S:
    case AArch64::SMIN_VG2_2ZZ_B:
    case AArch64::SMIN_VG2_2ZZ_D:
    case AArch64::SMIN_VG2_2ZZ_H:
    case AArch64::SMIN_VG2_2ZZ_S:
    case AArch64::SQDMULH_VG2_2ZZ_B:
    case AArch64::SQDMULH_VG2_2ZZ_D:
    case AArch64::SQDMULH_VG2_2ZZ_H:
    case AArch64::SQDMULH_VG2_2ZZ_S:
    case AArch64::SRSHL_VG2_2ZZ_B:
    case AArch64::SRSHL_VG2_2ZZ_D:
    case AArch64::SRSHL_VG2_2ZZ_H:
    case AArch64::SRSHL_VG2_2ZZ_S:
    case AArch64::UMAX_VG2_2ZZ_B:
    case AArch64::UMAX_VG2_2ZZ_D:
    case AArch64::UMAX_VG2_2ZZ_H:
    case AArch64::UMAX_VG2_2ZZ_S:
    case AArch64::UMIN_VG2_2ZZ_B:
    case AArch64::UMIN_VG2_2ZZ_D:
    case AArch64::UMIN_VG2_2ZZ_H:
    case AArch64::UMIN_VG2_2ZZ_S:
    case AArch64::URSHL_VG2_2ZZ_B:
    case AArch64::URSHL_VG2_2ZZ_D:
    case AArch64::URSHL_VG2_2ZZ_H:
    case AArch64::URSHL_VG2_2ZZ_S: {
      switch (OpNum) {
      case 2:
        // op: Zm
        return 16;
      case 0:
        // op: Zdn
        return 1;
      }
      break;
    }
    case AArch64::ADD_VG4_4ZZ_B:
    case AArch64::ADD_VG4_4ZZ_D:
    case AArch64::ADD_VG4_4ZZ_H:
    case AArch64::ADD_VG4_4ZZ_S:
    case AArch64::BFMAXNM_VG4_4ZZ_H:
    case AArch64::BFMAX_VG4_4ZZ_H:
    case AArch64::BFMINNM_VG4_4ZZ_H:
    case AArch64::BFMIN_VG4_4ZZ_H:
    case AArch64::BFSCALE_4ZZ:
    case AArch64::FMAXNM_VG4_4ZZ_D:
    case AArch64::FMAXNM_VG4_4ZZ_H:
    case AArch64::FMAXNM_VG4_4ZZ_S:
    case AArch64::FMAX_VG4_4ZZ_D:
    case AArch64::FMAX_VG4_4ZZ_H:
    case AArch64::FMAX_VG4_4ZZ_S:
    case AArch64::FMINNM_VG4_4ZZ_D:
    case AArch64::FMINNM_VG4_4ZZ_H:
    case AArch64::FMINNM_VG4_4ZZ_S:
    case AArch64::FMIN_VG4_4ZZ_D:
    case AArch64::FMIN_VG4_4ZZ_H:
    case AArch64::FMIN_VG4_4ZZ_S:
    case AArch64::FSCALE_4ZZ_D:
    case AArch64::FSCALE_4ZZ_H:
    case AArch64::FSCALE_4ZZ_S:
    case AArch64::SMAX_VG4_4ZZ_B:
    case AArch64::SMAX_VG4_4ZZ_D:
    case AArch64::SMAX_VG4_4ZZ_H:
    case AArch64::SMAX_VG4_4ZZ_S:
    case AArch64::SMIN_VG4_4ZZ_B:
    case AArch64::SMIN_VG4_4ZZ_D:
    case AArch64::SMIN_VG4_4ZZ_H:
    case AArch64::SMIN_VG4_4ZZ_S:
    case AArch64::SQDMULH_VG4_4ZZ_B:
    case AArch64::SQDMULH_VG4_4ZZ_D:
    case AArch64::SQDMULH_VG4_4ZZ_H:
    case AArch64::SQDMULH_VG4_4ZZ_S:
    case AArch64::SRSHL_VG4_4ZZ_B:
    case AArch64::SRSHL_VG4_4ZZ_D:
    case AArch64::SRSHL_VG4_4ZZ_H:
    case AArch64::SRSHL_VG4_4ZZ_S:
    case AArch64::UMAX_VG4_4ZZ_B:
    case AArch64::UMAX_VG4_4ZZ_D:
    case AArch64::UMAX_VG4_4ZZ_H:
    case AArch64::UMAX_VG4_4ZZ_S:
    case AArch64::UMIN_VG4_4ZZ_B:
    case AArch64::UMIN_VG4_4ZZ_D:
    case AArch64::UMIN_VG4_4ZZ_H:
    case AArch64::UMIN_VG4_4ZZ_S:
    case AArch64::URSHL_VG4_4ZZ_B:
    case AArch64::URSHL_VG4_4ZZ_D:
    case AArch64::URSHL_VG4_4ZZ_H:
    case AArch64::URSHL_VG4_4ZZ_S: {
      switch (OpNum) {
      case 2:
        // op: Zm
        return 16;
      case 0:
        // op: Zdn
        return 2;
      }
      break;
    }
    case AArch64::PMULL_2ZZZ_Q: {
      switch (OpNum) {
      case 2:
        // op: Zm
        return 16;
      case 1:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 1;
      }
      break;
    }
    case AArch64::BFMAXNM_VG2_2Z2Z_H:
    case AArch64::BFMAX_VG2_2Z2Z_H:
    case AArch64::BFMINNM_VG2_2Z2Z_H:
    case AArch64::BFMIN_VG2_2Z2Z_H:
    case AArch64::BFSCALE_2Z2Z:
    case AArch64::FAMAX_2Z2Z_D:
    case AArch64::FAMAX_2Z2Z_H:
    case AArch64::FAMAX_2Z2Z_S:
    case AArch64::FAMIN_2Z2Z_D:
    case AArch64::FAMIN_2Z2Z_H:
    case AArch64::FAMIN_2Z2Z_S:
    case AArch64::FMAXNM_VG2_2Z2Z_D:
    case AArch64::FMAXNM_VG2_2Z2Z_H:
    case AArch64::FMAXNM_VG2_2Z2Z_S:
    case AArch64::FMAX_VG2_2Z2Z_D:
    case AArch64::FMAX_VG2_2Z2Z_H:
    case AArch64::FMAX_VG2_2Z2Z_S:
    case AArch64::FMINNM_VG2_2Z2Z_D:
    case AArch64::FMINNM_VG2_2Z2Z_H:
    case AArch64::FMINNM_VG2_2Z2Z_S:
    case AArch64::FMIN_VG2_2Z2Z_D:
    case AArch64::FMIN_VG2_2Z2Z_H:
    case AArch64::FMIN_VG2_2Z2Z_S:
    case AArch64::FSCALE_2Z2Z_D:
    case AArch64::FSCALE_2Z2Z_H:
    case AArch64::FSCALE_2Z2Z_S:
    case AArch64::SMAX_VG2_2Z2Z_B:
    case AArch64::SMAX_VG2_2Z2Z_D:
    case AArch64::SMAX_VG2_2Z2Z_H:
    case AArch64::SMAX_VG2_2Z2Z_S:
    case AArch64::SMIN_VG2_2Z2Z_B:
    case AArch64::SMIN_VG2_2Z2Z_D:
    case AArch64::SMIN_VG2_2Z2Z_H:
    case AArch64::SMIN_VG2_2Z2Z_S:
    case AArch64::SQDMULH_VG2_2Z2Z_B:
    case AArch64::SQDMULH_VG2_2Z2Z_D:
    case AArch64::SQDMULH_VG2_2Z2Z_H:
    case AArch64::SQDMULH_VG2_2Z2Z_S:
    case AArch64::SRSHL_VG2_2Z2Z_B:
    case AArch64::SRSHL_VG2_2Z2Z_D:
    case AArch64::SRSHL_VG2_2Z2Z_H:
    case AArch64::SRSHL_VG2_2Z2Z_S:
    case AArch64::UMAX_VG2_2Z2Z_B:
    case AArch64::UMAX_VG2_2Z2Z_D:
    case AArch64::UMAX_VG2_2Z2Z_H:
    case AArch64::UMAX_VG2_2Z2Z_S:
    case AArch64::UMIN_VG2_2Z2Z_B:
    case AArch64::UMIN_VG2_2Z2Z_D:
    case AArch64::UMIN_VG2_2Z2Z_H:
    case AArch64::UMIN_VG2_2Z2Z_S:
    case AArch64::URSHL_VG2_2Z2Z_B:
    case AArch64::URSHL_VG2_2Z2Z_D:
    case AArch64::URSHL_VG2_2Z2Z_H:
    case AArch64::URSHL_VG2_2Z2Z_S: {
      switch (OpNum) {
      case 2:
        // op: Zm
        return 17;
      case 0:
        // op: Zdn
        return 1;
      }
      break;
    }
    case AArch64::BFMAXNM_VG4_4Z2Z_H:
    case AArch64::BFMAX_VG4_4Z2Z_H:
    case AArch64::BFMINNM_VG4_4Z2Z_H:
    case AArch64::BFMIN_VG4_4Z2Z_H:
    case AArch64::BFSCALE_4Z4Z:
    case AArch64::FAMAX_4Z4Z_D:
    case AArch64::FAMAX_4Z4Z_H:
    case AArch64::FAMAX_4Z4Z_S:
    case AArch64::FAMIN_4Z4Z_D:
    case AArch64::FAMIN_4Z4Z_H:
    case AArch64::FAMIN_4Z4Z_S:
    case AArch64::FMAXNM_VG4_4Z4Z_D:
    case AArch64::FMAXNM_VG4_4Z4Z_H:
    case AArch64::FMAXNM_VG4_4Z4Z_S:
    case AArch64::FMAX_VG4_4Z4Z_D:
    case AArch64::FMAX_VG4_4Z4Z_H:
    case AArch64::FMAX_VG4_4Z4Z_S:
    case AArch64::FMINNM_VG4_4Z4Z_D:
    case AArch64::FMINNM_VG4_4Z4Z_H:
    case AArch64::FMINNM_VG4_4Z4Z_S:
    case AArch64::FMIN_VG4_4Z4Z_D:
    case AArch64::FMIN_VG4_4Z4Z_H:
    case AArch64::FMIN_VG4_4Z4Z_S:
    case AArch64::FSCALE_4Z4Z_D:
    case AArch64::FSCALE_4Z4Z_H:
    case AArch64::FSCALE_4Z4Z_S:
    case AArch64::SMAX_VG4_4Z4Z_B:
    case AArch64::SMAX_VG4_4Z4Z_D:
    case AArch64::SMAX_VG4_4Z4Z_H:
    case AArch64::SMAX_VG4_4Z4Z_S:
    case AArch64::SMIN_VG4_4Z4Z_B:
    case AArch64::SMIN_VG4_4Z4Z_D:
    case AArch64::SMIN_VG4_4Z4Z_H:
    case AArch64::SMIN_VG4_4Z4Z_S:
    case AArch64::SQDMULH_VG4_4Z4Z_B:
    case AArch64::SQDMULH_VG4_4Z4Z_D:
    case AArch64::SQDMULH_VG4_4Z4Z_H:
    case AArch64::SQDMULH_VG4_4Z4Z_S:
    case AArch64::SRSHL_VG4_4Z4Z_B:
    case AArch64::SRSHL_VG4_4Z4Z_D:
    case AArch64::SRSHL_VG4_4Z4Z_H:
    case AArch64::SRSHL_VG4_4Z4Z_S:
    case AArch64::UMAX_VG4_4Z4Z_B:
    case AArch64::UMAX_VG4_4Z4Z_D:
    case AArch64::UMAX_VG4_4Z4Z_H:
    case AArch64::UMAX_VG4_4Z4Z_S:
    case AArch64::UMIN_VG4_4Z4Z_B:
    case AArch64::UMIN_VG4_4Z4Z_D:
    case AArch64::UMIN_VG4_4Z4Z_H:
    case AArch64::UMIN_VG4_4Z4Z_S:
    case AArch64::URSHL_VG4_4Z4Z_B:
    case AArch64::URSHL_VG4_4Z4Z_D:
    case AArch64::URSHL_VG4_4Z4Z_H:
    case AArch64::URSHL_VG4_4Z4Z_S: {
      switch (OpNum) {
      case 2:
        // op: Zm
        return 18;
      case 0:
        // op: Zdn
        return 2;
      }
      break;
    }
    case AArch64::AESDIMC_2ZZI_B:
    case AArch64::AESD_2ZZI_B:
    case AArch64::AESEMC_2ZZI_B:
    case AArch64::AESE_2ZZI_B: {
      switch (OpNum) {
      case 2:
        // op: Zm
        return 5;
      case 0:
        // op: Zdn
        return 1;
      case 3:
        // op: imm2
        return 19;
      }
      break;
    }
    case AArch64::AESDIMC_4ZZI_B:
    case AArch64::AESD_4ZZI_B:
    case AArch64::AESEMC_4ZZI_B:
    case AArch64::AESE_4ZZI_B: {
      switch (OpNum) {
      case 2:
        // op: Zm
        return 5;
      case 0:
        // op: Zdn
        return 2;
      case 3:
        // op: imm2
        return 19;
      }
      break;
    }
    case AArch64::FADDV_VPZ_D:
    case AArch64::FADDV_VPZ_H:
    case AArch64::FADDV_VPZ_S:
    case AArch64::FMAXNMV_VPZ_D:
    case AArch64::FMAXNMV_VPZ_H:
    case AArch64::FMAXNMV_VPZ_S:
    case AArch64::FMAXV_VPZ_D:
    case AArch64::FMAXV_VPZ_H:
    case AArch64::FMAXV_VPZ_S:
    case AArch64::FMINNMV_VPZ_D:
    case AArch64::FMINNMV_VPZ_H:
    case AArch64::FMINNMV_VPZ_S:
    case AArch64::FMINV_VPZ_D:
    case AArch64::FMINV_VPZ_H:
    case AArch64::FMINV_VPZ_S: {
      switch (OpNum) {
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Vd
        return 0;
      case 1:
        // op: Pg
        return 10;
      }
      break;
    }
    case AArch64::LUTI2_ZTZI_B:
    case AArch64::LUTI2_ZTZI_H:
    case AArch64::LUTI2_ZTZI_S:
    case AArch64::LUTI4_ZTZI_B:
    case AArch64::LUTI4_ZTZI_H:
    case AArch64::LUTI4_ZTZI_S: {
      switch (OpNum) {
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: i
        return 14;
      }
      break;
    }
    case AArch64::LUTI2_S_2ZTZI_B:
    case AArch64::LUTI2_S_2ZTZI_H:
    case AArch64::LUTI4_S_2ZTZI_B:
    case AArch64::LUTI4_S_2ZTZI_H: {
      switch (OpNum) {
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: i
        return 15;
      }
      break;
    }
    case AArch64::LUTI2_S_4ZTZI_B:
    case AArch64::LUTI2_S_4ZTZI_H:
    case AArch64::LUTI4_S_4ZTZI_H: {
      switch (OpNum) {
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: i
        return 16;
      }
      break;
    }
    case AArch64::LUTI2_2ZTZI_B:
    case AArch64::LUTI2_2ZTZI_H:
    case AArch64::LUTI2_2ZTZI_S:
    case AArch64::LUTI4_2ZTZI_B:
    case AArch64::LUTI4_2ZTZI_H:
    case AArch64::LUTI4_2ZTZI_S: {
      switch (OpNum) {
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 1;
      case 3:
        // op: i
        return 15;
      }
      break;
    }
    case AArch64::LUTI2_4ZTZI_B:
    case AArch64::LUTI2_4ZTZI_H:
    case AArch64::LUTI2_4ZTZI_S:
    case AArch64::LUTI4_4ZTZI_H:
    case AArch64::LUTI4_4ZTZI_S: {
      switch (OpNum) {
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 2;
      case 3:
        // op: i
        return 16;
      }
      break;
    }
    case AArch64::LUTI4_S_4ZZT2Z: {
      switch (OpNum) {
      case 2:
        // op: Zn
        return 6;
      case 0:
        // op: Zd
        return 0;
      }
      break;
    }
    case AArch64::LUTI4_4ZZT2Z: {
      switch (OpNum) {
      case 2:
        // op: Zn
        return 6;
      case 0:
        // op: Zd
        return 2;
      }
      break;
    }
    case AArch64::MOVT_TIZ: {
      switch (OpNum) {
      case 2:
        // op: Zt
        return 0;
      case 1:
        // op: off2
        return 12;
      }
      break;
    }
    case AArch64::MOVT_XTI: {
      switch (OpNum) {
      case 2:
        // op: imm3
        return 12;
      case 0:
        // op: Rt
        return 0;
      }
      break;
    }
    case AArch64::SQRSHRU_VG2_Z2ZI_H:
    case AArch64::SQRSHR_VG2_Z2ZI_H:
    case AArch64::UQRSHR_VG2_Z2ZI_H: {
      switch (OpNum) {
      case 2:
        // op: imm4
        return 16;
      case 1:
        // op: Zn
        return 6;
      case 0:
        // op: Zd
        return 0;
      }
      break;
    }
    case AArch64::LDRAAindexed:
    case AArch64::LDRABindexed: {
      switch (OpNum) {
      case 2:
        // op: offset
        return 12;
      case 1:
        // op: Rn
        return 5;
      case 0:
        // op: Rt
        return 0;
      }
      break;
    }
    case AArch64::ADDHA_MPPZ_D:
    case AArch64::ADDHA_MPPZ_S:
    case AArch64::ADDVA_MPPZ_D:
    case AArch64::ADDVA_MPPZ_S: {
      switch (OpNum) {
      case 3:
        // op: Pm
        return 13;
      case 2:
        // op: Pn
        return 10;
      case 4:
        // op: Zn
        return 5;
      case 0:
        // op: ZAda
        return 0;
      }
      break;
    }
    case AArch64::CPYE:
    case AArch64::CPYEN:
    case AArch64::CPYERN:
    case AArch64::CPYERT:
    case AArch64::CPYERTN:
    case AArch64::CPYERTRN:
    case AArch64::CPYERTWN:
    case AArch64::CPYET:
    case AArch64::CPYETN:
    case AArch64::CPYETRN:
    case AArch64::CPYETWN:
    case AArch64::CPYEWN:
    case AArch64::CPYEWT:
    case AArch64::CPYEWTN:
    case AArch64::CPYEWTRN:
    case AArch64::CPYEWTWN:
    case AArch64::CPYFE:
    case AArch64::CPYFEN:
    case AArch64::CPYFERN:
    case AArch64::CPYFERT:
    case AArch64::CPYFERTN:
    case AArch64::CPYFERTRN:
    case AArch64::CPYFERTWN:
    case AArch64::CPYFET:
    case AArch64::CPYFETN:
    case AArch64::CPYFETRN:
    case AArch64::CPYFETWN:
    case AArch64::CPYFEWN:
    case AArch64::CPYFEWT:
    case AArch64::CPYFEWTN:
    case AArch64::CPYFEWTRN:
    case AArch64::CPYFEWTWN:
    case AArch64::CPYFM:
    case AArch64::CPYFMN:
    case AArch64::CPYFMRN:
    case AArch64::CPYFMRT:
    case AArch64::CPYFMRTN:
    case AArch64::CPYFMRTRN:
    case AArch64::CPYFMRTWN:
    case AArch64::CPYFMT:
    case AArch64::CPYFMTN:
    case AArch64::CPYFMTRN:
    case AArch64::CPYFMTWN:
    case AArch64::CPYFMWN:
    case AArch64::CPYFMWT:
    case AArch64::CPYFMWTN:
    case AArch64::CPYFMWTRN:
    case AArch64::CPYFMWTWN:
    case AArch64::CPYFP:
    case AArch64::CPYFPN:
    case AArch64::CPYFPRN:
    case AArch64::CPYFPRT:
    case AArch64::CPYFPRTN:
    case AArch64::CPYFPRTRN:
    case AArch64::CPYFPRTWN:
    case AArch64::CPYFPT:
    case AArch64::CPYFPTN:
    case AArch64::CPYFPTRN:
    case AArch64::CPYFPTWN:
    case AArch64::CPYFPWN:
    case AArch64::CPYFPWT:
    case AArch64::CPYFPWTN:
    case AArch64::CPYFPWTRN:
    case AArch64::CPYFPWTWN:
    case AArch64::CPYM:
    case AArch64::CPYMN:
    case AArch64::CPYMRN:
    case AArch64::CPYMRT:
    case AArch64::CPYMRTN:
    case AArch64::CPYMRTRN:
    case AArch64::CPYMRTWN:
    case AArch64::CPYMT:
    case AArch64::CPYMTN:
    case AArch64::CPYMTRN:
    case AArch64::CPYMTWN:
    case AArch64::CPYMWN:
    case AArch64::CPYMWT:
    case AArch64::CPYMWTN:
    case AArch64::CPYMWTRN:
    case AArch64::CPYMWTWN:
    case AArch64::CPYP:
    case AArch64::CPYPN:
    case AArch64::CPYPRN:
    case AArch64::CPYPRT:
    case AArch64::CPYPRTN:
    case AArch64::CPYPRTRN:
    case AArch64::CPYPRTWN:
    case AArch64::CPYPT:
    case AArch64::CPYPTN:
    case AArch64::CPYPTRN:
    case AArch64::CPYPTWN:
    case AArch64::CPYPWN:
    case AArch64::CPYPWT:
    case AArch64::CPYPWTN:
    case AArch64::CPYPWTRN:
    case AArch64::CPYPWTWN: {
      switch (OpNum) {
      case 3:
        // op: Rd
        return 0;
      case 4:
        // op: Rs
        return 16;
      case 5:
        // op: Rn
        return 5;
      }
      break;
    }
    case AArch64::LD1B_2Z_STRIDED:
    case AArch64::LD1B_4Z_STRIDED:
    case AArch64::LD1D_2Z_STRIDED:
    case AArch64::LD1D_4Z_STRIDED:
    case AArch64::LD1H_2Z_STRIDED:
    case AArch64::LD1H_4Z_STRIDED:
    case AArch64::LD1W_2Z_STRIDED:
    case AArch64::LD1W_4Z_STRIDED:
    case AArch64::LDNT1B_2Z_STRIDED:
    case AArch64::LDNT1B_4Z_STRIDED:
    case AArch64::LDNT1D_2Z_STRIDED:
    case AArch64::LDNT1D_4Z_STRIDED:
    case AArch64::LDNT1H_2Z_STRIDED:
    case AArch64::LDNT1H_4Z_STRIDED:
    case AArch64::LDNT1W_2Z_STRIDED:
    case AArch64::LDNT1W_4Z_STRIDED:
    case AArch64::ST1B_2Z_STRIDED:
    case AArch64::ST1B_4Z_STRIDED:
    case AArch64::ST1D_2Z_STRIDED:
    case AArch64::ST1D_4Z_STRIDED:
    case AArch64::ST1H_2Z_STRIDED:
    case AArch64::ST1H_4Z_STRIDED:
    case AArch64::ST1W_2Z_STRIDED:
    case AArch64::ST1W_4Z_STRIDED:
    case AArch64::STNT1B_2Z_STRIDED:
    case AArch64::STNT1B_4Z_STRIDED:
    case AArch64::STNT1D_2Z_STRIDED:
    case AArch64::STNT1D_4Z_STRIDED:
    case AArch64::STNT1H_2Z_STRIDED:
    case AArch64::STNT1H_4Z_STRIDED:
    case AArch64::STNT1W_2Z_STRIDED:
    case AArch64::STNT1W_4Z_STRIDED: {
      switch (OpNum) {
      case 3:
        // op: Rm
        return 16;
      case 1:
        // op: PNg
        return 10;
      case 2:
        // op: Rn
        return 5;
      case 0:
        // op: Zt
        return 0;
      }
      break;
    }
    case AArch64::PRFB_PRR:
    case AArch64::PRFD_PRR:
    case AArch64::PRFH_PRR:
    case AArch64::PRFW_PRR: {
      switch (OpNum) {
      case 3:
        // op: Rm
        return 16;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: Pg
        return 10;
      case 0:
        // op: prfop
        return 0;
      }
      break;
    }
    case AArch64::MOVAZ_ZMI_H_Q:
    case AArch64::MOVAZ_ZMI_V_Q: {
      switch (OpNum) {
      case 3:
        // op: Rs
        return 13;
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: ZAn
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_ZMI_H_D:
    case AArch64::MOVAZ_ZMI_V_D: {
      switch (OpNum) {
      case 3:
        // op: Rs
        return 13;
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: ZAn
        return 6;
      case 4:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_ZMI_H_S:
    case AArch64::MOVAZ_ZMI_V_S: {
      switch (OpNum) {
      case 3:
        // op: Rs
        return 13;
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: ZAn
        return 7;
      case 4:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_ZMI_H_H:
    case AArch64::MOVAZ_ZMI_V_H: {
      switch (OpNum) {
      case 3:
        // op: Rs
        return 13;
      case 0:
        // op: Zd
        return 0;
      case 1:
        // op: ZAn
        return 8;
      case 4:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_ZMI_H_B:
    case AArch64::MOVAZ_ZMI_V_B: {
      switch (OpNum) {
      case 3:
        // op: Rs
        return 13;
      case 0:
        // op: Zd
        return 0;
      case 4:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::MOVAZ_VG2_2ZMXI: {
      switch (OpNum) {
      case 3:
        // op: Rs
        return 13;
      case 4:
        // op: imm
        return 5;
      case 0:
        // op: Zd
        return 1;
      }
      break;
    }
    case AArch64::MOVAZ_VG4_4ZMXI: {
      switch (OpNum) {
      case 3:
        // op: Rs
        return 13;
      case 4:
        // op: imm
        return 5;
      case 0:
        // op: Zd
        return 2;
      }
      break;
    }
    case AArch64::RCWCLRP:
    case AArch64::RCWCLRPA:
    case AArch64::RCWCLRPAL:
    case AArch64::RCWCLRPL:
    case AArch64::RCWCLRSP:
    case AArch64::RCWCLRSPA:
    case AArch64::RCWCLRSPAL:
    case AArch64::RCWCLRSPL:
    case AArch64::RCWSETP:
    case AArch64::RCWSETPA:
    case AArch64::RCWSETPAL:
    case AArch64::RCWSETPL:
    case AArch64::RCWSETSP:
    case AArch64::RCWSETSPA:
    case AArch64::RCWSETSPAL:
    case AArch64::RCWSETSPL:
    case AArch64::RCWSWPP:
    case AArch64::RCWSWPPA:
    case AArch64::RCWSWPPAL:
    case AArch64::RCWSWPPL:
    case AArch64::RCWSWPSP:
    case AArch64::RCWSWPSPA:
    case AArch64::RCWSWPSPAL:
    case AArch64::RCWSWPSPL: {
      switch (OpNum) {
      case 3:
        // op: Rt2
        return 16;
      case 4:
        // op: Rn
        return 5;
      case 2:
        // op: Rt
        return 0;
      }
      break;
    }
    case AArch64::PSEL_PPPRI_B: {
      switch (OpNum) {
      case 3:
        // op: Rv
        return 16;
      case 1:
        // op: Pn
        return 10;
      case 2:
        // op: Pm
        return 5;
      case 0:
        // op: Pd
        return 0;
      case 4:
        // op: imm
        return 19;
      }
      break;
    }
    case AArch64::PSEL_PPPRI_H: {
      switch (OpNum) {
      case 3:
        // op: Rv
        return 16;
      case 1:
        // op: Pn
        return 10;
      case 2:
        // op: Pm
        return 5;
      case 0:
        // op: Pd
        return 0;
      case 4:
        // op: imm
        return 20;
      }
      break;
    }
    case AArch64::PSEL_PPPRI_S: {
      switch (OpNum) {
      case 3:
        // op: Rv
        return 16;
      case 1:
        // op: Pn
        return 10;
      case 2:
        // op: Pm
        return 5;
      case 0:
        // op: Pd
        return 0;
      case 4:
        // op: imm
        return 22;
      }
      break;
    }
    case AArch64::PSEL_PPPRI_D: {
      switch (OpNum) {
      case 3:
        // op: Rv
        return 16;
      case 1:
        // op: Pn
        return 10;
      case 2:
        // op: Pm
        return 5;
      case 0:
        // op: Pd
        return 0;
      case 4:
        // op: imm
        return 23;
      }
      break;
    }
    case AArch64::BFCLAMP_ZZZ:
    case AArch64::FCLAMP_ZZZ_D:
    case AArch64::FCLAMP_ZZZ_H:
    case AArch64::FCLAMP_ZZZ_S:
    case AArch64::SCLAMP_ZZZ_B:
    case AArch64::SCLAMP_ZZZ_D:
    case AArch64::SCLAMP_ZZZ_H:
    case AArch64::SCLAMP_ZZZ_S:
    case AArch64::UCLAMP_ZZZ_B:
    case AArch64::UCLAMP_ZZZ_D:
    case AArch64::UCLAMP_ZZZ_H:
    case AArch64::UCLAMP_ZZZ_S: {
      switch (OpNum) {
      case 3:
        // op: Zm
        return 16;
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 0;
      }
      break;
    }
    case AArch64::BFCLAMP_VG2_2ZZZ_H:
    case AArch64::FCLAMP_VG2_2Z2Z_D:
    case AArch64::FCLAMP_VG2_2Z2Z_H:
    case AArch64::FCLAMP_VG2_2Z2Z_S:
    case AArch64::SCLAMP_VG2_2Z2Z_B:
    case AArch64::SCLAMP_VG2_2Z2Z_D:
    case AArch64::SCLAMP_VG2_2Z2Z_H:
    case AArch64::SCLAMP_VG2_2Z2Z_S:
    case AArch64::UCLAMP_VG2_2Z2Z_B:
    case AArch64::UCLAMP_VG2_2Z2Z_D:
    case AArch64::UCLAMP_VG2_2Z2Z_H:
    case AArch64::UCLAMP_VG2_2Z2Z_S: {
      switch (OpNum) {
      case 3:
        // op: Zm
        return 16;
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 1;
      }
      break;
    }
    case AArch64::BFCLAMP_VG4_4ZZZ_H:
    case AArch64::FCLAMP_VG4_4Z4Z_D:
    case AArch64::FCLAMP_VG4_4Z4Z_H:
    case AArch64::FCLAMP_VG4_4Z4Z_S:
    case AArch64::SCLAMP_VG4_4Z4Z_B:
    case AArch64::SCLAMP_VG4_4Z4Z_D:
    case AArch64::SCLAMP_VG4_4Z4Z_H:
    case AArch64::SCLAMP_VG4_4Z4Z_S:
    case AArch64::UCLAMP_VG4_4Z4Z_B:
    case AArch64::UCLAMP_VG4_4Z4Z_D:
    case AArch64::UCLAMP_VG4_4Z4Z_H:
    case AArch64::UCLAMP_VG4_4Z4Z_S: {
      switch (OpNum) {
      case 3:
        // op: Zm
        return 16;
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zd
        return 2;
      }
      break;
    }
    case AArch64::PMLAL_2ZZZ_Q: {
      switch (OpNum) {
      case 3:
        // op: Zm
        return 16;
      case 2:
        // op: Zn
        return 5;
      case 0:
        // op: Zda
        return 1;
      }
      break;
    }
    case AArch64::LD1B_2Z_STRIDED_IMM:
    case AArch64::LD1B_4Z_STRIDED_IMM:
    case AArch64::LD1D_2Z_STRIDED_IMM:
    case AArch64::LD1D_4Z_STRIDED_IMM:
    case AArch64::LD1H_2Z_STRIDED_IMM:
    case AArch64::LD1H_4Z_STRIDED_IMM:
    case AArch64::LD1W_2Z_STRIDED_IMM:
    case AArch64::LD1W_4Z_STRIDED_IMM:
    case AArch64::LDNT1B_2Z_STRIDED_IMM:
    case AArch64::LDNT1B_4Z_STRIDED_IMM:
    case AArch64::LDNT1D_2Z_STRIDED_IMM:
    case AArch64::LDNT1D_4Z_STRIDED_IMM:
    case AArch64::LDNT1H_2Z_STRIDED_IMM:
    case AArch64::LDNT1H_4Z_STRIDED_IMM:
    case AArch64::LDNT1W_2Z_STRIDED_IMM:
    case AArch64::LDNT1W_4Z_STRIDED_IMM:
    case AArch64::ST1B_2Z_STRIDED_IMM:
    case AArch64::ST1B_4Z_STRIDED_IMM:
    case AArch64::ST1D_2Z_STRIDED_IMM:
    case AArch64::ST1D_4Z_STRIDED_IMM:
    case AArch64::ST1H_2Z_STRIDED_IMM:
    case AArch64::ST1H_4Z_STRIDED_IMM:
    case AArch64::ST1W_2Z_STRIDED_IMM:
    case AArch64::ST1W_4Z_STRIDED_IMM:
    case AArch64::STNT1B_2Z_STRIDED_IMM:
    case AArch64::STNT1B_4Z_STRIDED_IMM:
    case AArch64::STNT1D_2Z_STRIDED_IMM:
    case AArch64::STNT1D_4Z_STRIDED_IMM:
    case AArch64::STNT1H_2Z_STRIDED_IMM:
    case AArch64::STNT1H_4Z_STRIDED_IMM:
    case AArch64::STNT1W_2Z_STRIDED_IMM:
    case AArch64::STNT1W_4Z_STRIDED_IMM: {
      switch (OpNum) {
      case 3:
        // op: imm4
        return 16;
      case 1:
        // op: PNg
        return 10;
      case 2:
        // op: Rn
        return 5;
      case 0:
        // op: Zt
        return 0;
      }
      break;
    }
    case AArch64::LDRAAwriteback:
    case AArch64::LDRABwriteback: {
      switch (OpNum) {
      case 3:
        // op: offset
        return 12;
      case 2:
        // op: Rn
        return 5;
      case 1:
        // op: Rt
        return 0;
      }
      break;
    }
    case AArch64::SYSPxt:
    case AArch64::SYSxt: {
      switch (OpNum) {
      case 4:
        // op: Rt
        return 0;
      case 0:
        // op: op1
        return 16;
      case 1:
        // op: Cn
        return 12;
      case 2:
        // op: Cm
        return 8;
      case 3:
        // op: op2
        return 5;
      }
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_Q:
    case AArch64::EXTRACT_ZPMXI_V_Q: {
      switch (OpNum) {
      case 4:
        // op: Rv
        return 13;
      case 2:
        // op: Pg
        return 10;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: ZAn
        return 5;
      }
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_D:
    case AArch64::EXTRACT_ZPMXI_V_D: {
      switch (OpNum) {
      case 4:
        // op: Rv
        return 13;
      case 2:
        // op: Pg
        return 10;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: ZAn
        return 6;
      case 5:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_S:
    case AArch64::EXTRACT_ZPMXI_V_S: {
      switch (OpNum) {
      case 4:
        // op: Rv
        return 13;
      case 2:
        // op: Pg
        return 10;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: ZAn
        return 7;
      case 5:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_H:
    case AArch64::EXTRACT_ZPMXI_V_H: {
      switch (OpNum) {
      case 4:
        // op: Rv
        return 13;
      case 2:
        // op: Pg
        return 10;
      case 0:
        // op: Zd
        return 0;
      case 3:
        // op: ZAn
        return 8;
      case 5:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::EXTRACT_ZPMXI_H_B:
    case AArch64::EXTRACT_ZPMXI_V_B: {
      switch (OpNum) {
      case 4:
        // op: Rv
        return 13;
      case 2:
        // op: Pg
        return 10;
      case 0:
        // op: Zd
        return 0;
      case 5:
        // op: imm
        return 5;
      }
      break;
    }
    case AArch64::LD1_MXIPXX_H_Q:
    case AArch64::LD1_MXIPXX_V_Q:
    case AArch64::ST1_MXIPXX_H_Q:
    case AArch64::ST1_MXIPXX_V_Q: {
      switch (OpNum) {
      case 5:
        // op: Rm
        return 16;
      case 1:
        // op: Rv
        return 13;
      case 3:
        // op: Pg
        return 10;
      case 4:
        // op: Rn
        return 5;
      case 0:
        // op: ZAt
        return 0;
      }
      break;
    }
    case AArch64::LD1_MXIPXX_H_D:
    case AArch64::LD1_MXIPXX_V_D:
    case AArch64::ST1_MXIPXX_H_D:
    case AArch64::ST1_MXIPXX_V_D: {
      switch (OpNum) {
      case 5:
        // op: Rm
        return 16;
      case 1:
        // op: Rv
        return 13;
      case 3:
        // op: Pg
        return 10;
      case 4:
        // op: Rn
        return 5;
      case 0:
        // op: ZAt
        return 1;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::LD1_MXIPXX_H_S:
    case AArch64::LD1_MXIPXX_V_S:
    case AArch64::ST1_MXIPXX_H_S:
    case AArch64::ST1_MXIPXX_V_S: {
      switch (OpNum) {
      case 5:
        // op: Rm
        return 16;
      case 1:
        // op: Rv
        return 13;
      case 3:
        // op: Pg
        return 10;
      case 4:
        // op: Rn
        return 5;
      case 0:
        // op: ZAt
        return 2;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::LD1_MXIPXX_H_H:
    case AArch64::LD1_MXIPXX_V_H:
    case AArch64::ST1_MXIPXX_H_H:
    case AArch64::ST1_MXIPXX_V_H: {
      switch (OpNum) {
      case 5:
        // op: Rm
        return 16;
      case 1:
        // op: Rv
        return 13;
      case 3:
        // op: Pg
        return 10;
      case 4:
        // op: Rn
        return 5;
      case 0:
        // op: ZAt
        return 3;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::LD1_MXIPXX_H_B:
    case AArch64::LD1_MXIPXX_V_B:
    case AArch64::ST1_MXIPXX_H_B:
    case AArch64::ST1_MXIPXX_V_B: {
      switch (OpNum) {
      case 5:
        // op: Rm
        return 16;
      case 1:
        // op: Rv
        return 13;
      case 3:
        // op: Pg
        return 10;
      case 4:
        // op: Rn
        return 5;
      case 2:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::FMLALL_MZZ_BtoS:
    case AArch64::FMLALL_VG2_M2ZZ_BtoS:
    case AArch64::FMLALL_VG4_M4ZZ_BtoS:
    case AArch64::SMLALL_MZZ_BtoS:
    case AArch64::SMLALL_MZZ_HtoD:
    case AArch64::SMLALL_VG2_M2ZZ_BtoS:
    case AArch64::SMLALL_VG2_M2ZZ_HtoD:
    case AArch64::SMLALL_VG4_M4ZZ_BtoS:
    case AArch64::SMLALL_VG4_M4ZZ_HtoD:
    case AArch64::SMLSLL_MZZ_BtoS:
    case AArch64::SMLSLL_MZZ_HtoD:
    case AArch64::SMLSLL_VG2_M2ZZ_BtoS:
    case AArch64::SMLSLL_VG2_M2ZZ_HtoD:
    case AArch64::SMLSLL_VG4_M4ZZ_BtoS:
    case AArch64::SMLSLL_VG4_M4ZZ_HtoD:
    case AArch64::SUMLALL_VG2_M2ZZ_BtoS:
    case AArch64::SUMLALL_VG4_M4ZZ_BtoS:
    case AArch64::UMLALL_MZZ_BtoS:
    case AArch64::UMLALL_MZZ_HtoD:
    case AArch64::UMLALL_VG2_M2ZZ_BtoS:
    case AArch64::UMLALL_VG2_M2ZZ_HtoD:
    case AArch64::UMLALL_VG4_M4ZZ_BtoS:
    case AArch64::UMLALL_VG4_M4ZZ_HtoD:
    case AArch64::UMLSLL_MZZ_BtoS:
    case AArch64::UMLSLL_MZZ_HtoD:
    case AArch64::UMLSLL_VG2_M2ZZ_BtoS:
    case AArch64::UMLSLL_VG2_M2ZZ_HtoD:
    case AArch64::UMLSLL_VG4_M4ZZ_BtoS:
    case AArch64::UMLSLL_VG4_M4ZZ_HtoD:
    case AArch64::USMLALL_MZZ_BtoS:
    case AArch64::USMLALL_VG2_M2ZZ_BtoS:
    case AArch64::USMLALL_VG4_M4ZZ_BtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Zn
        return 5;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::BFDOT_VG2_M2ZZI_HtoS:
    case AArch64::BFVDOT_VG2_M2ZZI_HtoS:
    case AArch64::FDOT_VG2_M2ZZI_BtoS:
    case AArch64::FDOT_VG2_M2ZZI_HtoS:
    case AArch64::FMLA_VG2_M2ZZI_S:
    case AArch64::FMLS_VG2_M2ZZI_S:
    case AArch64::FVDOT_VG2_M2ZZI_HtoS:
    case AArch64::SDOT_VG2_M2ZZI_BToS:
    case AArch64::SDOT_VG2_M2ZZI_HToS:
    case AArch64::SUDOT_VG2_M2ZZI_BToS:
    case AArch64::SVDOT_VG2_M2ZZI_HtoS:
    case AArch64::UDOT_VG2_M2ZZI_BToS:
    case AArch64::UDOT_VG2_M2ZZI_HToS:
    case AArch64::USDOT_VG2_M2ZZI_BToS:
    case AArch64::UVDOT_VG2_M2ZZI_HtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Zn
        return 6;
      case 3:
        // op: imm3
        return 0;
      case 6:
        // op: i
        return 10;
      }
      break;
    }
    case AArch64::BFMLA_VG2_M2ZZI:
    case AArch64::BFMLS_VG2_M2ZZI:
    case AArch64::FDOT_VG2_M2ZZI_BtoH:
    case AArch64::FMLA_VG2_M2ZZI_H:
    case AArch64::FMLS_VG2_M2ZZI_H:
    case AArch64::FVDOTB_VG4_M2ZZI_BtoS:
    case AArch64::FVDOTT_VG4_M2ZZI_BtoS:
    case AArch64::FVDOT_VG2_M2ZZI_BtoH: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Zn
        return 6;
      case 3:
        // op: imm3
        return 0;
      case 6:
        // op: i
        return 3;
      }
      break;
    }
    case AArch64::BFDOT_VG4_M4ZZI_HtoS:
    case AArch64::FDOT_VG4_M4ZZI_BtoS:
    case AArch64::FDOT_VG4_M4ZZI_HtoS:
    case AArch64::FMLA_VG4_M4ZZI_S:
    case AArch64::FMLS_VG4_M4ZZI_S:
    case AArch64::SDOT_VG4_M4ZZI_BToS:
    case AArch64::SDOT_VG4_M4ZZI_HToS:
    case AArch64::SUDOT_VG4_M4ZZI_BToS:
    case AArch64::SUVDOT_VG4_M4ZZI_BToS:
    case AArch64::SVDOT_VG4_M4ZZI_BtoS:
    case AArch64::UDOT_VG4_M4ZZI_BtoS:
    case AArch64::UDOT_VG4_M4ZZI_HToS:
    case AArch64::USDOT_VG4_M4ZZI_BToS:
    case AArch64::USVDOT_VG4_M4ZZI_BToS:
    case AArch64::UVDOT_VG4_M4ZZI_BtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Zn
        return 7;
      case 3:
        // op: imm3
        return 0;
      case 6:
        // op: i
        return 10;
      }
      break;
    }
    case AArch64::BFMLA_VG4_M4ZZI:
    case AArch64::BFMLS_VG4_M4ZZI:
    case AArch64::FDOT_VG4_M4ZZI_BtoH:
    case AArch64::FMLA_VG4_M4ZZI_H:
    case AArch64::FMLS_VG4_M4ZZI_H: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Zn
        return 7;
      case 3:
        // op: imm3
        return 0;
      case 6:
        // op: i
        return 3;
      }
      break;
    }
    case AArch64::FMLALL_MZZI_BtoS:
    case AArch64::SMLALL_MZZI_BtoS:
    case AArch64::SMLALL_MZZI_HtoD:
    case AArch64::SMLSLL_MZZI_BtoS:
    case AArch64::SMLSLL_MZZI_HtoD:
    case AArch64::SUMLALL_MZZI_BtoS:
    case AArch64::UMLALL_MZZI_BtoS:
    case AArch64::UMLALL_MZZI_HtoD:
    case AArch64::UMLSLL_MZZI_BtoS:
    case AArch64::UMLSLL_MZZI_HtoD:
    case AArch64::USMLALL_MZZI_BtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i
        return 10;
      case 4:
        // op: Zn
        return 5;
      case 3:
        // op: imm2
        return 0;
      }
      break;
    }
    case AArch64::FMLALL_VG2_M2ZZI_BtoS:
    case AArch64::SMLALL_VG2_M2ZZI_BtoS:
    case AArch64::SMLALL_VG2_M2ZZI_HtoD:
    case AArch64::SMLSLL_VG2_M2ZZI_BtoS:
    case AArch64::SMLSLL_VG2_M2ZZI_HtoD:
    case AArch64::SUMLALL_VG2_M2ZZI_BtoS:
    case AArch64::UMLALL_VG2_M2ZZI_BtoS:
    case AArch64::UMLALL_VG2_M2ZZI_HtoD:
    case AArch64::UMLSLL_VG2_M2ZZI_BtoS:
    case AArch64::UMLSLL_VG2_M2ZZI_HtoD:
    case AArch64::USMLALL_VG2_M2ZZI_BtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i
        return 1;
      case 3:
        // op: imm
        return 0;
      case 4:
        // op: Zn
        return 6;
      }
      break;
    }
    case AArch64::FMLALL_VG4_M4ZZI_BtoS:
    case AArch64::SMLALL_VG4_M4ZZI_BtoS:
    case AArch64::SMLALL_VG4_M4ZZI_HtoD:
    case AArch64::SMLSLL_VG4_M4ZZI_BtoS:
    case AArch64::SMLSLL_VG4_M4ZZI_HtoD:
    case AArch64::SUMLALL_VG4_M4ZZI_BtoS:
    case AArch64::UMLALL_VG4_M4ZZI_BtoS:
    case AArch64::UMLALL_VG4_M4ZZI_HtoD:
    case AArch64::UMLSLL_VG4_M4ZZI_BtoS:
    case AArch64::UMLSLL_VG4_M4ZZI_HtoD:
    case AArch64::USMLALL_VG4_M4ZZI_BtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i
        return 1;
      case 3:
        // op: imm
        return 0;
      case 4:
        // op: Zn
        return 7;
      }
      break;
    }
    case AArch64::FMLAL_VG2_M2ZZI_BtoH: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i
        return 2;
      case 3:
        // op: imm2
        return 0;
      case 4:
        // op: Zn
        return 6;
      }
      break;
    }
    case AArch64::FMLAL_VG4_M4ZZI_BtoH: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i
        return 2;
      case 3:
        // op: imm2
        return 0;
      case 4:
        // op: Zn
        return 7;
      }
      break;
    }
    case AArch64::FMLAL_MZZI_BtoH: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i
        return 3;
      case 4:
        // op: Zn
        return 5;
      case 3:
        // op: imm3
        return 0;
      }
      break;
    }
    case AArch64::FMLA_VG2_M2ZZI_D:
    case AArch64::FMLS_VG2_M2ZZI_D:
    case AArch64::SDOT_VG2_M2ZZI_HtoD:
    case AArch64::UDOT_VG2_M2ZZI_HtoD: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i1
        return 10;
      case 4:
        // op: Zn
        return 6;
      case 3:
        // op: imm3
        return 0;
      }
      break;
    }
    case AArch64::FMLA_VG4_M4ZZI_D:
    case AArch64::FMLS_VG4_M4ZZI_D:
    case AArch64::SDOT_VG4_M4ZZI_HtoD:
    case AArch64::SVDOT_VG4_M4ZZI_HtoD:
    case AArch64::UDOT_VG4_M4ZZI_HtoD:
    case AArch64::UVDOT_VG4_M4ZZI_HtoD: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i1
        return 10;
      case 4:
        // op: Zn
        return 7;
      case 3:
        // op: imm3
        return 0;
      }
      break;
    }
    case AArch64::BFMLAL_MZZI_HtoS:
    case AArch64::BFMLSL_MZZI_HtoS:
    case AArch64::FMLAL_MZZI_HtoS:
    case AArch64::FMLSL_MZZI_HtoS:
    case AArch64::SMLAL_MZZI_HtoS:
    case AArch64::SMLSL_MZZI_HtoS:
    case AArch64::UMLAL_MZZI_HtoS:
    case AArch64::UMLSL_MZZI_HtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i3
        return 10;
      case 4:
        // op: Zn
        return 5;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::BFMLAL_VG2_M2ZZI_HtoS:
    case AArch64::BFMLSL_VG2_M2ZZI_HtoS:
    case AArch64::FMLAL_VG2_M2ZZI_HtoS:
    case AArch64::FMLSL_VG2_M2ZZI_HtoS:
    case AArch64::SMLAL_VG2_M2ZZI_S:
    case AArch64::SMLSL_VG2_M2ZZI_S:
    case AArch64::UMLAL_VG2_M2ZZI_S:
    case AArch64::UMLSL_VG2_M2ZZI_S: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i3
        return 2;
      case 4:
        // op: Zn
        return 6;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::BFMLAL_VG4_M4ZZI_HtoS:
    case AArch64::BFMLSL_VG4_M4ZZI_HtoS:
    case AArch64::FMLAL_VG4_M4ZZI_HtoS:
    case AArch64::FMLSL_VG4_M4ZZI_HtoS:
    case AArch64::SMLAL_VG4_M4ZZI_HtoS:
    case AArch64::SMLSL_VG4_M4ZZI_HtoS:
    case AArch64::UMLAL_VG4_M4ZZI_HtoS:
    case AArch64::UMLSL_VG4_M4ZZI_HtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 2:
        // op: Rv
        return 13;
      case 6:
        // op: i3
        return 2;
      case 4:
        // op: Zn
        return 7;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::BFMOPA_MPPZZ:
    case AArch64::BFMOPA_MPPZZ_H:
    case AArch64::BFMOPS_MPPZZ:
    case AArch64::BFMOPS_MPPZZ_H:
    case AArch64::BMOPA_MPPZZ_S:
    case AArch64::BMOPS_MPPZZ_S:
    case AArch64::FMOPAL_MPPZZ:
    case AArch64::FMOPA_MPPZZ_BtoH:
    case AArch64::FMOPA_MPPZZ_BtoS:
    case AArch64::FMOPA_MPPZZ_D:
    case AArch64::FMOPA_MPPZZ_H:
    case AArch64::FMOPA_MPPZZ_S:
    case AArch64::FMOPSL_MPPZZ:
    case AArch64::FMOPS_MPPZZ_D:
    case AArch64::FMOPS_MPPZZ_H:
    case AArch64::FMOPS_MPPZZ_S:
    case AArch64::SMOPA_MPPZZ_D:
    case AArch64::SMOPA_MPPZZ_HtoS:
    case AArch64::SMOPA_MPPZZ_S:
    case AArch64::SMOPS_MPPZZ_D:
    case AArch64::SMOPS_MPPZZ_HtoS:
    case AArch64::SMOPS_MPPZZ_S:
    case AArch64::SUMOPA_MPPZZ_D:
    case AArch64::SUMOPA_MPPZZ_S:
    case AArch64::SUMOPS_MPPZZ_D:
    case AArch64::SUMOPS_MPPZZ_S:
    case AArch64::UMOPA_MPPZZ_D:
    case AArch64::UMOPA_MPPZZ_HtoS:
    case AArch64::UMOPA_MPPZZ_S:
    case AArch64::UMOPS_MPPZZ_D:
    case AArch64::UMOPS_MPPZZ_HtoS:
    case AArch64::UMOPS_MPPZZ_S:
    case AArch64::USMOPA_MPPZZ_D:
    case AArch64::USMOPA_MPPZZ_S:
    case AArch64::USMOPS_MPPZZ_D:
    case AArch64::USMOPS_MPPZZ_S: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 3:
        // op: Pm
        return 13;
      case 2:
        // op: Pn
        return 10;
      case 4:
        // op: Zn
        return 5;
      case 0:
        // op: ZAda
        return 0;
      }
      break;
    }
    case AArch64::ADD_VG2_M2ZZ_D:
    case AArch64::ADD_VG2_M2ZZ_S:
    case AArch64::ADD_VG4_M4ZZ_D:
    case AArch64::ADD_VG4_M4ZZ_S:
    case AArch64::BFDOT_VG2_M2ZZ_HtoS:
    case AArch64::BFDOT_VG4_M4ZZ_HtoS:
    case AArch64::BFMLA_VG2_M2ZZ:
    case AArch64::BFMLA_VG4_M4ZZ:
    case AArch64::BFMLS_VG2_M2ZZ:
    case AArch64::BFMLS_VG4_M4ZZ:
    case AArch64::FDOT_VG2_M2ZZ_BtoH:
    case AArch64::FDOT_VG2_M2ZZ_BtoS:
    case AArch64::FDOT_VG2_M2ZZ_HtoS:
    case AArch64::FDOT_VG4_M4ZZ_BtoH:
    case AArch64::FDOT_VG4_M4ZZ_BtoS:
    case AArch64::FDOT_VG4_M4ZZ_HtoS:
    case AArch64::FMLA_VG2_M2ZZ_D:
    case AArch64::FMLA_VG2_M2ZZ_H:
    case AArch64::FMLA_VG2_M2ZZ_S:
    case AArch64::FMLA_VG4_M4ZZ_D:
    case AArch64::FMLA_VG4_M4ZZ_H:
    case AArch64::FMLA_VG4_M4ZZ_S:
    case AArch64::FMLS_VG2_M2ZZ_D:
    case AArch64::FMLS_VG2_M2ZZ_H:
    case AArch64::FMLS_VG2_M2ZZ_S:
    case AArch64::FMLS_VG4_M4ZZ_D:
    case AArch64::FMLS_VG4_M4ZZ_H:
    case AArch64::FMLS_VG4_M4ZZ_S:
    case AArch64::SDOT_VG2_M2ZZ_BtoS:
    case AArch64::SDOT_VG2_M2ZZ_HtoD:
    case AArch64::SDOT_VG2_M2ZZ_HtoS:
    case AArch64::SDOT_VG4_M4ZZ_BtoS:
    case AArch64::SDOT_VG4_M4ZZ_HtoD:
    case AArch64::SDOT_VG4_M4ZZ_HtoS:
    case AArch64::SUB_VG2_M2ZZ_D:
    case AArch64::SUB_VG2_M2ZZ_S:
    case AArch64::SUB_VG4_M4ZZ_D:
    case AArch64::SUB_VG4_M4ZZ_S:
    case AArch64::SUDOT_VG2_M2ZZ_BToS:
    case AArch64::SUDOT_VG4_M4ZZ_BToS:
    case AArch64::UDOT_VG2_M2ZZ_BtoS:
    case AArch64::UDOT_VG2_M2ZZ_HtoD:
    case AArch64::UDOT_VG2_M2ZZ_HtoS:
    case AArch64::UDOT_VG4_M4ZZ_BtoS:
    case AArch64::UDOT_VG4_M4ZZ_HtoD:
    case AArch64::UDOT_VG4_M4ZZ_HtoS:
    case AArch64::USDOT_VG2_M2ZZ_BToS:
    case AArch64::USDOT_VG4_M4ZZ_BToS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 16;
      case 4:
        // op: Zn
        return 5;
      case 2:
        // op: Rv
        return 13;
      case 3:
        // op: imm3
        return 0;
      }
      break;
    }
    case AArch64::FMLALL_VG2_M2Z2Z_BtoS:
    case AArch64::SMLALL_VG2_M2Z2Z_BtoS:
    case AArch64::SMLALL_VG2_M2Z2Z_HtoD:
    case AArch64::SMLSLL_VG2_M2Z2Z_BtoS:
    case AArch64::SMLSLL_VG2_M2Z2Z_HtoD:
    case AArch64::UMLALL_VG2_M2Z2Z_BtoS:
    case AArch64::UMLALL_VG2_M2Z2Z_HtoD:
    case AArch64::UMLSLL_VG2_M2Z2Z_BtoS:
    case AArch64::UMLSLL_VG2_M2Z2Z_HtoD:
    case AArch64::USMLALL_VG2_M2Z2Z_BtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 17;
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Zn
        return 6;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::ADD_VG2_M2Z2Z_D:
    case AArch64::ADD_VG2_M2Z2Z_S:
    case AArch64::BFDOT_VG2_M2Z2Z_HtoS:
    case AArch64::BFMLA_VG2_M2Z2Z:
    case AArch64::BFMLS_VG2_M2Z2Z:
    case AArch64::FDOT_VG2_M2Z2Z_BtoH:
    case AArch64::FDOT_VG2_M2Z2Z_BtoS:
    case AArch64::FDOT_VG2_M2Z2Z_HtoS:
    case AArch64::FMLA_VG2_M2Z2Z_D:
    case AArch64::FMLA_VG2_M2Z2Z_H:
    case AArch64::FMLA_VG2_M2Z2Z_S:
    case AArch64::FMLS_VG2_M2Z2Z_D:
    case AArch64::FMLS_VG2_M2Z2Z_H:
    case AArch64::FMLS_VG2_M2Z2Z_S:
    case AArch64::SDOT_VG2_M2Z2Z_BtoS:
    case AArch64::SDOT_VG2_M2Z2Z_HtoD:
    case AArch64::SDOT_VG2_M2Z2Z_HtoS:
    case AArch64::SUB_VG2_M2Z2Z_D:
    case AArch64::SUB_VG2_M2Z2Z_S:
    case AArch64::UDOT_VG2_M2Z2Z_BtoS:
    case AArch64::UDOT_VG2_M2Z2Z_HtoD:
    case AArch64::UDOT_VG2_M2Z2Z_HtoS:
    case AArch64::USDOT_VG2_M2Z2Z_BToS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 17;
      case 4:
        // op: Zn
        return 6;
      case 2:
        // op: Rv
        return 13;
      case 3:
        // op: imm3
        return 0;
      }
      break;
    }
    case AArch64::FMLALL_VG4_M4Z4Z_BtoS:
    case AArch64::SMLALL_VG4_M4Z4Z_BtoS:
    case AArch64::SMLALL_VG4_M4Z4Z_HtoD:
    case AArch64::SMLSLL_VG4_M4Z4Z_BtoS:
    case AArch64::SMLSLL_VG4_M4Z4Z_HtoD:
    case AArch64::UMLALL_VG4_M4Z4Z_BtoS:
    case AArch64::UMLALL_VG4_M4Z4Z_HtoD:
    case AArch64::UMLSLL_VG4_M4Z4Z_BtoS:
    case AArch64::UMLSLL_VG4_M4Z4Z_HtoD:
    case AArch64::USMLALL_VG4_M4Z4Z_BtoS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 18;
      case 2:
        // op: Rv
        return 13;
      case 4:
        // op: Zn
        return 7;
      case 3:
        // op: imm
        return 0;
      }
      break;
    }
    case AArch64::ADD_VG4_M4Z4Z_D:
    case AArch64::ADD_VG4_M4Z4Z_S:
    case AArch64::BFDOT_VG4_M4Z4Z_HtoS:
    case AArch64::BFMLA_VG4_M4Z4Z:
    case AArch64::BFMLS_VG4_M4Z4Z:
    case AArch64::FDOT_VG4_M4Z4Z_BtoH:
    case AArch64::FDOT_VG4_M4Z4Z_BtoS:
    case AArch64::FDOT_VG4_M4Z4Z_HtoS:
    case AArch64::FMLA_VG4_M4Z4Z_D:
    case AArch64::FMLA_VG4_M4Z4Z_H:
    case AArch64::FMLA_VG4_M4Z4Z_S:
    case AArch64::FMLS_VG4_M4Z4Z_D:
    case AArch64::FMLS_VG4_M4Z4Z_H:
    case AArch64::FMLS_VG4_M4Z4Z_S:
    case AArch64::SDOT_VG4_M4Z4Z_BtoS:
    case AArch64::SDOT_VG4_M4Z4Z_HtoD:
    case AArch64::SDOT_VG4_M4Z4Z_HtoS:
    case AArch64::SUB_VG4_M4Z4Z_D:
    case AArch64::SUB_VG4_M4Z4Z_S:
    case AArch64::UDOT_VG4_M4Z4Z_BtoS:
    case AArch64::UDOT_VG4_M4Z4Z_HtoD:
    case AArch64::UDOT_VG4_M4Z4Z_HtoS:
    case AArch64::USDOT_VG4_M4Z4Z_BToS: {
      switch (OpNum) {
      case 5:
        // op: Zm
        return 18;
      case 4:
        // op: Zn
        return 7;
      case 2:
        // op: Rv
        return 13;
      case 3:
        // op: imm3
        return 0;
      }
      break;
    }
  default:
    reportUnsupportedInst(MI);
  }
  reportUnsupportedOperand(MI, OpNum);
}

#endif // GET_OPERAND_BIT_OFFSET

