/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

namespace llvm {

extern const MCRegisterClass HexagonMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i1, MVT::Other,
  /* 2 */ MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
  /* 10 */ MVT::i64, MVT::Other,
  /* 12 */ MVT::v64i1, MVT::v64i1, MVT::v32i1, MVT::v16i1, MVT::Other,
  /* 17 */ MVT::v128i1, MVT::v128i1, MVT::v64i1, MVT::v32i1, MVT::Other,
  /* 22 */ MVT::i32, MVT::f32, MVT::v4i8, MVT::v2i16, MVT::Other,
  /* 27 */ MVT::i64, MVT::f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::Other,
  /* 33 */ MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v32f16, MVT::v32bf16, MVT::v16f32, MVT::Other,
  /* 40 */ MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v64f16, MVT::v64bf16, MVT::v32f32, MVT::Other,
  /* 47 */ MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v128f16, MVT::v128bf16, MVT::v64f32, MVT::Other,
  /* 54 */ MVT::Untyped, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "isub_hi", "isub_lo", "subreg_overflow", "vsub_fake", "vsub_hi", "vsub_lo", "wsub_hi", "wsub_lo", "wsub_hi_then_vsub_fake", "wsub_hi_then_vsub_hi", "wsub_hi_then_vsub_lo", "" };

static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
  { 65535, 65535 },
  { 32, 32 },	// isub_hi
  { 0, 32 },	// isub_lo
  { 0, 1 },	// subreg_overflow
  { 65535, 65535 },	// vsub_fake
  { 65535, 65535 },	// vsub_hi
  { 65535, 65535 },	// vsub_lo
  { 65535, 65535 },	// wsub_hi
  { 65535, 65535 },	// wsub_lo
  { 65535, 65535 },	// wsub_hi_then_vsub_fake
  { 65535, 65535 },	// wsub_hi_then_vsub_hi
  { 65535, 65535 },	// wsub_hi_then_vsub_lo
  { 65535, 65535 },
  { 32, 32 },	// isub_hi
  { 0, 32 },	// isub_lo
  { 0, 1 },	// subreg_overflow
  { 65535, 65535 },	// vsub_fake
  { 65535, 65535 },	// vsub_hi
  { 65535, 65535 },	// vsub_lo
  { 65535, 65535 },	// wsub_hi
  { 65535, 65535 },	// wsub_lo
  { 65535, 65535 },	// wsub_hi_then_vsub_fake
  { 65535, 65535 },	// wsub_hi_then_vsub_hi
  { 65535, 65535 },	// wsub_hi_then_vsub_lo
  { 65535, 65535 },
  { 32, 32 },	// isub_hi
  { 0, 32 },	// isub_lo
  { 0, 1 },	// subreg_overflow
  { 65535, 65535 },	// vsub_fake
  { 65535, 65535 },	// vsub_hi
  { 65535, 65535 },	// vsub_lo
  { 65535, 65535 },	// wsub_hi
  { 65535, 65535 },	// wsub_lo
  { 65535, 65535 },	// wsub_hi_then_vsub_fake
  { 65535, 65535 },	// wsub_hi_then_vsub_hi
  { 65535, 65535 },	// wsub_hi_then_vsub_lo
};


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000000000001), // isub_hi
  LaneBitmask(0x0000000000000002), // isub_lo
  LaneBitmask(0x0000000000000004), // subreg_overflow
  LaneBitmask(0x0000000000000008), // vsub_fake
  LaneBitmask(0x0000000000000010), // vsub_hi
  LaneBitmask(0x0000000000000020), // vsub_lo
  LaneBitmask(0x00000000000001C0), // wsub_hi
  LaneBitmask(0x0000000000000038), // wsub_lo
  LaneBitmask(0x0000000000000040), // wsub_hi_then_vsub_fake
  LaneBitmask(0x0000000000000080), // wsub_hi_then_vsub_hi
  LaneBitmask(0x0000000000000100), // wsub_hi_then_vsub_lo
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 1, 1, 0, /*VTLists+*/0 },    // UsrBits
  { 32, 32, 32, /*VTLists+*/8 },    // SysRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GuestRegs
  { 32, 32, 32, /*VTLists+*/22 },    // IntRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GeneralSubRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs
  { 32, 32, 32, /*VTLists+*/8 },    // IntRegsLow8
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_and_V62Regs
  { 32, 32, 32, /*VTLists+*/2 },    // PredRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs_with_isub_hi
  { 32, 32, 32, /*VTLists+*/8 },    // ModRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_with_subreg_overflow
  { 32, 32, 32, /*VTLists+*/8 },    // V65Regs
  { 64, 64, 64, /*VTLists+*/10 },    // SysRegs64
  { 64, 64, 64, /*VTLists+*/27 },    // DoubleRegs
  { 64, 64, 64, /*VTLists+*/10 },    // GuestRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // VectRegRev
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // GeneralDoubleLow8Regs
  { 64, 64, 64, /*VTLists+*/10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_and_V62Regs
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_with_isub_hi_in_ModRegs
  { 64, 512, 512, /*VTLists+*/12 },    // HvxQR
  { 512, 512, 512, /*VTLists+*/33 },    // HvxVR
  { 512, 512, 512, /*VTLists+*/33 },    // HvxVR_and_V65Regs
  { 1024, 1024, 512, /*VTLists+*/40 },    // HvxWR
  { 1024, 1024, 512, /*VTLists+*/40 },    // HvxWR_and_VectRegRev
  { 2048, 2048, 512, /*VTLists+*/54 },    // HvxVQR
  // Mode = 1 (Hvx64)
  { 1, 1, 0, /*VTLists+*/0 },    // UsrBits
  { 32, 32, 32, /*VTLists+*/8 },    // SysRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GuestRegs
  { 32, 32, 32, /*VTLists+*/22 },    // IntRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GeneralSubRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs
  { 32, 32, 32, /*VTLists+*/8 },    // IntRegsLow8
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_and_V62Regs
  { 32, 32, 32, /*VTLists+*/2 },    // PredRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs_with_isub_hi
  { 32, 32, 32, /*VTLists+*/8 },    // ModRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_with_subreg_overflow
  { 32, 32, 32, /*VTLists+*/8 },    // V65Regs
  { 64, 64, 64, /*VTLists+*/10 },    // SysRegs64
  { 64, 64, 64, /*VTLists+*/27 },    // DoubleRegs
  { 64, 64, 64, /*VTLists+*/10 },    // GuestRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // VectRegRev
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // GeneralDoubleLow8Regs
  { 64, 64, 64, /*VTLists+*/10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_and_V62Regs
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_with_isub_hi_in_ModRegs
  { 64, 512, 512, /*VTLists+*/12 },    // HvxQR
  { 512, 512, 512, /*VTLists+*/33 },    // HvxVR
  { 512, 512, 512, /*VTLists+*/33 },    // HvxVR_and_V65Regs
  { 1024, 1024, 512, /*VTLists+*/40 },    // HvxWR
  { 1024, 1024, 512, /*VTLists+*/40 },    // HvxWR_and_VectRegRev
  { 2048, 2048, 512, /*VTLists+*/54 },    // HvxVQR
  // Mode = 2 (Hvx128)
  { 1, 1, 0, /*VTLists+*/0 },    // UsrBits
  { 32, 32, 32, /*VTLists+*/8 },    // SysRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GuestRegs
  { 32, 32, 32, /*VTLists+*/22 },    // IntRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs
  { 32, 32, 32, /*VTLists+*/8 },    // GeneralSubRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs
  { 32, 32, 32, /*VTLists+*/8 },    // IntRegsLow8
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_and_V62Regs
  { 32, 32, 32, /*VTLists+*/2 },    // PredRegs
  { 32, 32, 32, /*VTLists+*/8 },    // V62Regs_with_isub_hi
  { 32, 32, 32, /*VTLists+*/8 },    // ModRegs
  { 32, 32, 32, /*VTLists+*/8 },    // CtrRegs_with_subreg_overflow
  { 32, 32, 32, /*VTLists+*/8 },    // V65Regs
  { 64, 64, 64, /*VTLists+*/10 },    // SysRegs64
  { 64, 64, 64, /*VTLists+*/27 },    // DoubleRegs
  { 64, 64, 64, /*VTLists+*/10 },    // GuestRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // VectRegRev
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64
  { 64, 64, 64, /*VTLists+*/10 },    // GeneralDoubleLow8Regs
  { 64, 64, 64, /*VTLists+*/10 },    // DoubleRegs_with_isub_hi_in_IntRegsLow8
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_and_V62Regs
  { 64, 64, 64, /*VTLists+*/10 },    // CtrRegs64_with_isub_hi_in_ModRegs
  { 128, 1024, 1024, /*VTLists+*/17 },    // HvxQR
  { 1024, 1024, 1024, /*VTLists+*/40 },    // HvxVR
  { 1024, 1024, 1024, /*VTLists+*/40 },    // HvxVR_and_V65Regs
  { 2048, 2048, 1024, /*VTLists+*/47 },    // HvxWR
  { 2048, 2048, 1024, /*VTLists+*/47 },    // HvxWR_and_VectRegRev
  { 4096, 4096, 1024, /*VTLists+*/54 },    // HvxVQR
};
static const uint32_t UsrBitsSubClassMask[] = {
  0x00000001, 
  0x00001000, // subreg_overflow
};

static const uint32_t SysRegsSubClassMask[] = {
  0x00000002, 
  0x00004000, // isub_hi
  0x00004000, // isub_lo
};

static const uint32_t GuestRegsSubClassMask[] = {
  0x00000004, 
  0x00010000, // isub_hi
  0x00010000, // isub_lo
};

static const uint32_t IntRegsSubClassMask[] = {
  0x000000a8, 
  0x00188000, // isub_hi
  0x00188000, // isub_lo
};

static const uint32_t CtrRegsSubClassMask[] = {
  0x00001910, 
  0x00640400, // isub_hi
  0x00640400, // isub_lo
};

static const uint32_t GeneralSubRegsSubClassMask[] = {
  0x000000a0, 
  0x00180000, // isub_hi
  0x00180000, // isub_lo
};

static const uint32_t V62RegsSubClassMask[] = {
  0x00200540, 
  0x00200400, // isub_hi
  0x00200400, // isub_lo
};

static const uint32_t IntRegsLow8SubClassMask[] = {
  0x00000080, 
  0x00100000, // isub_hi
  0x00100000, // isub_lo
};

static const uint32_t CtrRegs_and_V62RegsSubClassMask[] = {
  0x00000100, 
  0x00200400, // isub_hi
  0x00200400, // isub_lo
};

static const uint32_t PredRegsSubClassMask[] = {
  0x00000200, 
};

static const uint32_t V62Regs_with_isub_hiSubClassMask[] = {
  0x00200400, 
};

static const uint32_t ModRegsSubClassMask[] = {
  0x00000800, 
  0x00400000, // isub_hi
  0x00400000, // isub_lo
};

static const uint32_t CtrRegs_with_subreg_overflowSubClassMask[] = {
  0x00001000, 
};

static const uint32_t V65RegsSubClassMask[] = {
  0x02002000, 
};

static const uint32_t SysRegs64SubClassMask[] = {
  0x00004000, 
};

static const uint32_t DoubleRegsSubClassMask[] = {
  0x00188000, 
};

static const uint32_t GuestRegs64SubClassMask[] = {
  0x00010000, 
};

static const uint32_t VectRegRevSubClassMask[] = {
  0x08020000, 
};

static const uint32_t CtrRegs64SubClassMask[] = {
  0x00640000, 
};

static const uint32_t GeneralDoubleLow8RegsSubClassMask[] = {
  0x00180000, 
};

static const uint32_t DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask[] = {
  0x00100000, 
};

static const uint32_t CtrRegs64_and_V62RegsSubClassMask[] = {
  0x00200000, 
};

static const uint32_t CtrRegs64_with_isub_hi_in_ModRegsSubClassMask[] = {
  0x00400000, 
};

static const uint32_t HvxQRSubClassMask[] = {
  0x00800000, 
};

static const uint32_t HvxVRSubClassMask[] = {
  0x03000000, 
  0x1c020000, // vsub_hi
  0x1c020000, // vsub_lo
  0x10000000, // wsub_hi_then_vsub_hi
  0x10000000, // wsub_hi_then_vsub_lo
};

static const uint32_t HvxVR_and_V65RegsSubClassMask[] = {
  0x02000000, 
};

static const uint32_t HvxWRSubClassMask[] = {
  0x0c000000, 
  0x10000000, // wsub_hi
  0x10000000, // wsub_lo
};

static const uint32_t HvxWR_and_VectRegRevSubClassMask[] = {
  0x08000000, 
};

static const uint32_t HvxVQRSubClassMask[] = {
  0x10000000, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 2, 0,
  /* 3 */ 3, 0,
  /* 5 */ 7, 8, 0,
  /* 8 */ 5, 6, 10, 11, 0,
};

static unsigned const GeneralSubRegsSuperclasses[] = {
  Hexagon::IntRegsRegClassID,
};

static unsigned const IntRegsLow8Superclasses[] = {
  Hexagon::IntRegsRegClassID,
  Hexagon::GeneralSubRegsRegClassID,
};

static unsigned const CtrRegs_and_V62RegsSuperclasses[] = {
  Hexagon::CtrRegsRegClassID,
  Hexagon::V62RegsRegClassID,
};

static unsigned const V62Regs_with_isub_hiSuperclasses[] = {
  Hexagon::V62RegsRegClassID,
};

static unsigned const ModRegsSuperclasses[] = {
  Hexagon::CtrRegsRegClassID,
};

static unsigned const CtrRegs_with_subreg_overflowSuperclasses[] = {
  Hexagon::CtrRegsRegClassID,
};

static unsigned const GeneralDoubleLow8RegsSuperclasses[] = {
  Hexagon::DoubleRegsRegClassID,
};

static unsigned const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
  Hexagon::DoubleRegsRegClassID,
  Hexagon::GeneralDoubleLow8RegsRegClassID,
};

static unsigned const CtrRegs64_and_V62RegsSuperclasses[] = {
  Hexagon::V62RegsRegClassID,
  Hexagon::V62Regs_with_isub_hiRegClassID,
  Hexagon::CtrRegs64RegClassID,
};

static unsigned const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
  Hexagon::CtrRegs64RegClassID,
};

static unsigned const HvxVR_and_V65RegsSuperclasses[] = {
  Hexagon::V65RegsRegClassID,
  Hexagon::HvxVRRegClassID,
};

static unsigned const HvxWR_and_VectRegRevSuperclasses[] = {
  Hexagon::VectRegRevRegClassID,
  Hexagon::HvxWRRegClassID,
};


namespace Hexagon {   // Register class instances
  extern const TargetRegisterClass UsrBitsRegClass = {
    &HexagonMCRegisterClasses[UsrBitsRegClassID],
    UsrBitsSubClassMask,
    SuperRegIdxSeqs + 3,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass SysRegsRegClass = {
    &HexagonMCRegisterClasses[SysRegsRegClassID],
    SysRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GuestRegsRegClass = {
    &HexagonMCRegisterClasses[GuestRegsRegClassID],
    GuestRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass IntRegsRegClass = {
    &HexagonMCRegisterClasses[IntRegsRegClassID],
    IntRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass CtrRegsRegClass = {
    &HexagonMCRegisterClasses[CtrRegsRegClassID],
    CtrRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GeneralSubRegsRegClass = {
    &HexagonMCRegisterClasses[GeneralSubRegsRegClassID],
    GeneralSubRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GeneralSubRegsSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass V62RegsRegClass = {
    &HexagonMCRegisterClasses[V62RegsRegClassID],
    V62RegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass IntRegsLow8RegClass = {
    &HexagonMCRegisterClasses[IntRegsLow8RegClassID],
    IntRegsLow8SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    IntRegsLow8Superclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
    &HexagonMCRegisterClasses[CtrRegs_and_V62RegsRegClassID],
    CtrRegs_and_V62RegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CtrRegs_and_V62RegsSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass PredRegsRegClass = {
    &HexagonMCRegisterClasses[PredRegsRegClassID],
    PredRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
    &HexagonMCRegisterClasses[V62Regs_with_isub_hiRegClassID],
    V62Regs_with_isub_hiSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    V62Regs_with_isub_hiSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass ModRegsRegClass = {
    &HexagonMCRegisterClasses[ModRegsRegClassID],
    ModRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    ModRegsSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
    &HexagonMCRegisterClasses[CtrRegs_with_subreg_overflowRegClassID],
    CtrRegs_with_subreg_overflowSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CtrRegs_with_subreg_overflowSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass V65RegsRegClass = {
    &HexagonMCRegisterClasses[V65RegsRegClassID],
    V65RegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass SysRegs64RegClass = {
    &HexagonMCRegisterClasses[SysRegs64RegClassID],
    SysRegs64SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass DoubleRegsRegClass = {
    &HexagonMCRegisterClasses[DoubleRegsRegClassID],
    DoubleRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GuestRegs64RegClass = {
    &HexagonMCRegisterClasses[GuestRegs64RegClassID],
    GuestRegs64SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass VectRegRevRegClass = {
    &HexagonMCRegisterClasses[VectRegRevRegClassID],
    VectRegRevSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000038),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs64RegClass = {
    &HexagonMCRegisterClasses[CtrRegs64RegClassID],
    CtrRegs64SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
    &HexagonMCRegisterClasses[GeneralDoubleLow8RegsRegClassID],
    GeneralDoubleLow8RegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GeneralDoubleLow8RegsSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
    &HexagonMCRegisterClasses[DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID],
    DoubleRegs_with_isub_hi_in_IntRegsLow8SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
    &HexagonMCRegisterClasses[CtrRegs64_and_V62RegsRegClassID],
    CtrRegs64_and_V62RegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    CtrRegs64_and_V62RegsSuperclasses,  3,
    nullptr
  };

  extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
    &HexagonMCRegisterClasses[CtrRegs64_with_isub_hi_in_ModRegsRegClassID],
    CtrRegs64_with_isub_hi_in_ModRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    CtrRegs64_with_isub_hi_in_ModRegsSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass HvxQRRegClass = {
    &HexagonMCRegisterClasses[HvxQRRegClassID],
    HvxQRSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass HvxVRRegClass = {
    &HexagonMCRegisterClasses[HvxVRRegClassID],
    HvxVRSubClassMask,
    SuperRegIdxSeqs + 8,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
    &HexagonMCRegisterClasses[HvxVR_and_V65RegsRegClassID],
    HvxVR_and_V65RegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    HvxVR_and_V65RegsSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass HvxWRRegClass = {
    &HexagonMCRegisterClasses[HvxWRRegClassID],
    HvxWRSubClassMask,
    SuperRegIdxSeqs + 5,
    LaneBitmask(0x0000000000000038),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass HvxWR_and_VectRegRevRegClass = {
    &HexagonMCRegisterClasses[HvxWR_and_VectRegRevRegClassID],
    HvxWR_and_VectRegRevSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000038),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    HvxWR_and_VectRegRevSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass HvxVQRRegClass = {
    &HexagonMCRegisterClasses[HvxVQRRegClassID],
    HvxVQRSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000000000001F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

} // end namespace Hexagon

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &Hexagon::UsrBitsRegClass,
    &Hexagon::SysRegsRegClass,
    &Hexagon::GuestRegsRegClass,
    &Hexagon::IntRegsRegClass,
    &Hexagon::CtrRegsRegClass,
    &Hexagon::GeneralSubRegsRegClass,
    &Hexagon::V62RegsRegClass,
    &Hexagon::IntRegsLow8RegClass,
    &Hexagon::CtrRegs_and_V62RegsRegClass,
    &Hexagon::PredRegsRegClass,
    &Hexagon::V62Regs_with_isub_hiRegClass,
    &Hexagon::ModRegsRegClass,
    &Hexagon::CtrRegs_with_subreg_overflowRegClass,
    &Hexagon::V65RegsRegClass,
    &Hexagon::SysRegs64RegClass,
    &Hexagon::DoubleRegsRegClass,
    &Hexagon::GuestRegs64RegClass,
    &Hexagon::VectRegRevRegClass,
    &Hexagon::CtrRegs64RegClass,
    &Hexagon::GeneralDoubleLow8RegsRegClass,
    &Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass,
    &Hexagon::CtrRegs64_and_V62RegsRegClass,
    &Hexagon::CtrRegs64_with_isub_hi_in_ModRegsRegClass,
    &Hexagon::HvxQRRegClass,
    &Hexagon::HvxVRRegClass,
    &Hexagon::HvxVR_and_V65RegsRegClass,
    &Hexagon::HvxWRRegClass,
    &Hexagon::HvxWR_and_VectRegRevRegClass,
    &Hexagon::HvxVQRRegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, };


static const TargetRegisterInfoDesc HexagonRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

unsigned HexagonGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t RowMap[11] = {
    0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 
  };
  static const uint8_t Rows[2][11] = {
    { 0, 0, 0, Hexagon::wsub_hi_then_vsub_fake, Hexagon::wsub_hi_then_vsub_hi, Hexagon::wsub_hi_then_vsub_lo, 0, 0, 0, 0, 0, },
    { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
  };

  --IdxA; assert(IdxA < 11); (void) IdxA;
  --IdxB; assert(IdxB < 11);
  return Rows[RowMap[IdxA]][IdxB];
}

unsigned HexagonGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t Table[11][11] = {
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
    { 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
    { 0, 0, 0, 0, 0, 0, 0, 0, Hexagon::vsub_fake, Hexagon::vsub_hi, Hexagon::vsub_lo, },
  };

  --IdxA; assert(IdxA < 11);
  --IdxB; assert(IdxB < 11);
  return Table[IdxA][IdxB];
  }

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 }  // Sequence 16
  };
  static const uint8_t CompositeSequences[] = {
    0, // to isub_hi
    2, // to isub_lo
    4, // to subreg_overflow
    6, // to vsub_fake
    8, // to vsub_hi
    10, // to vsub_lo
    6, // to wsub_hi
    0, // to wsub_lo
    12, // to wsub_hi_then_vsub_fake
    14, // to wsub_hi_then_vsub_hi
    16 // to wsub_hi_then_vsub_lo
  };

LaneBitmask HexagonGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask HexagonGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[29][11] = {
    {	// UsrBits
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// SysRegs
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// GuestRegs
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// IntRegs
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// CtrRegs
      0,	// isub_hi
      0,	// isub_lo
      13,	// subreg_overflow -> CtrRegs_with_subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// GeneralSubRegs
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// V62Regs
      11,	// isub_hi -> V62Regs_with_isub_hi
      11,	// isub_lo -> V62Regs_with_isub_hi
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// IntRegsLow8
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// CtrRegs_and_V62Regs
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// PredRegs
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// V62Regs_with_isub_hi
      11,	// isub_hi -> V62Regs_with_isub_hi
      11,	// isub_lo -> V62Regs_with_isub_hi
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// ModRegs
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// CtrRegs_with_subreg_overflow
      0,	// isub_hi
      0,	// isub_lo
      13,	// subreg_overflow -> CtrRegs_with_subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// V65Regs
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// SysRegs64
      15,	// isub_hi -> SysRegs64
      15,	// isub_lo -> SysRegs64
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// DoubleRegs
      16,	// isub_hi -> DoubleRegs
      16,	// isub_lo -> DoubleRegs
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// GuestRegs64
      17,	// isub_hi -> GuestRegs64
      17,	// isub_lo -> GuestRegs64
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// VectRegRev
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      18,	// vsub_fake -> VectRegRev
      18,	// vsub_hi -> VectRegRev
      18,	// vsub_lo -> VectRegRev
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// CtrRegs64
      19,	// isub_hi -> CtrRegs64
      19,	// isub_lo -> CtrRegs64
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// GeneralDoubleLow8Regs
      20,	// isub_hi -> GeneralDoubleLow8Regs
      20,	// isub_lo -> GeneralDoubleLow8Regs
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// DoubleRegs_with_isub_hi_in_IntRegsLow8
      21,	// isub_hi -> DoubleRegs_with_isub_hi_in_IntRegsLow8
      21,	// isub_lo -> DoubleRegs_with_isub_hi_in_IntRegsLow8
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// CtrRegs64_and_V62Regs
      22,	// isub_hi -> CtrRegs64_and_V62Regs
      22,	// isub_lo -> CtrRegs64_and_V62Regs
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// CtrRegs64_with_isub_hi_in_ModRegs
      23,	// isub_hi -> CtrRegs64_with_isub_hi_in_ModRegs
      23,	// isub_lo -> CtrRegs64_with_isub_hi_in_ModRegs
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// HvxQR
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// HvxVR
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// HvxVR_and_V65Regs
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      0,	// vsub_fake
      0,	// vsub_hi
      0,	// vsub_lo
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// HvxWR
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      27,	// vsub_fake -> HvxWR
      27,	// vsub_hi -> HvxWR
      27,	// vsub_lo -> HvxWR
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// HvxWR_and_VectRegRev
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      28,	// vsub_fake -> HvxWR_and_VectRegRev
      28,	// vsub_hi -> HvxWR_and_VectRegRev
      28,	// vsub_lo -> HvxWR_and_VectRegRev
      0,	// wsub_hi
      0,	// wsub_lo
      0,	// wsub_hi_then_vsub_fake
      0,	// wsub_hi_then_vsub_hi
      0,	// wsub_hi_then_vsub_lo
    },
    {	// HvxVQR
      0,	// isub_hi
      0,	// isub_lo
      0,	// subreg_overflow
      29,	// vsub_fake -> HvxVQR
      29,	// vsub_hi -> HvxVQR
      29,	// vsub_lo -> HvxVQR
      29,	// wsub_hi -> HvxVQR
      29,	// wsub_lo -> HvxVQR
      29,	// wsub_hi_then_vsub_fake -> HvxVQR
      29,	// wsub_hi_then_vsub_hi -> HvxVQR
      29,	// wsub_hi_then_vsub_lo -> HvxVQR
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 11 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

const TargetRegisterClass *HexagonGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[29][11] = {
    {	// UsrBits
      0,	// UsrBits:isub_hi
      0,	// UsrBits:isub_lo
      0,	// UsrBits:subreg_overflow
      0,	// UsrBits:vsub_fake
      0,	// UsrBits:vsub_hi
      0,	// UsrBits:vsub_lo
      0,	// UsrBits:wsub_hi
      0,	// UsrBits:wsub_lo
      0,	// UsrBits:wsub_hi_then_vsub_fake
      0,	// UsrBits:wsub_hi_then_vsub_hi
      0,	// UsrBits:wsub_hi_then_vsub_lo
    },
    {	// SysRegs
      0,	// SysRegs:isub_hi
      0,	// SysRegs:isub_lo
      0,	// SysRegs:subreg_overflow
      0,	// SysRegs:vsub_fake
      0,	// SysRegs:vsub_hi
      0,	// SysRegs:vsub_lo
      0,	// SysRegs:wsub_hi
      0,	// SysRegs:wsub_lo
      0,	// SysRegs:wsub_hi_then_vsub_fake
      0,	// SysRegs:wsub_hi_then_vsub_hi
      0,	// SysRegs:wsub_hi_then_vsub_lo
    },
    {	// GuestRegs
      0,	// GuestRegs:isub_hi
      0,	// GuestRegs:isub_lo
      0,	// GuestRegs:subreg_overflow
      0,	// GuestRegs:vsub_fake
      0,	// GuestRegs:vsub_hi
      0,	// GuestRegs:vsub_lo
      0,	// GuestRegs:wsub_hi
      0,	// GuestRegs:wsub_lo
      0,	// GuestRegs:wsub_hi_then_vsub_fake
      0,	// GuestRegs:wsub_hi_then_vsub_hi
      0,	// GuestRegs:wsub_hi_then_vsub_lo
    },
    {	// IntRegs
      0,	// IntRegs:isub_hi
      0,	// IntRegs:isub_lo
      0,	// IntRegs:subreg_overflow
      0,	// IntRegs:vsub_fake
      0,	// IntRegs:vsub_hi
      0,	// IntRegs:vsub_lo
      0,	// IntRegs:wsub_hi
      0,	// IntRegs:wsub_lo
      0,	// IntRegs:wsub_hi_then_vsub_fake
      0,	// IntRegs:wsub_hi_then_vsub_hi
      0,	// IntRegs:wsub_hi_then_vsub_lo
    },
    {	// CtrRegs
      0,	// CtrRegs:isub_hi
      0,	// CtrRegs:isub_lo
      1,	// CtrRegs:subreg_overflow -> UsrBits
      0,	// CtrRegs:vsub_fake
      0,	// CtrRegs:vsub_hi
      0,	// CtrRegs:vsub_lo
      0,	// CtrRegs:wsub_hi
      0,	// CtrRegs:wsub_lo
      0,	// CtrRegs:wsub_hi_then_vsub_fake
      0,	// CtrRegs:wsub_hi_then_vsub_hi
      0,	// CtrRegs:wsub_hi_then_vsub_lo
    },
    {	// GeneralSubRegs
      0,	// GeneralSubRegs:isub_hi
      0,	// GeneralSubRegs:isub_lo
      0,	// GeneralSubRegs:subreg_overflow
      0,	// GeneralSubRegs:vsub_fake
      0,	// GeneralSubRegs:vsub_hi
      0,	// GeneralSubRegs:vsub_lo
      0,	// GeneralSubRegs:wsub_hi
      0,	// GeneralSubRegs:wsub_lo
      0,	// GeneralSubRegs:wsub_hi_then_vsub_fake
      0,	// GeneralSubRegs:wsub_hi_then_vsub_hi
      0,	// GeneralSubRegs:wsub_hi_then_vsub_lo
    },
    {	// V62Regs
      9,	// V62Regs:isub_hi -> CtrRegs_and_V62Regs
      9,	// V62Regs:isub_lo -> CtrRegs_and_V62Regs
      0,	// V62Regs:subreg_overflow
      0,	// V62Regs:vsub_fake
      0,	// V62Regs:vsub_hi
      0,	// V62Regs:vsub_lo
      0,	// V62Regs:wsub_hi
      0,	// V62Regs:wsub_lo
      0,	// V62Regs:wsub_hi_then_vsub_fake
      0,	// V62Regs:wsub_hi_then_vsub_hi
      0,	// V62Regs:wsub_hi_then_vsub_lo
    },
    {	// IntRegsLow8
      0,	// IntRegsLow8:isub_hi
      0,	// IntRegsLow8:isub_lo
      0,	// IntRegsLow8:subreg_overflow
      0,	// IntRegsLow8:vsub_fake
      0,	// IntRegsLow8:vsub_hi
      0,	// IntRegsLow8:vsub_lo
      0,	// IntRegsLow8:wsub_hi
      0,	// IntRegsLow8:wsub_lo
      0,	// IntRegsLow8:wsub_hi_then_vsub_fake
      0,	// IntRegsLow8:wsub_hi_then_vsub_hi
      0,	// IntRegsLow8:wsub_hi_then_vsub_lo
    },
    {	// CtrRegs_and_V62Regs
      0,	// CtrRegs_and_V62Regs:isub_hi
      0,	// CtrRegs_and_V62Regs:isub_lo
      0,	// CtrRegs_and_V62Regs:subreg_overflow
      0,	// CtrRegs_and_V62Regs:vsub_fake
      0,	// CtrRegs_and_V62Regs:vsub_hi
      0,	// CtrRegs_and_V62Regs:vsub_lo
      0,	// CtrRegs_and_V62Regs:wsub_hi
      0,	// CtrRegs_and_V62Regs:wsub_lo
      0,	// CtrRegs_and_V62Regs:wsub_hi_then_vsub_fake
      0,	// CtrRegs_and_V62Regs:wsub_hi_then_vsub_hi
      0,	// CtrRegs_and_V62Regs:wsub_hi_then_vsub_lo
    },
    {	// PredRegs
      0,	// PredRegs:isub_hi
      0,	// PredRegs:isub_lo
      0,	// PredRegs:subreg_overflow
      0,	// PredRegs:vsub_fake
      0,	// PredRegs:vsub_hi
      0,	// PredRegs:vsub_lo
      0,	// PredRegs:wsub_hi
      0,	// PredRegs:wsub_lo
      0,	// PredRegs:wsub_hi_then_vsub_fake
      0,	// PredRegs:wsub_hi_then_vsub_hi
      0,	// PredRegs:wsub_hi_then_vsub_lo
    },
    {	// V62Regs_with_isub_hi
      9,	// V62Regs_with_isub_hi:isub_hi -> CtrRegs_and_V62Regs
      9,	// V62Regs_with_isub_hi:isub_lo -> CtrRegs_and_V62Regs
      0,	// V62Regs_with_isub_hi:subreg_overflow
      0,	// V62Regs_with_isub_hi:vsub_fake
      0,	// V62Regs_with_isub_hi:vsub_hi
      0,	// V62Regs_with_isub_hi:vsub_lo
      0,	// V62Regs_with_isub_hi:wsub_hi
      0,	// V62Regs_with_isub_hi:wsub_lo
      0,	// V62Regs_with_isub_hi:wsub_hi_then_vsub_fake
      0,	// V62Regs_with_isub_hi:wsub_hi_then_vsub_hi
      0,	// V62Regs_with_isub_hi:wsub_hi_then_vsub_lo
    },
    {	// ModRegs
      0,	// ModRegs:isub_hi
      0,	// ModRegs:isub_lo
      0,	// ModRegs:subreg_overflow
      0,	// ModRegs:vsub_fake
      0,	// ModRegs:vsub_hi
      0,	// ModRegs:vsub_lo
      0,	// ModRegs:wsub_hi
      0,	// ModRegs:wsub_lo
      0,	// ModRegs:wsub_hi_then_vsub_fake
      0,	// ModRegs:wsub_hi_then_vsub_hi
      0,	// ModRegs:wsub_hi_then_vsub_lo
    },
    {	// CtrRegs_with_subreg_overflow
      0,	// CtrRegs_with_subreg_overflow:isub_hi
      0,	// CtrRegs_with_subreg_overflow:isub_lo
      1,	// CtrRegs_with_subreg_overflow:subreg_overflow -> UsrBits
      0,	// CtrRegs_with_subreg_overflow:vsub_fake
      0,	// CtrRegs_with_subreg_overflow:vsub_hi
      0,	// CtrRegs_with_subreg_overflow:vsub_lo
      0,	// CtrRegs_with_subreg_overflow:wsub_hi
      0,	// CtrRegs_with_subreg_overflow:wsub_lo
      0,	// CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_fake
      0,	// CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_hi
      0,	// CtrRegs_with_subreg_overflow:wsub_hi_then_vsub_lo
    },
    {	// V65Regs
      0,	// V65Regs:isub_hi
      0,	// V65Regs:isub_lo
      0,	// V65Regs:subreg_overflow
      0,	// V65Regs:vsub_fake
      0,	// V65Regs:vsub_hi
      0,	// V65Regs:vsub_lo
      0,	// V65Regs:wsub_hi
      0,	// V65Regs:wsub_lo
      0,	// V65Regs:wsub_hi_then_vsub_fake
      0,	// V65Regs:wsub_hi_then_vsub_hi
      0,	// V65Regs:wsub_hi_then_vsub_lo
    },
    {	// SysRegs64
      2,	// SysRegs64:isub_hi -> SysRegs
      2,	// SysRegs64:isub_lo -> SysRegs
      0,	// SysRegs64:subreg_overflow
      0,	// SysRegs64:vsub_fake
      0,	// SysRegs64:vsub_hi
      0,	// SysRegs64:vsub_lo
      0,	// SysRegs64:wsub_hi
      0,	// SysRegs64:wsub_lo
      0,	// SysRegs64:wsub_hi_then_vsub_fake
      0,	// SysRegs64:wsub_hi_then_vsub_hi
      0,	// SysRegs64:wsub_hi_then_vsub_lo
    },
    {	// DoubleRegs
      4,	// DoubleRegs:isub_hi -> IntRegs
      4,	// DoubleRegs:isub_lo -> IntRegs
      0,	// DoubleRegs:subreg_overflow
      0,	// DoubleRegs:vsub_fake
      0,	// DoubleRegs:vsub_hi
      0,	// DoubleRegs:vsub_lo
      0,	// DoubleRegs:wsub_hi
      0,	// DoubleRegs:wsub_lo
      0,	// DoubleRegs:wsub_hi_then_vsub_fake
      0,	// DoubleRegs:wsub_hi_then_vsub_hi
      0,	// DoubleRegs:wsub_hi_then_vsub_lo
    },
    {	// GuestRegs64
      3,	// GuestRegs64:isub_hi -> GuestRegs
      3,	// GuestRegs64:isub_lo -> GuestRegs
      0,	// GuestRegs64:subreg_overflow
      0,	// GuestRegs64:vsub_fake
      0,	// GuestRegs64:vsub_hi
      0,	// GuestRegs64:vsub_lo
      0,	// GuestRegs64:wsub_hi
      0,	// GuestRegs64:wsub_lo
      0,	// GuestRegs64:wsub_hi_then_vsub_fake
      0,	// GuestRegs64:wsub_hi_then_vsub_hi
      0,	// GuestRegs64:wsub_hi_then_vsub_lo
    },
    {	// VectRegRev
      0,	// VectRegRev:isub_hi
      0,	// VectRegRev:isub_lo
      0,	// VectRegRev:subreg_overflow
      0,	// VectRegRev:vsub_fake
      25,	// VectRegRev:vsub_hi -> HvxVR
      25,	// VectRegRev:vsub_lo -> HvxVR
      0,	// VectRegRev:wsub_hi
      0,	// VectRegRev:wsub_lo
      0,	// VectRegRev:wsub_hi_then_vsub_fake
      0,	// VectRegRev:wsub_hi_then_vsub_hi
      0,	// VectRegRev:wsub_hi_then_vsub_lo
    },
    {	// CtrRegs64
      5,	// CtrRegs64:isub_hi -> CtrRegs
      5,	// CtrRegs64:isub_lo -> CtrRegs
      0,	// CtrRegs64:subreg_overflow
      0,	// CtrRegs64:vsub_fake
      0,	// CtrRegs64:vsub_hi
      0,	// CtrRegs64:vsub_lo
      0,	// CtrRegs64:wsub_hi
      0,	// CtrRegs64:wsub_lo
      0,	// CtrRegs64:wsub_hi_then_vsub_fake
      0,	// CtrRegs64:wsub_hi_then_vsub_hi
      0,	// CtrRegs64:wsub_hi_then_vsub_lo
    },
    {	// GeneralDoubleLow8Regs
      6,	// GeneralDoubleLow8Regs:isub_hi -> GeneralSubRegs
      6,	// GeneralDoubleLow8Regs:isub_lo -> GeneralSubRegs
      0,	// GeneralDoubleLow8Regs:subreg_overflow
      0,	// GeneralDoubleLow8Regs:vsub_fake
      0,	// GeneralDoubleLow8Regs:vsub_hi
      0,	// GeneralDoubleLow8Regs:vsub_lo
      0,	// GeneralDoubleLow8Regs:wsub_hi
      0,	// GeneralDoubleLow8Regs:wsub_lo
      0,	// GeneralDoubleLow8Regs:wsub_hi_then_vsub_fake
      0,	// GeneralDoubleLow8Regs:wsub_hi_then_vsub_hi
      0,	// GeneralDoubleLow8Regs:wsub_hi_then_vsub_lo
    },
    {	// DoubleRegs_with_isub_hi_in_IntRegsLow8
      8,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_hi -> IntRegsLow8
      8,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:isub_lo -> IntRegsLow8
      0,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:subreg_overflow
      0,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_fake
      0,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_hi
      0,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:vsub_lo
      0,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi
      0,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_lo
      0,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_fake
      0,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_hi
      0,	// DoubleRegs_with_isub_hi_in_IntRegsLow8:wsub_hi_then_vsub_lo
    },
    {	// CtrRegs64_and_V62Regs
      9,	// CtrRegs64_and_V62Regs:isub_hi -> CtrRegs_and_V62Regs
      9,	// CtrRegs64_and_V62Regs:isub_lo -> CtrRegs_and_V62Regs
      0,	// CtrRegs64_and_V62Regs:subreg_overflow
      0,	// CtrRegs64_and_V62Regs:vsub_fake
      0,	// CtrRegs64_and_V62Regs:vsub_hi
      0,	// CtrRegs64_and_V62Regs:vsub_lo
      0,	// CtrRegs64_and_V62Regs:wsub_hi
      0,	// CtrRegs64_and_V62Regs:wsub_lo
      0,	// CtrRegs64_and_V62Regs:wsub_hi_then_vsub_fake
      0,	// CtrRegs64_and_V62Regs:wsub_hi_then_vsub_hi
      0,	// CtrRegs64_and_V62Regs:wsub_hi_then_vsub_lo
    },
    {	// CtrRegs64_with_isub_hi_in_ModRegs
      12,	// CtrRegs64_with_isub_hi_in_ModRegs:isub_hi -> ModRegs
      12,	// CtrRegs64_with_isub_hi_in_ModRegs:isub_lo -> ModRegs
      0,	// CtrRegs64_with_isub_hi_in_ModRegs:subreg_overflow
      0,	// CtrRegs64_with_isub_hi_in_ModRegs:vsub_fake
      0,	// CtrRegs64_with_isub_hi_in_ModRegs:vsub_hi
      0,	// CtrRegs64_with_isub_hi_in_ModRegs:vsub_lo
      0,	// CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi
      0,	// CtrRegs64_with_isub_hi_in_ModRegs:wsub_lo
      0,	// CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_fake
      0,	// CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_hi
      0,	// CtrRegs64_with_isub_hi_in_ModRegs:wsub_hi_then_vsub_lo
    },
    {	// HvxQR
      0,	// HvxQR:isub_hi
      0,	// HvxQR:isub_lo
      0,	// HvxQR:subreg_overflow
      0,	// HvxQR:vsub_fake
      0,	// HvxQR:vsub_hi
      0,	// HvxQR:vsub_lo
      0,	// HvxQR:wsub_hi
      0,	// HvxQR:wsub_lo
      0,	// HvxQR:wsub_hi_then_vsub_fake
      0,	// HvxQR:wsub_hi_then_vsub_hi
      0,	// HvxQR:wsub_hi_then_vsub_lo
    },
    {	// HvxVR
      0,	// HvxVR:isub_hi
      0,	// HvxVR:isub_lo
      0,	// HvxVR:subreg_overflow
      0,	// HvxVR:vsub_fake
      0,	// HvxVR:vsub_hi
      0,	// HvxVR:vsub_lo
      0,	// HvxVR:wsub_hi
      0,	// HvxVR:wsub_lo
      0,	// HvxVR:wsub_hi_then_vsub_fake
      0,	// HvxVR:wsub_hi_then_vsub_hi
      0,	// HvxVR:wsub_hi_then_vsub_lo
    },
    {	// HvxVR_and_V65Regs
      0,	// HvxVR_and_V65Regs:isub_hi
      0,	// HvxVR_and_V65Regs:isub_lo
      0,	// HvxVR_and_V65Regs:subreg_overflow
      0,	// HvxVR_and_V65Regs:vsub_fake
      0,	// HvxVR_and_V65Regs:vsub_hi
      0,	// HvxVR_and_V65Regs:vsub_lo
      0,	// HvxVR_and_V65Regs:wsub_hi
      0,	// HvxVR_and_V65Regs:wsub_lo
      0,	// HvxVR_and_V65Regs:wsub_hi_then_vsub_fake
      0,	// HvxVR_and_V65Regs:wsub_hi_then_vsub_hi
      0,	// HvxVR_and_V65Regs:wsub_hi_then_vsub_lo
    },
    {	// HvxWR
      0,	// HvxWR:isub_hi
      0,	// HvxWR:isub_lo
      0,	// HvxWR:subreg_overflow
      0,	// HvxWR:vsub_fake
      25,	// HvxWR:vsub_hi -> HvxVR
      25,	// HvxWR:vsub_lo -> HvxVR
      0,	// HvxWR:wsub_hi
      0,	// HvxWR:wsub_lo
      0,	// HvxWR:wsub_hi_then_vsub_fake
      0,	// HvxWR:wsub_hi_then_vsub_hi
      0,	// HvxWR:wsub_hi_then_vsub_lo
    },
    {	// HvxWR_and_VectRegRev
      0,	// HvxWR_and_VectRegRev:isub_hi
      0,	// HvxWR_and_VectRegRev:isub_lo
      0,	// HvxWR_and_VectRegRev:subreg_overflow
      0,	// HvxWR_and_VectRegRev:vsub_fake
      25,	// HvxWR_and_VectRegRev:vsub_hi -> HvxVR
      25,	// HvxWR_and_VectRegRev:vsub_lo -> HvxVR
      0,	// HvxWR_and_VectRegRev:wsub_hi
      0,	// HvxWR_and_VectRegRev:wsub_lo
      0,	// HvxWR_and_VectRegRev:wsub_hi_then_vsub_fake
      0,	// HvxWR_and_VectRegRev:wsub_hi_then_vsub_hi
      0,	// HvxWR_and_VectRegRev:wsub_hi_then_vsub_lo
    },
    {	// HvxVQR
      0,	// HvxVQR:isub_hi
      0,	// HvxVQR:isub_lo
      0,	// HvxVQR:subreg_overflow
      0,	// HvxVQR:vsub_fake
      25,	// HvxVQR:vsub_hi -> HvxVR
      25,	// HvxVQR:vsub_lo -> HvxVR
      27,	// HvxVQR:wsub_hi -> HvxWR
      27,	// HvxVQR:wsub_lo -> HvxWR
      0,	// HvxVQR:wsub_hi_then_vsub_fake
      25,	// HvxVQR:wsub_hi_then_vsub_hi -> HvxVR
      25,	// HvxVQR:wsub_hi_then_vsub_lo -> HvxVR
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 11 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &HexagonGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {0, 0},  	// UsrBits
    {0, 0},  	// SysRegs
    {0, 0},  	// GuestRegs
    {1, 32},  	// IntRegs
    {0, 6},  	// CtrRegs
    {1, 16},  	// GeneralSubRegs
    {0, 0},  	// V62Regs
    {1, 8},  	// IntRegsLow8
    {0, 0},  	// CtrRegs_and_V62Regs
    {2, 8},  	// PredRegs
    {0, 0},  	// V62Regs_with_isub_hi
    {1, 2},  	// ModRegs
    {0, 0},  	// CtrRegs_with_subreg_overflow
    {1, 1},  	// V65Regs
    {0, 0},  	// SysRegs64
    {2, 32},  	// DoubleRegs
    {0, 0},  	// GuestRegs64
    {2, 32},  	// VectRegRev
    {0, 6},  	// CtrRegs64
    {2, 16},  	// GeneralDoubleLow8Regs
    {2, 8},  	// DoubleRegs_with_isub_hi_in_IntRegsLow8
    {0, 0},  	// CtrRegs64_and_V62Regs
    {2, 2},  	// CtrRegs64_with_isub_hi_in_ModRegs
    {1, 4},  	// HvxQR
    {1, 33},  	// HvxVR
    {1, 1},  	// HvxVR_and_V65Regs
    {2, 32},  	// HvxWR
    {2, 32},  	// HvxWR_and_VectRegRev
    {4, 32},  	// HvxVQR
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned HexagonGenRegisterInfo::
getRegUnitWeight(MCRegUnit RegUnit) const {
  assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned HexagonGenRegisterInfo::getNumRegPressureSets() const {
  return 8;
}

// Get the name of this register unit pressure set.
const char *HexagonGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "HvxVR_and_V65Regs",
    "ModRegs",
    "HvxQR",
    "IntRegsLow8",
    "PredRegs",
    "GeneralSubRegs",
    "IntRegs",
    "HvxVR",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned HexagonGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    1,  	// 0: HvxVR_and_V65Regs
    2,  	// 1: ModRegs
    4,  	// 2: HvxQR
    8,  	// 3: IntRegsLow8
    8,  	// 4: PredRegs
    16,  	// 5: GeneralSubRegs
    32,  	// 6: IntRegs
    33,  	// 7: HvxVR
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 1, -1,
  /* 2 */ 2, -1,
  /* 4 */ 4, -1,
  /* 6 */ 3, 5, 6, -1,
  /* 10 */ 0, 7, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *HexagonGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    1,1,1,8,1,7,1,6,1,4,1,0,1,1,1,8,1,11,1,7,6,1,1,2,11,10,11,11,11,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *HexagonGenRegisterInfo::
getRegUnitPressureSets(MCRegUnit RegUnit) const {
  assert(static_cast<unsigned>(RegUnit) < 278 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,10,1,1,1,1,1,1,1,1,6,6,6,6,6,6,6,6,8,8,8,8,8,8,8,8,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,4,4,4,4,4,4,4,4,1,1,1,1,2,2,2,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
  return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
}

extern const MCRegisterDesc HexagonRegDesc[];
extern const int16_t HexagonRegDiffLists[];
extern const LaneBitmask HexagonLaneMaskLists[];
extern const char HexagonRegStrings[];
extern const char HexagonRegClassStrings[];
extern const MCPhysReg HexagonRegUnitRoots[][2];
extern const uint16_t HexagonSubRegIdxLists[];
extern const uint16_t HexagonRegEncodingTable[];
// Hexagon Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0Dwarf2L[];
extern const unsigned HexagonDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0Dwarf2L[];
extern const unsigned HexagonEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair HexagonDwarfFlavour0L2Dwarf[];
extern const unsigned HexagonDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair HexagonEHFlavour0L2Dwarf[];
extern const unsigned HexagonEHFlavour0L2DwarfSize;

HexagonGenRegisterInfo::
HexagonGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&HexagonRegInfoDesc, RegisterClasses, RegisterClasses+29,
             SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFFFFB), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(HexagonRegDesc, 398, RA, PC,
                     HexagonMCRegisterClasses, 29,
                     HexagonRegUnitRoots,
                     278,
                     HexagonRegDiffLists,
                     HexagonLaneMaskLists,
                     HexagonRegStrings,
                     HexagonRegClassStrings,
                     HexagonSubRegIdxLists,
                     12,
                     HexagonRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(HexagonDwarfFlavour0Dwarf2L, HexagonDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(HexagonEHFlavour0Dwarf2L, HexagonEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(HexagonDwarfFlavour0L2Dwarf, HexagonDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(HexagonEHFlavour0L2Dwarf, HexagonEHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg HexagonCSR_SaveList[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 };
static const uint32_t HexagonCSR_RegMask[] = { 0x00000000, 0x00000000, 0x0000007e, 0x00000000, 0x0003ffc0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };


ArrayRef<const uint32_t *> HexagonGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    HexagonCSR_RegMask,
  };
  return ArrayRef(Masks);
}

bool HexagonGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool HexagonGenRegisterInfo::
isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
  return
      false;
}

bool HexagonGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool HexagonGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool HexagonGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      false;
}

ArrayRef<const char *> HexagonGenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "HexagonCSR",
  };
  return ArrayRef(Names);
}

const HexagonFrameLowering *
HexagonGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const HexagonFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

