/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass NVPTXMCRegisterClasses[];

namespace NVPTX {
enum : unsigned {
  NoRegister,
  VRDepot = 1,
  ENVREG0 = 2,
  ENVREG1 = 3,
  ENVREG2 = 4,
  ENVREG3 = 5,
  ENVREG4 = 6,
  ENVREG5 = 7,
  ENVREG6 = 8,
  ENVREG7 = 9,
  ENVREG8 = 10,
  ENVREG9 = 11,
  ENVREG10 = 12,
  ENVREG11 = 13,
  ENVREG12 = 14,
  ENVREG13 = 15,
  ENVREG14 = 16,
  ENVREG15 = 17,
  ENVREG16 = 18,
  ENVREG17 = 19,
  ENVREG18 = 20,
  ENVREG19 = 21,
  ENVREG20 = 22,
  ENVREG21 = 23,
  ENVREG22 = 24,
  ENVREG23 = 25,
  ENVREG24 = 26,
  ENVREG25 = 27,
  ENVREG26 = 28,
  ENVREG27 = 29,
  ENVREG28 = 30,
  ENVREG29 = 31,
  ENVREG30 = 32,
  ENVREG31 = 33,
  P0 = 34,
  P1 = 35,
  P2 = 36,
  P3 = 37,
  P4 = 38,
  R0 = 39,
  R1 = 40,
  R2 = 41,
  R3 = 42,
  R4 = 43,
  RL0 = 44,
  RL1 = 45,
  RL2 = 46,
  RL3 = 47,
  RL4 = 48,
  RQ0 = 49,
  RQ1 = 50,
  RQ2 = 51,
  RQ3 = 52,
  RQ4 = 53,
  RS0 = 54,
  RS1 = 55,
  RS2 = 56,
  RS3 = 57,
  RS4 = 58,
  VRFrame32 = 59,
  VRFrame64 = 60,
  VRFrameLocal32 = 61,
  VRFrameLocal64 = 62,
  NUM_TARGET_REGS // 63
};
} // end namespace NVPTX

// Register classes

namespace NVPTX {
enum {
  B1RegClassID = 0,
  B16RegClassID = 1,
  SpecialRegsRegClassID = 2,
  B32RegClassID = 3,
  B32_and_SpecialRegsRegClassID = 4,
  B64RegClassID = 5,
  B128RegClassID = 6,

};
} // end namespace NVPTX

// Register pressure sets enum.
namespace NVPTX {
enum RegisterPressureSets {
  B32_and_SpecialRegs = 0,
  B1 = 1,
  B16 = 2,
  B128 = 3,
  B32 = 4,
  B64 = 5,
  SpecialRegs = 6,
  SpecialRegs_with_B32 = 7,
};
} // end namespace NVPTX

} // end namespace llvm

