/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass ARMMCRegisterClasses[];

namespace ARM {
enum : unsigned {
  NoRegister,
  APSR = 1,
  APSR_NZCV = 2,
  CPSR = 3,
  FPCXTNS = 4,
  FPCXTS = 5,
  FPEXC = 6,
  FPINST = 7,
  FPSCR = 8,
  FPSCR_NZCV = 9,
  FPSCR_NZCVQC = 10,
  FPSCR_RM = 11,
  FPSID = 12,
  ITSTATE = 13,
  LR = 14,
  PC = 15,
  RA_AUTH_CODE = 16,
  SP = 17,
  SPSR = 18,
  VPR = 19,
  ZR = 20,
  D0 = 21,
  D1 = 22,
  D2 = 23,
  D3 = 24,
  D4 = 25,
  D5 = 26,
  D6 = 27,
  D7 = 28,
  D8 = 29,
  D9 = 30,
  D10 = 31,
  D11 = 32,
  D12 = 33,
  D13 = 34,
  D14 = 35,
  D15 = 36,
  D16 = 37,
  D17 = 38,
  D18 = 39,
  D19 = 40,
  D20 = 41,
  D21 = 42,
  D22 = 43,
  D23 = 44,
  D24 = 45,
  D25 = 46,
  D26 = 47,
  D27 = 48,
  D28 = 49,
  D29 = 50,
  D30 = 51,
  D31 = 52,
  FPINST2 = 53,
  MVFR0 = 54,
  MVFR1 = 55,
  MVFR2 = 56,
  P0 = 57,
  Q0 = 58,
  Q1 = 59,
  Q2 = 60,
  Q3 = 61,
  Q4 = 62,
  Q5 = 63,
  Q6 = 64,
  Q7 = 65,
  Q8 = 66,
  Q9 = 67,
  Q10 = 68,
  Q11 = 69,
  Q12 = 70,
  Q13 = 71,
  Q14 = 72,
  Q15 = 73,
  R0 = 74,
  R1 = 75,
  R2 = 76,
  R3 = 77,
  R4 = 78,
  R5 = 79,
  R6 = 80,
  R7 = 81,
  R8 = 82,
  R9 = 83,
  R10 = 84,
  R11 = 85,
  R12 = 86,
  S0 = 87,
  S1 = 88,
  S2 = 89,
  S3 = 90,
  S4 = 91,
  S5 = 92,
  S6 = 93,
  S7 = 94,
  S8 = 95,
  S9 = 96,
  S10 = 97,
  S11 = 98,
  S12 = 99,
  S13 = 100,
  S14 = 101,
  S15 = 102,
  S16 = 103,
  S17 = 104,
  S18 = 105,
  S19 = 106,
  S20 = 107,
  S21 = 108,
  S22 = 109,
  S23 = 110,
  S24 = 111,
  S25 = 112,
  S26 = 113,
  S27 = 114,
  S28 = 115,
  S29 = 116,
  S30 = 117,
  S31 = 118,
  D0_D2 = 119,
  D1_D3 = 120,
  D2_D4 = 121,
  D3_D5 = 122,
  D4_D6 = 123,
  D5_D7 = 124,
  D6_D8 = 125,
  D7_D9 = 126,
  D8_D10 = 127,
  D9_D11 = 128,
  D10_D12 = 129,
  D11_D13 = 130,
  D12_D14 = 131,
  D13_D15 = 132,
  D14_D16 = 133,
  D15_D17 = 134,
  D16_D18 = 135,
  D17_D19 = 136,
  D18_D20 = 137,
  D19_D21 = 138,
  D20_D22 = 139,
  D21_D23 = 140,
  D22_D24 = 141,
  D23_D25 = 142,
  D24_D26 = 143,
  D25_D27 = 144,
  D26_D28 = 145,
  D27_D29 = 146,
  D28_D30 = 147,
  D29_D31 = 148,
  Q0_Q1 = 149,
  Q1_Q2 = 150,
  Q2_Q3 = 151,
  Q3_Q4 = 152,
  Q4_Q5 = 153,
  Q5_Q6 = 154,
  Q6_Q7 = 155,
  Q7_Q8 = 156,
  Q8_Q9 = 157,
  Q9_Q10 = 158,
  Q10_Q11 = 159,
  Q11_Q12 = 160,
  Q12_Q13 = 161,
  Q13_Q14 = 162,
  Q14_Q15 = 163,
  Q0_Q1_Q2_Q3 = 164,
  Q1_Q2_Q3_Q4 = 165,
  Q2_Q3_Q4_Q5 = 166,
  Q3_Q4_Q5_Q6 = 167,
  Q4_Q5_Q6_Q7 = 168,
  Q5_Q6_Q7_Q8 = 169,
  Q6_Q7_Q8_Q9 = 170,
  Q7_Q8_Q9_Q10 = 171,
  Q8_Q9_Q10_Q11 = 172,
  Q9_Q10_Q11_Q12 = 173,
  Q10_Q11_Q12_Q13 = 174,
  Q11_Q12_Q13_Q14 = 175,
  Q12_Q13_Q14_Q15 = 176,
  R0_R1 = 177,
  R2_R3 = 178,
  R4_R5 = 179,
  R6_R7 = 180,
  R8_R9 = 181,
  R10_R11 = 182,
  R12_SP = 183,
  D0_D1_D2 = 184,
  D1_D2_D3 = 185,
  D2_D3_D4 = 186,
  D3_D4_D5 = 187,
  D4_D5_D6 = 188,
  D5_D6_D7 = 189,
  D6_D7_D8 = 190,
  D7_D8_D9 = 191,
  D8_D9_D10 = 192,
  D9_D10_D11 = 193,
  D10_D11_D12 = 194,
  D11_D12_D13 = 195,
  D12_D13_D14 = 196,
  D13_D14_D15 = 197,
  D14_D15_D16 = 198,
  D15_D16_D17 = 199,
  D16_D17_D18 = 200,
  D17_D18_D19 = 201,
  D18_D19_D20 = 202,
  D19_D20_D21 = 203,
  D20_D21_D22 = 204,
  D21_D22_D23 = 205,
  D22_D23_D24 = 206,
  D23_D24_D25 = 207,
  D24_D25_D26 = 208,
  D25_D26_D27 = 209,
  D26_D27_D28 = 210,
  D27_D28_D29 = 211,
  D28_D29_D30 = 212,
  D29_D30_D31 = 213,
  D0_D2_D4 = 214,
  D1_D3_D5 = 215,
  D2_D4_D6 = 216,
  D3_D5_D7 = 217,
  D4_D6_D8 = 218,
  D5_D7_D9 = 219,
  D6_D8_D10 = 220,
  D7_D9_D11 = 221,
  D8_D10_D12 = 222,
  D9_D11_D13 = 223,
  D10_D12_D14 = 224,
  D11_D13_D15 = 225,
  D12_D14_D16 = 226,
  D13_D15_D17 = 227,
  D14_D16_D18 = 228,
  D15_D17_D19 = 229,
  D16_D18_D20 = 230,
  D17_D19_D21 = 231,
  D18_D20_D22 = 232,
  D19_D21_D23 = 233,
  D20_D22_D24 = 234,
  D21_D23_D25 = 235,
  D22_D24_D26 = 236,
  D23_D25_D27 = 237,
  D24_D26_D28 = 238,
  D25_D27_D29 = 239,
  D26_D28_D30 = 240,
  D27_D29_D31 = 241,
  D0_D2_D4_D6 = 242,
  D1_D3_D5_D7 = 243,
  D2_D4_D6_D8 = 244,
  D3_D5_D7_D9 = 245,
  D4_D6_D8_D10 = 246,
  D5_D7_D9_D11 = 247,
  D6_D8_D10_D12 = 248,
  D7_D9_D11_D13 = 249,
  D8_D10_D12_D14 = 250,
  D9_D11_D13_D15 = 251,
  D10_D12_D14_D16 = 252,
  D11_D13_D15_D17 = 253,
  D12_D14_D16_D18 = 254,
  D13_D15_D17_D19 = 255,
  D14_D16_D18_D20 = 256,
  D15_D17_D19_D21 = 257,
  D16_D18_D20_D22 = 258,
  D17_D19_D21_D23 = 259,
  D18_D20_D22_D24 = 260,
  D19_D21_D23_D25 = 261,
  D20_D22_D24_D26 = 262,
  D21_D23_D25_D27 = 263,
  D22_D24_D26_D28 = 264,
  D23_D25_D27_D29 = 265,
  D24_D26_D28_D30 = 266,
  D25_D27_D29_D31 = 267,
  D1_D2 = 268,
  D3_D4 = 269,
  D5_D6 = 270,
  D7_D8 = 271,
  D9_D10 = 272,
  D11_D12 = 273,
  D13_D14 = 274,
  D15_D16 = 275,
  D17_D18 = 276,
  D19_D20 = 277,
  D21_D22 = 278,
  D23_D24 = 279,
  D25_D26 = 280,
  D27_D28 = 281,
  D29_D30 = 282,
  D1_D2_D3_D4 = 283,
  D3_D4_D5_D6 = 284,
  D5_D6_D7_D8 = 285,
  D7_D8_D9_D10 = 286,
  D9_D10_D11_D12 = 287,
  D11_D12_D13_D14 = 288,
  D13_D14_D15_D16 = 289,
  D15_D16_D17_D18 = 290,
  D17_D18_D19_D20 = 291,
  D19_D20_D21_D22 = 292,
  D21_D22_D23_D24 = 293,
  D23_D24_D25_D26 = 294,
  D25_D26_D27_D28 = 295,
  D27_D28_D29_D30 = 296,
  NUM_TARGET_REGS // 297
};
} // end namespace ARM

// Register classes

namespace ARM {
enum {
  HPRRegClassID = 0,
  FPWithVPRRegClassID = 1,
  SPRRegClassID = 2,
  FPWithVPR_with_ssub_0RegClassID = 3,
  GPRRegClassID = 4,
  GPRwithAPSRRegClassID = 5,
  GPRwithZRRegClassID = 6,
  SPR_8RegClassID = 7,
  GPRnopcRegClassID = 8,
  GPRnospRegClassID = 9,
  GPRwithAPSR_NZCVnospRegClassID = 10,
  GPRwithAPSRnospRegClassID = 11,
  GPRwithZRnospRegClassID = 12,
  GPRnoipRegClassID = 13,
  rGPRRegClassID = 14,
  GPRnoip_and_GPRnopcRegClassID = 15,
  GPRnoip_and_GPRnospRegClassID = 16,
  GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID = 17,
  tGPRwithpcRegClassID = 18,
  FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID = 19,
  hGPRRegClassID = 20,
  tGPRRegClassID = 21,
  tGPREvenRegClassID = 22,
  GPRnopc_and_hGPRRegClassID = 23,
  GPRnosp_and_hGPRRegClassID = 24,
  GPRnoip_and_hGPRRegClassID = 25,
  GPRnoip_and_tGPREvenRegClassID = 26,
  GPRnosp_and_GPRnopc_and_hGPRRegClassID = 27,
  tGPROddRegClassID = 28,
  GPRnopc_and_GPRnoip_and_hGPRRegClassID = 29,
  GPRnosp_and_GPRnoip_and_hGPRRegClassID = 30,
  tcGPRRegClassID = 31,
  GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 32,
  hGPR_and_tGPREvenRegClassID = 33,
  tGPR_and_tGPREvenRegClassID = 34,
  tGPR_and_tGPROddRegClassID = 35,
  tcGPRnotr12RegClassID = 36,
  tGPREven_and_tcGPRRegClassID = 37,
  FP_STATUS_REGSRegClassID = 38,
  hGPR_and_GPRnoip_and_tGPREvenRegClassID = 39,
  hGPR_and_tGPROddRegClassID = 40,
  tGPREven_and_tcGPRnotr12RegClassID = 41,
  tGPROdd_and_tcGPRRegClassID = 42,
  CCRRegClassID = 43,
  FPCXTRegsRegClassID = 44,
  GPRlrRegClassID = 45,
  GPRspRegClassID = 46,
  VCCRRegClassID = 47,
  cl_FPSCR_NZCVRegClassID = 48,
  hGPR_and_tGPRwithpcRegClassID = 49,
  hGPR_and_tcGPRRegClassID = 50,
  DPRRegClassID = 51,
  DPR_VFP2RegClassID = 52,
  DPR_8RegClassID = 53,
  GPRPairRegClassID = 54,
  GPRPairnospRegClassID = 55,
  GPRPair_with_gsub_0_in_tGPRRegClassID = 56,
  GPRPair_with_gsub_0_in_hGPRRegClassID = 57,
  GPRPair_with_gsub_0_in_tcGPRRegClassID = 58,
  GPRPair_with_gsub_0_in_tcGPRnotr12RegClassID = 59,
  GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID = 60,
  GPRPair_with_gsub_1_in_GPRspRegClassID = 61,
  DPairSpcRegClassID = 62,
  DPairSpc_with_ssub_0RegClassID = 63,
  DPairSpc_with_ssub_4RegClassID = 64,
  DPairSpc_with_dsub_0_in_DPR_8RegClassID = 65,
  DPairSpc_with_dsub_2_in_DPR_8RegClassID = 66,
  DPairRegClassID = 67,
  DPair_with_ssub_0RegClassID = 68,
  QPRRegClassID = 69,
  DPair_with_ssub_2RegClassID = 70,
  DPair_with_dsub_0_in_DPR_8RegClassID = 71,
  MQPRRegClassID = 72,
  QPR_VFP2RegClassID = 73,
  DPair_with_dsub_1_in_DPR_8RegClassID = 74,
  QPR_8RegClassID = 75,
  DTripleRegClassID = 76,
  DTripleSpcRegClassID = 77,
  DTripleSpc_with_ssub_0RegClassID = 78,
  DTriple_with_ssub_0RegClassID = 79,
  DTriple_with_qsub_0_in_QPRRegClassID = 80,
  DTriple_with_ssub_2RegClassID = 81,
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
  DTripleSpc_with_ssub_4RegClassID = 83,
  DTriple_with_ssub_4RegClassID = 84,
  DTripleSpc_with_ssub_8RegClassID = 85,
  DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 86,
  DTriple_with_dsub_0_in_DPR_8RegClassID = 87,
  DTriple_with_qsub_0_in_MQPRRegClassID = 88,
  DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
  DTriple_with_dsub_1_in_DPR_8RegClassID = 90,
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 91,
  DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID = 92,
  DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 93,
  DTriple_with_dsub_2_in_DPR_8RegClassID = 94,
  DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 95,
  DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 96,
  DTriple_with_qsub_0_in_QPR_8RegClassID = 97,
  DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID = 98,
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 99,
  DQuadSpcRegClassID = 100,
  DQuadSpc_with_ssub_0RegClassID = 101,
  DQuadSpc_with_ssub_4RegClassID = 102,
  DQuadSpc_with_ssub_8RegClassID = 103,
  DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 104,
  DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 105,
  DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 106,
  DQuadRegClassID = 107,
  DQuad_with_ssub_0RegClassID = 108,
  DQuad_with_ssub_2RegClassID = 109,
  QQPRRegClassID = 110,
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 111,
  DQuad_with_ssub_4RegClassID = 112,
  DQuad_with_ssub_6RegClassID = 113,
  DQuad_with_dsub_0_in_DPR_8RegClassID = 114,
  DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 115,
  QQPR_with_ssub_0RegClassID = 116,
  DQuad_with_dsub_1_in_DPR_8RegClassID = 117,
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 118,
  MQQPRRegClassID = 119,
  DQuad_with_dsub_2_in_DPR_8RegClassID = 120,
  DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 121,
  DQuad_with_dsub_3_in_DPR_8RegClassID = 122,
  DQuad_with_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5_in_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 123,
  MQQPR_with_qsub_0_in_QPR_8RegClassID = 124,
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 125,
  MQQPR_with_dsub_2_in_DPR_8RegClassID = 126,
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_in_DTriple_with_qsub_0_in_MQPR_and_DTriple_with_dsub_2_in_DPR_8RegClassID = 127,
  QQQQPRRegClassID = 128,
  QQQQPR_with_ssub_0RegClassID = 129,
  QQQQPR_with_ssub_4RegClassID = 130,
  QQQQPR_with_ssub_8RegClassID = 131,
  MQQQQPRRegClassID = 132,
  MQQQQPR_with_qqsub_0_in_MQQPR_with_qsub_0_in_QPR_8RegClassID = 133,
  MQQQQPR_with_qqsub_0_in_MQQPR_with_dsub_2_in_DPR_8RegClassID = 134,
  MQQQQPR_with_qsub_2_in_QPR_8RegClassID = 135,
  MQQQQPR_with_qqsub_1_in_MQQPR_with_dsub_2_in_DPR_8RegClassID = 136,

};
} // end namespace ARM


// Register alternate name indices

namespace ARM {
enum {
  NoRegAltName,	// 0
  RegNamesRaw,	// 1
  NUM_TARGET_REG_ALT_NAMES = 2
};
} // end namespace ARM


// Subregister indices

namespace ARM {
enum : uint16_t {
  NoSubRegister,
  dsub_0,	// 1
  dsub_1,	// 2
  dsub_2,	// 3
  dsub_3,	// 4
  dsub_4,	// 5
  dsub_5,	// 6
  dsub_6,	// 7
  dsub_7,	// 8
  gsub_0,	// 9
  gsub_1,	// 10
  qqsub_0,	// 11
  qqsub_1,	// 12
  qsub_0,	// 13
  qsub_1,	// 14
  qsub_2,	// 15
  qsub_3,	// 16
  ssub_0,	// 17
  ssub_1,	// 18
  ssub_2,	// 19
  ssub_3,	// 20
  ssub_4,	// 21
  ssub_5,	// 22
  ssub_6,	// 23
  ssub_7,	// 24
  ssub_8,	// 25
  ssub_9,	// 26
  ssub_10,	// 27
  ssub_11,	// 28
  ssub_12,	// 29
  ssub_13,	// 30
  ssub_14,	// 31
  ssub_15,	// 32
  ssub_0_ssub_1_ssub_4_ssub_5,	// 33
  ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5,	// 34
  ssub_2_ssub_3_ssub_6_ssub_7,	// 35
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7,	// 36
  ssub_2_ssub_3_ssub_4_ssub_5,	// 37
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9,	// 38
  ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,	// 39
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5,	// 40
  ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7,	// 41
  ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,	// 42
  ssub_4_ssub_5_ssub_8_ssub_9,	// 43
  ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9,	// 44
  ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13,	// 45
  ssub_6_ssub_7_dsub_5,	// 46
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5,	// 47
  ssub_6_ssub_7_dsub_5_dsub_7,	// 48
  ssub_6_ssub_7_ssub_8_ssub_9,	// 49
  ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13,	// 50
  ssub_8_ssub_9_ssub_12_ssub_13,	// 51
  ssub_8_ssub_9_dsub_5_ssub_12_ssub_13,	// 52
  dsub_5_dsub_7,	// 53
  dsub_5_ssub_12_ssub_13_dsub_7,	// 54
  dsub_5_ssub_12_ssub_13,	// 55
  ssub_4_ssub_5_ssub_6_ssub_7_qsub_2,	// 56
  NUM_TARGET_SUBREGS
};
} // end namespace ARM

// Register pressure sets enum.
namespace ARM {
enum RegisterPressureSets {
  FPCXTRegs = 0,
  GPRlr = 1,
  VCCR = 2,
  hGPR_and_tGPRwithpc = 3,
  cl_FPSCR_NZCV = 4,
  GPRsp = 5,
  tGPROdd = 6,
  tcGPR = 7,
  hGPR = 8,
  tGPROdd_with_tcGPR = 9,
  tGPR = 10,
  tGPR_with_tcGPR = 11,
  tGPREven = 12,
  hGPR_with_tGPREven = 13,
  hGPR_with_tGPROdd = 14,
  hGPR_with_tcGPR = 15,
  tGPR_with_tGPREven = 16,
  GPR = 17,
  GPRwithZR = 18,
  GPRwithAPSR_with_GPRwithZR = 19,
  DQuad_with_dsub_0_in_DPR_8 = 20,
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR = 21,
  HPR = 22,
  DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 23,
  DPair_with_ssub_0 = 24,
  DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 25,
  DPairSpc_with_ssub_0 = 26,
  DQuad_with_ssub_0 = 27,
  DTripleSpc_with_ssub_0 = 28,
  QQQQPR_with_ssub_0 = 29,
  DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 30,
  DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR = 31,
  DTriple_with_qsub_0_in_QPR = 32,
  DPR = 33,
};
} // end namespace ARM

} // end namespace llvm

